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Wed, 21 Oct 2026 07:06:42 -0700 (PDT) Received: from [192.168.226.26] ([178.235.128.140]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-c468a59ac2csm7665066b.51.2026.10.21.07.06.39 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Wed, 21 Oct 2026 07:06:41 -0700 (PDT) Message-ID: <5d3de423-e5e0-41b6-be5e-c1a46e53d570@oss.qualcomm.com> Date: Wed, 21 Oct 2026 16:06:39 +0200 X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Post: List-Help: List-Subscribe: List-Unsubscribe: List-Owner: Precedence: list MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH 3/3] arm64: dts: qcom: glymur-crd: Describe the PCIe M.2 Key B connector To: Krishna Chaitanya Chundru , Manivannan Sadhasivam , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Bartosz Golaszewski , Bjorn Andersson , Konrad Dybcio Cc: linux-pci@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org, linux-arm-msm@vger.kernel.org References: <20261021-pcie6_fix-v1-0-ad37134c35a3@oss.qualcomm.com> <20261021-pcie6_fix-v1-3-ad37134c35a3@oss.qualcomm.com> Content-Language: en-US From: Konrad Dybcio In-Reply-To: <20261021-pcie6_fix-v1-3-ad37134c35a3@oss.qualcomm.com> Content-Type: text/plain; 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Currently the > vreg_wwan supply is described directly on the PCIe6 host bridge. As a > result, the supply follows the PCIe controller power state and is turned > off when the controller is powered down, regardless of the requirements > of the device connected to the slot. [...] > &pcie6 { > - vddpe-3v3-supply = <&vreg_wwan>; > - > pinctrl-0 = <&pcie6_default>; > pinctrl-names = "default"; > > @@ -828,6 +847,12 @@ &pcie6_phy { > &pcie6_port0 { > reset-gpios = <&tlmm 149 GPIO_ACTIVE_LOW>; > wake-gpios = <&tlmm 151 GPIO_ACTIVE_LOW>; > + > + port { > + pcie6_port0_ep: endpoint { > + remote-endpoint = <&wwan_m2_pcie_ep>; > + }; > + }; This is already defined in glymur.dtsi, just reference it directly as &pcie6_port0_ep {} Konrad