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[108.51.35.162]) by smtp.googlemail.com with ESMTPSA id q25sm404003qkq.32.2021.02.02.15.54.07 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Tue, 02 Feb 2021 15:54:08 -0800 (PST) Subject: Re: [PATCH v14 07/16] dt-bindings: fix sifive gpio properties To: Atish Patra , Damien Le Moal Cc: Palmer Dabbelt , linux-riscv , devicetree , Rob Herring , Anup Patel , Atish Patra , Paul Walmsley References: <20210202103623.200809-1-damien.lemoal@wdc.com> <20210202103623.200809-8-damien.lemoal@wdc.com> From: Sean Anderson Message-ID: <5d565fe4-f624-ea28-177b-2fe01a678260@gmail.com> Date: Tue, 2 Feb 2021 18:54:07 -0500 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:68.0) Gecko/20100101 Thunderbird/68.12.0 MIME-Version: 1.0 In-Reply-To: Content-Type: text/plain; charset=utf-8; format=flowed Content-Language: en-US Content-Transfer-Encoding: 7bit Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org On 2/2/21 1:45 PM, Atish Patra wrote: > On Tue, Feb 2, 2021 at 2:37 AM Damien Le Moal wrote: >> >> The sifive gpio IP block supports up to 32 GPIOs. Reflect that in the > > The spec here says 16 GPIOs > https://static.dev.sifive.com/FU540-C000-v1.0.pdf > > Is there a updated spec available ? This GPIO device is (AFAICT) from [1]. While the version instantiated on SiFive's cores has 16 GPIOs, the actual number of GPIOs is configurable. In Canaan's version, there are 32 GPIOs. Unfortunately, I am not aware of any non-implementation-specific documentation for this device. --Sean [1] https://github.com/sifive/sifive-blocks/tree/master/src/main/scala/devices/gpio > >> interrupts property description and maxItems. Also add the standard >> ngpios property to describe the number of GPIOs available on the >> implementation. >> >> Also add the "canaan,k210-gpiohs" compatible string to indicate the use >> of this gpio controller in the Canaan Kendryte K210 SoC. If this >> compatible string is used, do not define the clocks property as >> required as the K210 SoC does not have a software controllable clock >> for the Sifive gpio IP block. >> >> Cc: Paul Walmsley >> Cc: Rob Herring >> Cc: devicetree@vger.kernel.org >> Signed-off-by: Damien Le Moal >> --- >> .../devicetree/bindings/gpio/sifive,gpio.yaml | 21 ++++++++++++++++--- >> 1 file changed, 18 insertions(+), 3 deletions(-) >> >> diff --git a/Documentation/devicetree/bindings/gpio/sifive,gpio.yaml b/Documentation/devicetree/bindings/gpio/sifive,gpio.yaml >> index ab22056f8b44..2cef18ca737c 100644 >> --- a/Documentation/devicetree/bindings/gpio/sifive,gpio.yaml >> +++ b/Documentation/devicetree/bindings/gpio/sifive,gpio.yaml >> @@ -16,6 +16,7 @@ properties: >> - enum: >> - sifive,fu540-c000-gpio >> - sifive,fu740-c000-gpio >> + - canaan,k210-gpiohs >> - const: sifive,gpio0 >> >> reg: >> @@ -23,9 +24,9 @@ properties: >> >> interrupts: >> description: >> - interrupt mapping one per GPIO. Maximum 16 GPIOs. >> + interrupt mapping one per GPIO. Maximum 32 GPIOs. >> minItems: 1 >> - maxItems: 16 >> + maxItems: 32 >> >> interrupt-controller: true >> >> @@ -38,6 +39,10 @@ properties: >> "#gpio-cells": >> const: 2 >> >> + ngpios: >> + minimum: 1 >> + maximum: 32 >> + >> gpio-controller: true >> >> required: >> @@ -46,10 +51,20 @@ required: >> - interrupts >> - interrupt-controller >> - "#interrupt-cells" >> - - clocks >> - "#gpio-cells" >> - gpio-controller >> >> +if: >> + properties: >> + compatible: >> + contains: >> + enum: >> + - sifive,fu540-c000-gpio >> + - sifive,fu740-c000-gpio >> +then: >> + required: >> + - clocks >> + >> additionalProperties: false >> >> examples: >> -- >> 2.29.2 >> >> >> _______________________________________________ >> linux-riscv mailing list >> linux-riscv@lists.infradead.org >> http://lists.infradead.org/mailman/listinfo/linux-riscv > > >