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From: Tomi Valkeinen <tomi.valkeinen+renesas@ideasonboard.com>
To: Prabhakar <prabhakar.csengg@gmail.com>
Cc: dri-devel@lists.freedesktop.org, devicetree@vger.kernel.org,
	linux-kernel@vger.kernel.org, linux-renesas-soc@vger.kernel.org,
	linux-clk@vger.kernel.org,
	Fabrizio Castro <fabrizio.castro.jz@renesas.com>,
	Tommaso Merciai <tommaso.merciai.xr@bp.renesas.com>,
	Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>,
	Andrzej Hajda <andrzej.hajda@intel.com>,
	Neil Armstrong <neil.armstrong@linaro.org>,
	Robert Foss <rfoss@kernel.org>,
	Laurent Pinchart <Laurent.pinchart@ideasonboard.com>,
	Jonas Karlman <jonas@kwiboo.se>,
	Jernej Skrabec <jernej.skrabec@gmail.com>,
	Maarten Lankhorst <maarten.lankhorst@linux.intel.com>,
	Maxime Ripard <mripard@kernel.org>,
	Thomas Zimmermann <tzimmermann@suse.de>,
	David Airlie <airlied@gmail.com>, Simona Vetter <simona@ffwll.ch>,
	Rob Herring <robh@kernel.org>,
	Krzysztof Kozlowski <krzk+dt@kernel.org>,
	Conor Dooley <conor+dt@kernel.org>,
	Geert Uytterhoeven <geert+renesas@glider.be>,
	Michael Turquette <mturquette@baylibre.com>,
	Stephen Boyd <sboyd@kernel.org>,
	Biju Das <biju.das.jz@bp.renesas.com>,
	Magnus Damm <magnus.damm@gmail.com>
Subject: Re: [PATCH v8 5/6] drm: renesas: rz-du: mipi_dsi: Add LPCLK clock support
Date: Wed, 10 Sep 2025 10:32:49 +0300	[thread overview]
Message-ID: <5ddabd43-35a0-406e-bc4d-3878febd3341@ideasonboard.com> (raw)
In-Reply-To: <20250903161718.180488-6-prabhakar.mahadev-lad.rj@bp.renesas.com>

On 03/09/2025 19:17, Prabhakar wrote:
> From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> 
> Add LPCLK clock handling to the RZ/G2L MIPI DSI driver to support proper
> DSI timing parameter configuration on RZ/V2H SoCs. While lpclk is present
> on both RZ/G2L and RZ/V2H SoCs, the RZ/V2H SoC specifically uses the lpclk
> rate to configure the DSI timing parameter ULPSEXIT.
> 
> Introduce a new lpclk field in the rzg2l_mipi_dsi structure and acquire
> the "lpclk" clock during probe to enable lpclk rate-based timing
> calculations on RZ/V2H while maintaining compatibility with RZ/G2L.
> 
> Co-developed-by: Fabrizio Castro <fabrizio.castro.jz@renesas.com>
> Signed-off-by: Fabrizio Castro <fabrizio.castro.jz@renesas.com>
> Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com>
> ---
> v7->v8:
> - Updated commit message
> - Switched to use devm_clk_get() instead of devm_clk_get_optional()
>   as lpclk clock is available on all SoCs.
> 
> v6->v7:
> - New patch
> Note, this patch was previously part of series [0].
> [0] https://lore.kernel.org/all/20250609225630.502888-1-prabhakar.mahadev-lad.rj@bp.renesas.com/
> ---
>  drivers/gpu/drm/renesas/rz-du/rzg2l_mipi_dsi.c | 5 +++++
>  1 file changed, 5 insertions(+)
> 
> diff --git a/drivers/gpu/drm/renesas/rz-du/rzg2l_mipi_dsi.c b/drivers/gpu/drm/renesas/rz-du/rzg2l_mipi_dsi.c
> index 3b52dfc0ea1e..bb03b49b1e85 100644
> --- a/drivers/gpu/drm/renesas/rz-du/rzg2l_mipi_dsi.c
> +++ b/drivers/gpu/drm/renesas/rz-du/rzg2l_mipi_dsi.c
> @@ -68,6 +68,7 @@ struct rzg2l_mipi_dsi {
>  	struct drm_bridge *next_bridge;
>  
>  	struct clk *vclk;
> +	struct clk *lpclk;
>  
>  	enum mipi_dsi_pixel_format format;
>  	unsigned int num_data_lanes;
> @@ -979,6 +980,10 @@ static int rzg2l_mipi_dsi_probe(struct platform_device *pdev)
>  	if (IS_ERR(dsi->vclk))
>  		return PTR_ERR(dsi->vclk);
>  
> +	dsi->lpclk = devm_clk_get(dsi->dev, "lpclk");
> +	if (IS_ERR(dsi->lpclk))
> +		return PTR_ERR(dsi->lpclk);
> +
>  	dsi->rstc = devm_reset_control_get_optional_exclusive(dsi->dev, "rst");
>  	if (IS_ERR(dsi->rstc))
>  		return dev_err_probe(dsi->dev, PTR_ERR(dsi->rstc),

Reviewed-by: Tomi Valkeinen <tomi.valkeinen+renesas@ideasonboard.com>

 Tomi


  reply	other threads:[~2025-09-10  7:32 UTC|newest]

Thread overview: 19+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2025-09-03 16:17 [PATCH v8 0/6] Add support for DU/DSI clocks and DSI driver support for the Renesas RZ/V2H(P) SoC Prabhakar
2025-09-03 16:17 ` [PATCH v8 1/6] clk: renesas: rzv2h-cpg: Add instance field to struct pll Prabhakar
2025-09-03 16:17 ` [PATCH v8 2/6] clk: renesas: rzv2h-cpg: Add support for DSI clocks Prabhakar
2025-09-10 12:30   ` Tomi Valkeinen
2025-09-11  8:14     ` Lad, Prabhakar
2025-09-11 14:26       ` Tomi Valkeinen
2025-09-11 14:30         ` Biju Das
2025-09-17 16:28         ` Biju Das
2025-10-01 12:23         ` Lad, Prabhakar
2025-10-01 13:17           ` Geert Uytterhoeven
2025-09-24 13:05   ` Geert Uytterhoeven
2025-10-01  9:29     ` Lad, Prabhakar
2025-09-03 16:17 ` [PATCH v8 3/6] clk: renesas: r9a09g057: Add clock and reset entries for DSI and LCDC Prabhakar
2025-09-03 16:17 ` [PATCH v8 4/6] dt-bindings: display: bridge: renesas,dsi: Document RZ/V2H(P) and RZ/V2N Prabhakar
2025-09-03 16:17 ` [PATCH v8 5/6] drm: renesas: rz-du: mipi_dsi: Add LPCLK clock support Prabhakar
2025-09-10  7:32   ` Tomi Valkeinen [this message]
2025-09-03 16:17 ` [PATCH v8 6/6] drm: renesas: rz-du: mipi_dsi: Add support for RZ/V2H(P) SoC Prabhakar
2025-09-10  7:36   ` Tomi Valkeinen
2025-09-24 13:11   ` Geert Uytterhoeven

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