Re: [PATCH 2/2] drivers/tidss: Add support for AM62A7 DSS

[Aradhya Bhatia <a-bhatia1@ti.com>]

On 18-Aug-23 18:47, Aradhya Bhatia wrote:
> Add support for the DSS controller on TI's AM62A7 SoC in the tidss
> driver.
> 
> This contrller has 2 video pipelines that can render 2 video planes on
> over a screen, using the overlay managers. The output of the DSS comes
> from video port 2 (VP2) in the form of RGB88 DPI signals, while the VP1
> is tied off inside the SoC.
> 
> Signed-off-by: Aradhya Bhatia <a-bhatia1@ti.com>
> ---
>  drivers/gpu/drm/tidss/tidss_dispc.c | 53 +++++++++++++++++++++++++++++
>  drivers/gpu/drm/tidss/tidss_dispc.h |  2 ++
>  drivers/gpu/drm/tidss/tidss_drv.c   |  1 +
>  3 files changed, 56 insertions(+)
> 
> diff --git a/drivers/gpu/drm/tidss/tidss_dispc.c b/drivers/gpu/drm/tidss/tidss_dispc.c
> index 9d9dee7abaef..0e2d55d9a0d7 100644
> --- a/drivers/gpu/drm/tidss/tidss_dispc.c
> +++ b/drivers/gpu/drm/tidss/tidss_dispc.c
> @@ -322,6 +322,54 @@ const struct dispc_features dispc_am625_feats = {
>  	.vid_order = { 1, 0 },
>  };
>  
> +const struct dispc_features dispc_am62a7_feats = {
> +	.max_pclk_khz = {
> +		[DISPC_VP_DPI] = 165000,
> +	},
> +
> +	.scaling = {
> +		.in_width_max_5tap_rgb = 1280,
> +		.in_width_max_3tap_rgb = 2560,
> +		.in_width_max_5tap_yuv = 2560,
> +		.in_width_max_3tap_yuv = 4096,
> +		.upscale_limit = 16,
> +		.downscale_limit_5tap = 4,
> +		.downscale_limit_3tap = 2,
> +		/*
> +		 * The max supported pixel inc value is 255. The value
> +		 * of pixel inc is calculated like this: 1+(xinc-1)*bpp.
> +		 * The maximum bpp of all formats supported by the HW
> +		 * is 8. So the maximum supported xinc value is 32,
> +		 * because 1+(32-1)*8 < 255 < 1+(33-1)*4.
> +		 */
> +		.xinc_max = 32,
> +	},
> +
> +	.subrev = DISPC_AM62A7,
> +
> +	.common = "common",
> +	.common_regs = tidss_am65x_common_regs,
> +
> +	.num_vps = 2,
> +	.vp_name = { "vp1", "vp2" },
> +	.ovr_name = { "ovr1", "ovr2" },
> +	.vpclk_name =  { "vp1", "vp2" },
> +	.vp_bus_type = { DISPC_VP_INTERNAL, DISPC_VP_DPI },
> +
> +	.vp_feat = { .color = {
> +			.has_ctm = true,
> +			.gamma_size = 256,
> +			.gamma_type = TIDSS_GAMMA_8BIT,
> +		},
> +	},
> +
> +	.num_planes = 2,
> +	/* note: vid is plane_id 0 and vidl1 is plane_id 1 */
> +	.vid_name = { "vid", "vidl1" },
> +	.vid_lite = { false, true, },
> +	.vid_order = { 1, 0 },
> +};
> +
>  static const u16 *dispc_common_regmap;
>  
>  struct dss_vp_data {
> @@ -823,6 +871,7 @@ dispc_irq_t dispc_read_and_clear_irqstatus(struct dispc_device *dispc)
>  	switch (dispc->feat->subrev) {
>  	case DISPC_K2G:
>  		return dispc_k2g_read_and_clear_irqstatus(dispc);
> +	case DISPC_AM62A7:
>  	case DISPC_AM625:
>  	case DISPC_AM65X:
>  	case DISPC_J721E:
> @@ -839,6 +888,7 @@ void dispc_set_irqenable(struct dispc_device *dispc, dispc_irq_t mask)
>  	case DISPC_K2G:
>  		dispc_k2g_set_irqenable(dispc, mask);
>  		break;
> +	case DISPC_AM62A7:
>  	case DISPC_AM625:
>  	case DISPC_AM65X:
>  	case DISPC_J721E:
> @@ -1330,6 +1380,7 @@ void dispc_ovr_set_plane(struct dispc_device *dispc, u32 hw_plane,
>  		dispc_k2g_ovr_set_plane(dispc, hw_plane, hw_videoport,
>  					x, y, layer);
>  		break;
> +	case DISPC_AM62A7:
>  	case DISPC_AM625:
>  	case DISPC_AM65X:
>  		dispc_am65x_ovr_set_plane(dispc, hw_plane, hw_videoport,
> @@ -2249,6 +2300,7 @@ static void dispc_plane_init(struct dispc_device *dispc)
>  	case DISPC_K2G:
>  		dispc_k2g_plane_init(dispc);
>  		break;
> +	case DISPC_AM62A7:
>  	case DISPC_AM625:
>  	case DISPC_AM65X:
>  	case DISPC_J721E:
> @@ -2356,6 +2408,7 @@ static void dispc_vp_write_gamma_table(struct dispc_device *dispc,
>  	case DISPC_K2G:
>  		dispc_k2g_vp_write_gamma_table(dispc, hw_videoport);
>  		break;
> +	case DISPC_AM62A7:
>  	case DISPC_AM625:
>  	case DISPC_AM65X:
>  		dispc_am65x_vp_write_gamma_table(dispc, hw_videoport);
> diff --git a/drivers/gpu/drm/tidss/tidss_dispc.h b/drivers/gpu/drm/tidss/tidss_dispc.h
> index 33ac5ad7a423..2aa1c814ea2a 100644
> --- a/drivers/gpu/drm/tidss/tidss_dispc.h
> +++ b/drivers/gpu/drm/tidss/tidss_dispc.h
> @@ -59,6 +59,7 @@ enum dispc_vp_bus_type {
>  
>  enum dispc_dss_subrevision {
>  	DISPC_K2G,
> +	DISPC_AM62A7,
>  	DISPC_AM625,
>  	DISPC_AM65X,
>  	DISPC_J721E,
> @@ -88,6 +89,7 @@ struct dispc_features {

Made an oopsie and missed sorting 'DISPC_AM62A7' in above instances. It
should be under DISPC_AM625. Please ignore this patch / series. Will
send a v2. Apologies for the noise.

Regards
Aradhya

>  
>  extern const struct dispc_features dispc_k2g_feats;
>  extern const struct dispc_features dispc_am625_feats;
> +extern const struct dispc_features dispc_am62a7_feats;
>  extern const struct dispc_features dispc_am65x_feats;
>  extern const struct dispc_features dispc_j721e_feats;
>  
> diff --git a/drivers/gpu/drm/tidss/tidss_drv.c b/drivers/gpu/drm/tidss/tidss_drv.c
> index 4d063eb9cd0b..edf69d020544 100644
> --- a/drivers/gpu/drm/tidss/tidss_drv.c
> +++ b/drivers/gpu/drm/tidss/tidss_drv.c
> @@ -231,6 +231,7 @@ static void tidss_shutdown(struct platform_device *pdev)
>  static const struct of_device_id tidss_of_table[] = {
>  	{ .compatible = "ti,k2g-dss", .data = &dispc_k2g_feats, },
>  	{ .compatible = "ti,am625-dss", .data = &dispc_am625_feats, },
> +	{ .compatible = "ti,am62a7-dss", .data = &dispc_am62a7_feats, },
>  	{ .compatible = "ti,am65x-dss", .data = &dispc_am65x_feats, },
>  	{ .compatible = "ti,j721e-dss", .data = &dispc_j721e_feats, },
>  	{ }