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[78.88.45.245]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-ab6e47f18f3sm452633266b.80.2025.02.01.07.51.06 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Sat, 01 Feb 2025 07:51:07 -0800 (PST) Message-ID: <5defdbcb-f134-4332-8b63-50794da6e2cd@oss.qualcomm.com> Date: Sat, 1 Feb 2025 16:51:05 +0100 Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v3 2/2] arm64: dts: qcom: qcs8300: Add device node for gfx_smmu To: Pratyush Brahma , Konrad Dybcio , andersson@kernel.org Cc: konradybcio@kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Prakash Gupta References: <20241227110024.30203-1-quic_pbrahma@quicinc.com> <1c8af731-c551-4d72-84a0-f14d57bec4ec@oss.qualcomm.com> <41fd6b59-249d-4f19-9ff8-4ae169a6db05@oss.qualcomm.com> <27aa8dc3-34b9-40e7-93bc-e52118b46138@quicinc.com> Content-Language: en-US From: Konrad Dybcio In-Reply-To: Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-Proofpoint-ORIG-GUID: eNcKYwA_Q3JKT1ISsPoLVtLgAGWuxZks X-Proofpoint-GUID: eNcKYwA_Q3JKT1ISsPoLVtLgAGWuxZks X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1057,Hydra:6.0.680,FMLib:17.12.68.34 definitions=2025-02-01_07,2025-01-31_02,2024-11-22_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 mlxscore=0 suspectscore=0 spamscore=0 impostorscore=0 clxscore=1015 adultscore=0 bulkscore=0 phishscore=0 mlxlogscore=999 lowpriorityscore=0 malwarescore=0 priorityscore=1501 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2501170000 definitions=main-2502010138 On 30.01.2025 6:40 AM, Pratyush Brahma wrote: > > On 1/29/2025 7:56 PM, Konrad Dybcio wrote: >> On 28.01.2025 11:02 AM, Pratyush Brahma wrote: >>> On 1/9/2025 8:56 PM, Konrad Dybcio wrote: >>>> On 8.01.2025 1:10 PM, Pratyush Brahma wrote: >>>>> On 12/30/2024 6:49 PM, Konrad Dybcio wrote: >>>>>> On 27.12.2024 12:00 PM, Pratyush Brahma wrote: >>>>>>> Add the device node for gfx smmu that is required for gpu >>>>>>> specific address translations. >>>>>>> >>>>>>> This patch depends on the patch series [1] posted by Imran Shaik >>>>>>> adding the clock support for gpu. >>>>>>> >>>>>>> [1] https://lore.kernel.org/all/802d32f1-ff7e-4d61-83f1-f804ee1750ed@oss.qualcomm.com/ >>>>>>> >>>>>>> Signed-off-by: Pratyush Brahma >>>>>>> --- >>>>>>>     arch/arm64/boot/dts/qcom/qcs8300.dtsi | 37 +++++++++++++++++++++++++++ >>>>>>>     1 file changed, 37 insertions(+) >>>>>>> >>>>>>> diff --git a/arch/arm64/boot/dts/qcom/qcs8300.dtsi b/arch/arm64/boot/dts/qcom/qcs8300.dtsi >>>>>>> index 80226992a65d..8eb688e2df0a 100644 >>>>>>> --- a/arch/arm64/boot/dts/qcom/qcs8300.dtsi >>>>>>> +++ b/arch/arm64/boot/dts/qcom/qcs8300.dtsi >>>>>>> @@ -816,6 +816,43 @@ >>>>>>>                 #power-domain-cells = <1>; >>>>>>>             }; >>>>>>>     +        adreno_smmu: iommu@3da0000 { >>>>>>> +            compatible = "qcom,qcs8300-smmu-500", "qcom,adreno-smmu", >>>>>>> +                   "qcom,smmu-500", "arm,mmu-500"; >>>>>>> +            reg = <0x0 0x3da0000 0x0 0x20000>; >>>>>>> +            #iommu-cells = <2>; >>>>>>> +            #global-interrupts = <2>; >>>>>>> +            dma-coherent; >>>>>>> + >>>>>>> +            power-domains = <&gpucc GPU_CC_CX_GDSC>; >>>>>>> +            clocks = <&gcc GCC_GPU_MEMNOC_GFX_CLK>, >>>>>>> +                 <&gcc GCC_GPU_SNOC_DVM_GFX_CLK>, >>>>>>> +                 <&gpucc GPU_CC_AHB_CLK>, >>>>>>> +                 <&gpucc GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK>, >>>>>>> +                 <&gpucc GPU_CC_CX_GMU_CLK>, >>>>>>> +                 <&gpucc GPU_CC_HUB_CX_INT_CLK>, >>>>>>> +                 <&gpucc GPU_CC_HUB_AON_CLK>; >>>>>>> +            clock-names = "gcc_gpu_memnoc_gfx_clk", >>>>>>> +                      "gcc_gpu_snoc_dvm_gfx_clk", >>>>>>> +                      "gpu_cc_ahb_clk", >>>>>>> +                      "gpu_cc_hlos1_vote_gpu_smmu_clk", >>>>>>> +                      "gpu_cc_cx_gmu_clk", >>>>>>> +                      "gpu_cc_hub_cx_int_clk", >>>>>>> +                      "gpu_cc_hub_aon_clk"; >>>>>> Most of these entries look totally bogus, please make sure you only >>>>>> reference the ones actually required >>>>> These entries are exactly similar to the ones we use in sa8775p as well [1] and the usecases >>>>> haven't changed between qcs8300 and sa8775p. >>>>> >>>>> Can you please let me know which entries you find irrelevant here? >>>> Well, I'm particularly unsure about CX_GMU and the HUB clocks. >>>> I >>don't think<< they don't have much to do with the SMMU, but please >>>> check internally with someone who knows for sure >>> I checked internally and found that these clocks are required for gpu smmu operations >>> as we don't use interconnect voting mechanism here as we do downstream. Hence the >>> list of clocks is same across all targets using gpu smmu as described in [1] previously. >> I managed to dig up some documents too.. It seems you're right, however the order >> is supposed to be slightly different: >> >> GPU_CC_CX_GMU_CLK >> GPU_CC_HUB_CX_INT_CLK >> GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK >> GCC_GPU_MEMNOC_GFX_CLK >> >> Unsure if it *actually* matters given we've added them in a random order on a >> multitude of platforms and there haven't been any visible adverse effects. > Thanks for checking this. We haven't really adhered to this order in > most of our platforms and things have been running fine. So I guess it doesn't matter. > However, I'll still send out the next patchset in the order you've mentioned. Just so that we > are in consonance, the final order would look like the following. Please correct me if you'd > prefer otherwise. > >                 clocks = <&gpucc GPU_CC_CX_GMU_CLK>, >                                <&gpucc GPU_CC_HUB_CX_INT_CLK>, >                                <&gpucc GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK>, >                                <&gcc GCC_GPU_MEMNOC_GFX_CLK>, >                                <&gcc GCC_GPU_SNOC_DVM_GFX_CLK>, >                                <&gpucc GPU_CC_AHB_CLK>, >                                <&gpucc GPU_CC_HUB_AON_CLK>; Looks good, please double-check if it works without clk_ignore_unused Konrad