[PATCH v5 0/7] Add the iMX8MP PCIe support

[PATCH v5 0/7] Add the iMX8MP PCIe support

[Richard Zhu]

Based on the 6.0-rc1 of the pci/next branch. 
This series adds the i.MX8MP PCIe support and tested on i.MX8MP
EVK board when one PCIe NVME device is used.

- i.MX8MP PCIe has reversed initial PERST bit value refer to i.MX8MQ/i.MX8MM.
  Add the PHY PERST explicitly for i.MX8MP PCIe PHY.
- Add the i.MX8MP PCIe PHY support in the i.MX8M PCIe PHY driver.
  And share as much as possible codes with i.MX8MM PCIe PHY.
- Add the i.MX8MP PCIe support in binding document, DTS files, and PCIe
  driver.

Main changes v4-->v5:
- Use Lucas' approach, let blk-ctrl driver do the hsio-mix resets.
- Fetch the iomuxc-gpr regmap by the different phandles.
- Reorder the patches, place the DT changes at the begin of this series.

Main changes v3-->v4:
- Regarding Phillipp's suggestions, add fix tag into the first commit.
- Add Reviewed and Tested tags.

Main changes v2-->v3:
- Fix the schema checking error in the PHY dt-binding patch.
- Inspired by Lucas, the PLL configurations might not required when
  external OSC is used as PCIe referrence clock. It's true. Remove all
  the HSIO PLL bit manipulations, and PCIe works fine on i.MX8MP EVK board
  with one NVME device is used.
- Drop the #4 patch of v2, since it had been applied by Rob.

Main changes v1-->v2:
- It's my fault forget including Vinod, re-send v2 after include Vinod
  and linux-phy@lists.infradead.org.
- List the basements of this patch-set. The branch, codes changes and so on.
- Clean up some useless register and bit definitions in #3 patch.

Lucas(1):
soc: imx: imx8mp-blk-ctrl: handle PCIe PHY resets

Richard(6):
dt-binding: phy: Add iMX8MP PCIe PHY binding
arm64: dts: imx8mp: Add iMX8MP PCIe support
arm64: dts: imx8mp-evk: Add PCIe support
reset: imx7: Fix the iMX8MP PCIe PHY PERST support
phy: freescale: imx8m-pcie: Add iMX8MP PCIe PHY
PCI: imx6: Add iMX8MP PCIe support

Documentation/devicetree/bindings/phy/fsl,imx8-pcie-phy.yaml |  16 ++++++++--
arch/arm64/boot/dts/freescale/imx8mp-evk.dts                 |  53 ++++++++++++++++++++++++++++++++
arch/arm64/boot/dts/freescale/imx8mp.dtsi                    |  43 ++++++++++++++++++++++++++
drivers/pci/controller/dwc/pci-imx6.c                        |  29 ++++++++++++++++--
drivers/phy/freescale/phy-fsl-imx8m-pcie.c                   | 137 +++++++++++++++++++++++++++++++++++++++++++++++++++++-----------------------------
drivers/reset/reset-imx7.c                                   |   1 +
drivers/soc/imx/imx8mp-blk-ctrl.c                            |  10 ++++++
7 files changed, 235 insertions(+), 54 deletions(-)

[PATCH v5 1/7] dt-binding: phy: Add iMX8MP PCIe PHY binding

[Richard Zhu]

Add i.MX8MP PCIe PHY binding.
On iMX8MM, the initialized default value of PERST bit(BIT3) of
SRC_PCIEPHY_RCR is 1b'1.
But i.MX8MP has one inversed default value 1b'0 of PERST bit.

And the PERST bit should be kept 1b'1 after power and clocks are stable.
So add one more PERST explicitly for i.MX8MP PCIe PHY.

Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com>
Tested-by: Marek Vasut <marex@denx.de>
Tested-by: Richard Leitner <richard.leitner@skidata.com>
Tested-by: Alexander Stein <alexander.stein@ew.tq-group.com>
---
 .../bindings/phy/fsl,imx8-pcie-phy.yaml          | 16 +++++++++++++---
 1 file changed, 13 insertions(+), 3 deletions(-)

diff --git a/Documentation/devicetree/bindings/phy/fsl,imx8-pcie-phy.yaml b/Documentation/devicetree/bindings/phy/fsl,imx8-pcie-phy.yaml
index b6421eedece3..692783c7fd69 100644
--- a/Documentation/devicetree/bindings/phy/fsl,imx8-pcie-phy.yaml
+++ b/Documentation/devicetree/bindings/phy/fsl,imx8-pcie-phy.yaml
@@ -16,6 +16,7 @@ properties:
   compatible:
     enum:
       - fsl,imx8mm-pcie-phy
+      - fsl,imx8mp-pcie-phy
 
   reg:
     maxItems: 1
@@ -28,11 +29,16 @@ properties:
       - const: ref
 
   resets:
-    maxItems: 1
+    minItems: 1
+    maxItems: 2
 
   reset-names:
-    items:
-      - const: pciephy
+    oneOf:
+      - items:          # for iMX8MM
+          - const: pciephy
+      - items:          # for IMX8MP
+          - const: pciephy
+          - const: perst
 
   fsl,refclk-pad-mode:
     description: |
@@ -60,6 +66,10 @@ properties:
     description: A boolean property indicating the CLKREQ# signal is
       not supported in the board design (optional)
 
+  power-domains:
+    description: PCIe PHY  power domain (optional).
+    maxItems: 1
+
 required:
   - "#phy-cells"
   - compatible
-- 
2.25.1

[PATCH v5 2/7] arm64: dts: imx8mp: Add iMX8MP PCIe support

[Richard Zhu]

Add i.MX8MP PCIe support.

Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com>
Tested-by: Marek Vasut <marex@denx.de>
Tested-by: Richard Leitner <richard.leitner@skidata.com>
Tested-by: Alexander Stein <alexander.stein@ew.tq-group.com>
---
 arch/arm64/boot/dts/freescale/imx8mp.dtsi | 43 +++++++++++++++++++++++
 1 file changed, 43 insertions(+)

diff --git a/arch/arm64/boot/dts/freescale/imx8mp.dtsi b/arch/arm64/boot/dts/freescale/imx8mp.dtsi
index fe178b7d063c..21a4cc417c81 100644
--- a/arch/arm64/boot/dts/freescale/imx8mp.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8mp.dtsi
@@ -5,6 +5,7 @@
 
 #include <dt-bindings/clock/imx8mp-clock.h>
 #include <dt-bindings/power/imx8mp-power.h>
+#include <dt-bindings/reset/imx8mp-reset.h>
 #include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/input/input.h>
 #include <dt-bindings/interrupt-controller/arm-gic.h>
@@ -1084,6 +1085,17 @@ media_blk_ctrl: blk-ctrl@32ec0000 {
 				#power-domain-cells = <1>;
 			};
 
+			pcie_phy: pcie-phy@32f00000 {
+				compatible = "fsl,imx8mp-pcie-phy";
+				reg = <0x32f00000 0x10000>;
+				resets = <&src IMX8MP_RESET_PCIEPHY>,
+					 <&src IMX8MP_RESET_PCIEPHY_PERST>;
+				reset-names = "pciephy", "perst";
+				power-domains = <&hsio_blk_ctrl IMX8MP_HSIOBLK_PD_PCIE_PHY>;
+				#phy-cells = <0>;
+				status = "disabled";
+			};
+
 			hsio_blk_ctrl: blk-ctrl@32f10000 {
 				compatible = "fsl,imx8mp-hsio-blk-ctrl", "syscon";
 				reg = <0x32f10000 0x24>;
@@ -1099,6 +1111,37 @@ hsio_blk_ctrl: blk-ctrl@32f10000 {
 			};
 		};
 
+		pcie: pcie@33800000 {
+			compatible = "fsl,imx8mp-pcie";
+			reg = <0x33800000 0x400000>, <0x1ff00000 0x80000>;
+			reg-names = "dbi", "config";
+			#address-cells = <3>;
+			#size-cells = <2>;
+			device_type = "pci";
+			bus-range = <0x00 0xff>;
+			ranges =  <0x81000000 0 0x00000000 0x1ff80000 0 0x00010000>, /* downstream I/O 64KB */
+				  <0x82000000 0 0x18000000 0x18000000 0 0x07f00000>; /* non-prefetchable memory */
+			num-lanes = <1>;
+			num-viewport = <4>;
+			interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
+			interrupt-names = "msi";
+			#interrupt-cells = <1>;
+			interrupt-map-mask = <0 0 0 0x7>;
+			interrupt-map = <0 0 0 1 &gic GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>,
+					<0 0 0 2 &gic GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
+					<0 0 0 3 &gic GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>,
+					<0 0 0 4 &gic GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>;
+			fsl,max-link-speed = <3>;
+			linux,pci-domain = <0>;
+			power-domains = <&hsio_blk_ctrl IMX8MP_HSIOBLK_PD_PCIE>;
+			resets = <&src IMX8MP_RESET_PCIE_CTRL_APPS_EN>,
+				 <&src IMX8MP_RESET_PCIE_CTRL_APPS_TURNOFF>;
+			reset-names = "apps", "turnoff";
+			phys = <&pcie_phy>;
+			phy-names = "pcie-phy";
+			status = "disabled";
+		};
+
 		gpu3d: gpu@38000000 {
 			compatible = "vivante,gc";
 			reg = <0x38000000 0x8000>;
-- 
2.25.1

[PATCH v5 3/7] arm64: dts: imx8mp-evk: Add PCIe support

[Richard Zhu]

Add PCIe support on i.MX8MP EVK board.

Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com>
Tested-by: Marek Vasut <marex@denx.de>
Tested-by: Richard Leitner <richard.leitner@skidata.com>
Tested-by: Alexander Stein <alexander.stein@ew.tq-group.com>
---
 arch/arm64/boot/dts/freescale/imx8mp-evk.dts | 53 ++++++++++++++++++++
 1 file changed, 53 insertions(+)

diff --git a/arch/arm64/boot/dts/freescale/imx8mp-evk.dts b/arch/arm64/boot/dts/freescale/imx8mp-evk.dts
index f6b017ab5f53..defc92a8bb60 100644
--- a/arch/arm64/boot/dts/freescale/imx8mp-evk.dts
+++ b/arch/arm64/boot/dts/freescale/imx8mp-evk.dts
@@ -5,6 +5,7 @@
 
 /dts-v1/;
 
+#include <dt-bindings/phy/phy-imx8-pcie.h>
 #include "imx8mp.dtsi"
 
 / {
@@ -33,6 +34,12 @@ memory@40000000 {
 		      <0x1 0x00000000 0 0xc0000000>;
 	};
 
+	pcie0_refclk: pcie0-refclk {
+		compatible = "fixed-clock";
+			#clock-cells = <0>;
+			clock-frequency = <100000000>;
+	};
+
 	reg_can1_stby: regulator-can1-stby {
 		compatible = "regulator-fixed";
 		regulator-name = "can1-stby";
@@ -55,6 +62,17 @@ reg_can2_stby: regulator-can2-stby {
 		enable-active-high;
 	};
 
+	reg_pcie0: regulator-pcie {
+		compatible = "regulator-fixed";
+		pinctrl-names = "default";
+		pinctrl-0 = <&pinctrl_pcie0_reg>;
+		regulator-name = "MPCIE_3V3";
+		regulator-min-microvolt = <3300000>;
+		regulator-max-microvolt = <3300000>;
+		gpio = <&gpio2 6 GPIO_ACTIVE_HIGH>;
+		enable-active-high;
+	};
+
 	reg_usdhc2_vmmc: regulator-usdhc2 {
 		compatible = "regulator-fixed";
 		pinctrl-names = "default";
@@ -350,6 +368,28 @@ &i2c5 {
 	 */
 };
 
+&pcie_phy {
+	fsl,refclk-pad-mode = <IMX8_PCIE_REFCLK_PAD_INPUT>;
+	clocks = <&pcie0_refclk>;
+	clock-names = "ref";
+	status = "okay";
+};
+
+&pcie{
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_pcie0>;
+	reset-gpio = <&gpio2 7 GPIO_ACTIVE_LOW>;
+	clocks = <&clk IMX8MP_CLK_HSIO_ROOT>,
+		 <&clk IMX8MP_CLK_PCIE_ROOT>,
+		 <&clk IMX8MP_CLK_HSIO_AXI>;
+	clock-names = "pcie", "pcie_aux", "pcie_bus";
+	assigned-clocks = <&clk IMX8MP_CLK_PCIE_AUX>;
+	assigned-clock-rates = <10000000>;
+	assigned-clock-parents = <&clk IMX8MP_SYS_PLL2_50M>;
+	vpcie-supply = <&reg_pcie0>;
+	status = "okay";
+};
+
 &snvs_pwrkey {
 	status = "okay";
 };
@@ -502,6 +542,19 @@ MX8MP_IOMUXC_SPDIF_TX__I2C5_SCL         0x400001c2
 		>;
 	};
 
+	pinctrl_pcie0: pcie0grp {
+		fsl,pins = <
+			MX8MP_IOMUXC_I2C4_SCL__PCIE_CLKREQ_B	0x61 /* open drain, pull up */
+			MX8MP_IOMUXC_SD1_DATA5__GPIO2_IO07	0x41
+		>;
+	};
+
+	pinctrl_pcie0_reg: pcie0reggrp {
+		fsl,pins = <
+			MX8MP_IOMUXC_SD1_DATA4__GPIO2_IO06	0x41
+		>;
+	};
+
 	pinctrl_pmic: pmicgrp {
 		fsl,pins = <
 			MX8MP_IOMUXC_GPIO1_IO03__GPIO1_IO03	0x000001c0
-- 
2.25.1

Re: [PATCH v5 3/7] arm64: dts: imx8mp-evk: Add PCIe support

[Marcel Ziswiler]

On Tue, 2022-08-30 at 15:46 +0800, Richard Zhu wrote:
> Add PCIe support on i.MX8MP EVK board.
> 
> Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com>
> Tested-by: Marek Vasut <marex@denx.de>
> Tested-by: Richard Leitner <richard.leitner@skidata.com>
> Tested-by: Alexander Stein <alexander.stein@ew.tq-group.com>
> ---
>  arch/arm64/boot/dts/freescale/imx8mp-evk.dts | 53 ++++++++++++++++++++
>  1 file changed, 53 insertions(+)
> 
> diff --git a/arch/arm64/boot/dts/freescale/imx8mp-evk.dts b/arch/arm64/boot/dts/freescale/imx8mp-evk.dts
> index f6b017ab5f53..defc92a8bb60 100644
> --- a/arch/arm64/boot/dts/freescale/imx8mp-evk.dts
> +++ b/arch/arm64/boot/dts/freescale/imx8mp-evk.dts
> @@ -5,6 +5,7 @@
>  
>  /dts-v1/;
>  
> +#include <dt-bindings/phy/phy-imx8-pcie.h>
>  #include "imx8mp.dtsi"
>  
>  / {
> @@ -33,6 +34,12 @@ memory@40000000 {
>                       <0x1 0x00000000 0 0xc0000000>;
>         };
>  
> +       pcie0_refclk: pcie0-refclk {
> +               compatible = "fixed-clock";
> +                       #clock-cells = <0>;
> +                       clock-frequency = <100000000>;
> +       };
> +
>         reg_can1_stby: regulator-can1-stby {
>                 compatible = "regulator-fixed";
>                 regulator-name = "can1-stby";
> @@ -55,6 +62,17 @@ reg_can2_stby: regulator-can2-stby {
>                 enable-active-high;
>         };
>  
> +       reg_pcie0: regulator-pcie {
> +               compatible = "regulator-fixed";
> +               pinctrl-names = "default";
> +               pinctrl-0 = <&pinctrl_pcie0_reg>;
> +               regulator-name = "MPCIE_3V3";
> +               regulator-min-microvolt = <3300000>;
> +               regulator-max-microvolt = <3300000>;
> +               gpio = <&gpio2 6 GPIO_ACTIVE_HIGH>;
> +               enable-active-high;
> +       };
> +
>         reg_usdhc2_vmmc: regulator-usdhc2 {
>                 compatible = "regulator-fixed";
>                 pinctrl-names = "default";
> @@ -350,6 +368,28 @@ &i2c5 {
>          */
>  };
>  
> +&pcie_phy {
> +       fsl,refclk-pad-mode = <IMX8_PCIE_REFCLK_PAD_INPUT>;
> +       clocks = <&pcie0_refclk>;
> +       clock-names = "ref";
> +       status = "okay";
> +};
> +
> +&pcie{

Missing space before that curly brace.

> +       pinctrl-names = "default";
> +       pinctrl-0 = <&pinctrl_pcie0>;
> +       reset-gpio = <&gpio2 7 GPIO_ACTIVE_LOW>;
> +       clocks = <&clk IMX8MP_CLK_HSIO_ROOT>,
> +                <&clk IMX8MP_CLK_PCIE_ROOT>,
> +                <&clk IMX8MP_CLK_HSIO_AXI>;
> +       clock-names = "pcie", "pcie_aux", "pcie_bus";
> +       assigned-clocks = <&clk IMX8MP_CLK_PCIE_AUX>;
> +       assigned-clock-rates = <10000000>;
> +       assigned-clock-parents = <&clk IMX8MP_SYS_PLL2_50M>;
> +       vpcie-supply = <&reg_pcie0>;
> +       status = "okay";
> +};
> +
>  &snvs_pwrkey {
>         status = "okay";
>  };
> @@ -502,6 +542,19 @@ MX8MP_IOMUXC_SPDIF_TX__I2C5_SCL         0x400001c2
>                 >;
>         };
>  
> +       pinctrl_pcie0: pcie0grp {
> +               fsl,pins = <
> +                       MX8MP_IOMUXC_I2C4_SCL__PCIE_CLKREQ_B    0x61 /* open drain, pull up */
> +                       MX8MP_IOMUXC_SD1_DATA5__GPIO2_IO07      0x41
> +               >;
> +       };
> +
> +       pinctrl_pcie0_reg: pcie0reggrp {
> +               fsl,pins = <
> +                       MX8MP_IOMUXC_SD1_DATA4__GPIO2_IO06      0x41
> +               >;
> +       };
> +
>         pinctrl_pmic: pmicgrp {
>                 fsl,pins = <
>                         MX8MP_IOMUXC_GPIO1_IO03__GPIO1_IO03     0x000001c0

RE: [PATCH v5 3/7] arm64: dts: imx8mp-evk: Add PCIe support

[Hongxing Zhu]

> -----Original Message-----
> From: Marcel Ziswiler <marcel.ziswiler@toradex.com>
> Sent: 2022年8月31日 18:18
> To: vkoul@kernel.org; richard.leitner@linux.dev;
> alexander.stein@ew.tq-group.com; robh@kernel.org; l.stach@pengutronix.de;
> shawnguo@kernel.org; lorenzo.pieralisi@arm.com; p.zabel@pengutronix.de;
> Hongxing Zhu <hongxing.zhu@nxp.com>; bhelgaas@google.com;
> marex@denx.de
> Cc: linux-phy@lists.infradead.org; linux-pci@vger.kernel.org;
> kernel@pengutronix.de; devicetree@vger.kernel.org;
> linux-kernel@vger.kernel.org; dl-linux-imx <linux-imx@nxp.com>;
> linux-arm-kernel@lists.infradead.org
> Subject: Re: [PATCH v5 3/7] arm64: dts: imx8mp-evk: Add PCIe support
> 
> On Tue, 2022-08-30 at 15:46 +0800, Richard Zhu wrote:
> > Add PCIe support on i.MX8MP EVK board.
> >
> > Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com>
> > Tested-by: Marek Vasut <marex@denx.de>
> > Tested-by: Richard Leitner <richard.leitner@skidata.com>
> > Tested-by: Alexander Stein <alexander.stein@ew.tq-group.com>
> > ---
> >  arch/arm64/boot/dts/freescale/imx8mp-evk.dts | 53
> > ++++++++++++++++++++
> >  1 file changed, 53 insertions(+)
> >
> > diff --git a/arch/arm64/boot/dts/freescale/imx8mp-evk.dts
> > b/arch/arm64/boot/dts/freescale/imx8mp-evk.dts
> > index f6b017ab5f53..defc92a8bb60 100644
> > --- a/arch/arm64/boot/dts/freescale/imx8mp-evk.dts
> > +++ b/arch/arm64/boot/dts/freescale/imx8mp-evk.dts
> > @@ -5,6 +5,7 @@
> >
> >  /dts-v1/;
> >
> > +#include <dt-bindings/phy/phy-imx8-pcie.h>
> >  #include "imx8mp.dtsi"
> >
> >  / {
> > @@ -33,6 +34,12 @@ memory@40000000 {
> >                       <0x1 0x00000000 0 0xc0000000>;
> >         };
> >
> > +       pcie0_refclk: pcie0-refclk {
> > +               compatible = "fixed-clock";
> > +                       #clock-cells = <0>;
> > +                       clock-frequency = <100000000>;
> > +       };
> > +
> >         reg_can1_stby: regulator-can1-stby {
> >                 compatible = "regulator-fixed";
> >                 regulator-name = "can1-stby"; @@ -55,6 +62,17
> @@
> > reg_can2_stby: regulator-can2-stby {
> >                 enable-active-high;
> >         };
> >
> > +       reg_pcie0: regulator-pcie {
> > +               compatible = "regulator-fixed";
> > +               pinctrl-names = "default";
> > +               pinctrl-0 = <&pinctrl_pcie0_reg>;
> > +               regulator-name = "MPCIE_3V3";
> > +               regulator-min-microvolt = <3300000>;
> > +               regulator-max-microvolt = <3300000>;
> > +               gpio = <&gpio2 6 GPIO_ACTIVE_HIGH>;
> > +               enable-active-high;
> > +       };
> > +
> >         reg_usdhc2_vmmc: regulator-usdhc2 {
> >                 compatible = "regulator-fixed";
> >                 pinctrl-names = "default"; @@ -350,6 +368,28 @@
> &i2c5
> > {
> >          */
> >  };
> >
> > +&pcie_phy {
> > +       fsl,refclk-pad-mode = <IMX8_PCIE_REFCLK_PAD_INPUT>;
> > +       clocks = <&pcie0_refclk>;
> > +       clock-names = "ref";
> > +       status = "okay";
> > +};
> > +
> > +&pcie{
> 
> Missing space before that curly brace.
> 
Good caught. Would be changed later, thanks.

Best Regards
Richard Zhu

> > +       pinctrl-names = "default";
> > +       pinctrl-0 = <&pinctrl_pcie0>;
> > +       reset-gpio = <&gpio2 7 GPIO_ACTIVE_LOW>;
> > +       clocks = <&clk IMX8MP_CLK_HSIO_ROOT>,
> > +                <&clk IMX8MP_CLK_PCIE_ROOT>,
> > +                <&clk IMX8MP_CLK_HSIO_AXI>;
> > +       clock-names = "pcie", "pcie_aux", "pcie_bus";
> > +       assigned-clocks = <&clk IMX8MP_CLK_PCIE_AUX>;
> > +       assigned-clock-rates = <10000000>;
> > +       assigned-clock-parents = <&clk IMX8MP_SYS_PLL2_50M>;
> > +       vpcie-supply = <&reg_pcie0>;
> > +       status = "okay";
> > +};
> > +
> >  &snvs_pwrkey {
> >         status = "okay";
> >  };
> > @@ -502,6 +542,19 @@
> MX8MP_IOMUXC_SPDIF_TX__I2C5_SCL
> > 0x400001c2
> >                 >;
> >         };
> >
> > +       pinctrl_pcie0: pcie0grp {
> > +               fsl,pins = <
> >
> +                       MX8MP_IOMUXC_I2C4_SCL__PCIE_CLKRE
> Q_B    0x61
> > +/* open drain, pull up */
> >
> +                       MX8MP_IOMUXC_SD1_DATA5__GPIO2_IO
> 07      0x41
> > +               >;
> > +       };
> > +
> > +       pinctrl_pcie0_reg: pcie0reggrp {
> > +               fsl,pins = <
> >
> +                       MX8MP_IOMUXC_SD1_DATA4__GPIO2_IO
> 06      0x41
> > +               >;
> > +       };
> > +
> >         pinctrl_pmic: pmicgrp {
> >                 fsl,pins = <
> >                         MX8MP_IOMUXC_GPIO1_IO03__GPIO1
> _IO03
> > 0x000001c0

[PATCH v5 4/7] reset: imx7: Fix the iMX8MP PCIe PHY PERST support

[Richard Zhu]

On i.MX7/iMX8MM/iMX8MQ, the initialized default value of PERST bit(BIT3)
of SRC_PCIEPHY_RCR is 1b'1.
But i.MX8MP has one inversed default value 1b'0 of PERST bit.

And the PERST bit should be kept 1b'1 after power and clocks are stable.
So fix the i.MX8MP PCIe PHY PERST support here.

Fixes: e08672c03981 ("reset: imx7: Add support for i.MX8MP SoC")
Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com>
Reviewed-by: Philipp Zabel <p.zabel@pengutronix.de>
Tested-by: Marek Vasut <marex@denx.de>
Tested-by: Richard Leitner <richard.leitner@skidata.com>
Tested-by: Alexander Stein <alexander.stein@ew.tq-group.com>
---
 drivers/reset/reset-imx7.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/reset/reset-imx7.c b/drivers/reset/reset-imx7.c
index 185a333df66c..d2408725eb2c 100644
--- a/drivers/reset/reset-imx7.c
+++ b/drivers/reset/reset-imx7.c
@@ -329,6 +329,7 @@ static int imx8mp_reset_set(struct reset_controller_dev *rcdev,
 		break;
 
 	case IMX8MP_RESET_PCIE_CTRL_APPS_EN:
+	case IMX8MP_RESET_PCIEPHY_PERST:
 		value = assert ? 0 : bit;
 		break;
 	}
-- 
2.25.1

Re: [PATCH v5 4/7] reset: imx7: Fix the iMX8MP PCIe PHY PERST support

[Philipp Zabel]

Hi,

On Di, 2022-08-30 at 15:46 +0800, Richard Zhu wrote:
> On i.MX7/iMX8MM/iMX8MQ, the initialized default value of PERST bit(BIT3)
> of SRC_PCIEPHY_RCR is 1b'1.
> But i.MX8MP has one inversed default value 1b'0 of PERST bit.
> 
> And the PERST bit should be kept 1b'1 after power and clocks are stable.
> So fix the i.MX8MP PCIe PHY PERST support here.
> 
> Fixes: e08672c03981 ("reset: imx7: Add support for i.MX8MP SoC")
> Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com>
> Reviewed-by: Philipp Zabel <p.zabel@pengutronix.de>
> Tested-by: Marek Vasut <marex@denx.de>
> Tested-by: Richard Leitner <richard.leitner@skidata.com>
> Tested-by: Alexander Stein <alexander.stein@ew.tq-group.com>

I've applied this patch to the reset/fixes branch.

regards
Philipp

RE: [PATCH v5 4/7] reset: imx7: Fix the iMX8MP PCIe PHY PERST support

[Hongxing Zhu]

> -----Original Message-----
> From: Philipp Zabel <p.zabel@pengutronix.de>
> Sent: 2022年8月31日 0:46
> To: Hongxing Zhu <hongxing.zhu@nxp.com>; l.stach@pengutronix.de;
> bhelgaas@google.com; lorenzo.pieralisi@arm.com; robh@kernel.org;
> shawnguo@kernel.org; vkoul@kernel.org; alexander.stein@ew.tq-group.com;
> marex@denx.de; richard.leitner@linux.dev
> Cc: linux-phy@lists.infradead.org; devicetree@vger.kernel.org;
> linux-pci@vger.kernel.org; linux-arm-kernel@lists.infradead.org;
> linux-kernel@vger.kernel.org; kernel@pengutronix.de; dl-linux-imx
> <linux-imx@nxp.com>
> Subject: Re: [PATCH v5 4/7] reset: imx7: Fix the iMX8MP PCIe PHY PERST
> support
> 
> Hi,
> 
> On Di, 2022-08-30 at 15:46 +0800, Richard Zhu wrote:
> > On i.MX7/iMX8MM/iMX8MQ, the initialized default value of PERST
> > bit(BIT3) of SRC_PCIEPHY_RCR is 1b'1.
> > But i.MX8MP has one inversed default value 1b'0 of PERST bit.
> >
> > And the PERST bit should be kept 1b'1 after power and clocks are stable.
> > So fix the i.MX8MP PCIe PHY PERST support here.
> >
> > Fixes: e08672c03981 ("reset: imx7: Add support for i.MX8MP SoC")
> > Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com>
> > Reviewed-by: Philipp Zabel <p.zabel@pengutronix.de>
> > Tested-by: Marek Vasut <marex@denx.de>
> > Tested-by: Richard Leitner <richard.leitner@skidata.com>
> > Tested-by: Alexander Stein <alexander.stein@ew.tq-group.com>
> 
> I've applied this patch to the reset/fixes branch.
> 

Thanks a lot.

Best Regards
Richard Zhu

> regards
> Philipp

[PATCH v5 5/7] soc: imx: imx8mp-blk-ctrl: handle PCIe PHY resets

[Richard Zhu]

From: Lucas Stach <l.stach@pengutronix.de>

Dessert the PHY reset when powering up the domain and put it back
into reset when the domain is powered down.

Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
---
 drivers/soc/imx/imx8mp-blk-ctrl.c | 10 ++++++++++
 1 file changed, 10 insertions(+)

diff --git a/drivers/soc/imx/imx8mp-blk-ctrl.c b/drivers/soc/imx/imx8mp-blk-ctrl.c
index 4ca2ede6871b..6c939d68ba9a 100644
--- a/drivers/soc/imx/imx8mp-blk-ctrl.c
+++ b/drivers/soc/imx/imx8mp-blk-ctrl.c
@@ -18,6 +18,8 @@
 #define GPR_REG0		0x0
 #define  PCIE_CLOCK_MODULE_EN	BIT(0)
 #define  USB_CLOCK_MODULE_EN	BIT(1)
+#define  PCIE_PHY_APB_RST	BIT(4)
+#define  PCIE_PHY_INIT_RST	BIT(5)
 
 struct imx8mp_blk_ctrl_domain;
 
@@ -75,6 +77,10 @@ static void imx8mp_hsio_blk_ctrl_power_on(struct imx8mp_blk_ctrl *bc,
 	case IMX8MP_HSIOBLK_PD_PCIE:
 		regmap_set_bits(bc->regmap, GPR_REG0, PCIE_CLOCK_MODULE_EN);
 		break;
+	case IMX8MP_HSIOBLK_PD_PCIE_PHY:
+		regmap_set_bits(bc->regmap, GPR_REG0,
+				PCIE_PHY_APB_RST | PCIE_PHY_INIT_RST);
+		break;
 	default:
 		break;
 	}
@@ -90,6 +96,10 @@ static void imx8mp_hsio_blk_ctrl_power_off(struct imx8mp_blk_ctrl *bc,
 	case IMX8MP_HSIOBLK_PD_PCIE:
 		regmap_clear_bits(bc->regmap, GPR_REG0, PCIE_CLOCK_MODULE_EN);
 		break;
+	case IMX8MP_HSIOBLK_PD_PCIE_PHY:
+		regmap_clear_bits(bc->regmap, GPR_REG0,
+				  PCIE_PHY_APB_RST | PCIE_PHY_INIT_RST);
+		break;
 	default:
 		break;
 	}
-- 
2.25.1

Re: [PATCH v5 5/7] soc: imx: imx8mp-blk-ctrl: handle PCIe PHY resets

[Lucas Stach]

Am Dienstag, dem 30.08.2022 um 15:46 +0800 schrieb Richard Zhu:
> From: Lucas Stach <l.stach@pengutronix.de>
> 
> Dessert the PHY reset when powering up the domain and put it back
> into reset when the domain is powered down.
> 
> Signed-off-by: Lucas Stach <l.stach@pengutronix.de>

According to patch submission guidelines you need to add your own sign-
off when integrating this patch into your series. Please add in the
next revision.

Regards,
Lucas

> ---
>  drivers/soc/imx/imx8mp-blk-ctrl.c | 10 ++++++++++
>  1 file changed, 10 insertions(+)
> 
> diff --git a/drivers/soc/imx/imx8mp-blk-ctrl.c b/drivers/soc/imx/imx8mp-blk-ctrl.c
> index 4ca2ede6871b..6c939d68ba9a 100644
> --- a/drivers/soc/imx/imx8mp-blk-ctrl.c
> +++ b/drivers/soc/imx/imx8mp-blk-ctrl.c
> @@ -18,6 +18,8 @@
>  #define GPR_REG0		0x0
>  #define  PCIE_CLOCK_MODULE_EN	BIT(0)
>  #define  USB_CLOCK_MODULE_EN	BIT(1)
> +#define  PCIE_PHY_APB_RST	BIT(4)
> +#define  PCIE_PHY_INIT_RST	BIT(5)
>  
>  struct imx8mp_blk_ctrl_domain;
>  
> @@ -75,6 +77,10 @@ static void imx8mp_hsio_blk_ctrl_power_on(struct imx8mp_blk_ctrl *bc,
>  	case IMX8MP_HSIOBLK_PD_PCIE:
>  		regmap_set_bits(bc->regmap, GPR_REG0, PCIE_CLOCK_MODULE_EN);
>  		break;
> +	case IMX8MP_HSIOBLK_PD_PCIE_PHY:
> +		regmap_set_bits(bc->regmap, GPR_REG0,
> +				PCIE_PHY_APB_RST | PCIE_PHY_INIT_RST);
> +		break;
>  	default:
>  		break;
>  	}
> @@ -90,6 +96,10 @@ static void imx8mp_hsio_blk_ctrl_power_off(struct imx8mp_blk_ctrl *bc,
>  	case IMX8MP_HSIOBLK_PD_PCIE:
>  		regmap_clear_bits(bc->regmap, GPR_REG0, PCIE_CLOCK_MODULE_EN);
>  		break;
> +	case IMX8MP_HSIOBLK_PD_PCIE_PHY:
> +		regmap_clear_bits(bc->regmap, GPR_REG0,
> +				  PCIE_PHY_APB_RST | PCIE_PHY_INIT_RST);
> +		break;
>  	default:
>  		break;
>  	}

RE: [PATCH v5 5/7] soc: imx: imx8mp-blk-ctrl: handle PCIe PHY resets

[Hongxing Zhu]

> -----Original Message-----
> From: Lucas Stach <l.stach@pengutronix.de>
> Sent: 2022年8月31日 16:37
> To: Hongxing Zhu <hongxing.zhu@nxp.com>; p.zabel@pengutronix.de;
> bhelgaas@google.com; lorenzo.pieralisi@arm.com; robh@kernel.org;
> shawnguo@kernel.org; vkoul@kernel.org; alexander.stein@ew.tq-group.com;
> marex@denx.de; richard.leitner@linux.dev
> Cc: linux-phy@lists.infradead.org; devicetree@vger.kernel.org;
> linux-pci@vger.kernel.org; linux-arm-kernel@lists.infradead.org;
> linux-kernel@vger.kernel.org; kernel@pengutronix.de; dl-linux-imx
> <linux-imx@nxp.com>
> Subject: Re: [PATCH v5 5/7] soc: imx: imx8mp-blk-ctrl: handle PCIe PHY resets
> 
> Am Dienstag, dem 30.08.2022 um 15:46 +0800 schrieb Richard Zhu:
> > From: Lucas Stach <l.stach@pengutronix.de>
> >
> > Dessert the PHY reset when powering up the domain and put it back into
> > reset when the domain is powered down.
> >
> > Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
> 
> According to patch submission guidelines you need to add your own sign- off
> when integrating this patch into your series. Please add in the next revision.

Okay, thanks.

Best Regards
Richard Zhu
> 
> Regards,
> Lucas
> 
> > ---
> >  drivers/soc/imx/imx8mp-blk-ctrl.c | 10 ++++++++++
> >  1 file changed, 10 insertions(+)
> >
> > diff --git a/drivers/soc/imx/imx8mp-blk-ctrl.c
> > b/drivers/soc/imx/imx8mp-blk-ctrl.c
> > index 4ca2ede6871b..6c939d68ba9a 100644
> > --- a/drivers/soc/imx/imx8mp-blk-ctrl.c
> > +++ b/drivers/soc/imx/imx8mp-blk-ctrl.c
> > @@ -18,6 +18,8 @@
> >  #define GPR_REG0		0x0
> >  #define  PCIE_CLOCK_MODULE_EN	BIT(0)
> >  #define  USB_CLOCK_MODULE_EN	BIT(1)
> > +#define  PCIE_PHY_APB_RST	BIT(4)
> > +#define  PCIE_PHY_INIT_RST	BIT(5)
> >
> >  struct imx8mp_blk_ctrl_domain;
> >
> > @@ -75,6 +77,10 @@ static void imx8mp_hsio_blk_ctrl_power_on(struct
> imx8mp_blk_ctrl *bc,
> >  	case IMX8MP_HSIOBLK_PD_PCIE:
> >  		regmap_set_bits(bc->regmap, GPR_REG0,
> PCIE_CLOCK_MODULE_EN);
> >  		break;
> > +	case IMX8MP_HSIOBLK_PD_PCIE_PHY:
> > +		regmap_set_bits(bc->regmap, GPR_REG0,
> > +				PCIE_PHY_APB_RST | PCIE_PHY_INIT_RST);
> > +		break;
> >  	default:
> >  		break;
> >  	}
> > @@ -90,6 +96,10 @@ static void imx8mp_hsio_blk_ctrl_power_off(struct
> imx8mp_blk_ctrl *bc,
> >  	case IMX8MP_HSIOBLK_PD_PCIE:
> >  		regmap_clear_bits(bc->regmap, GPR_REG0,
> PCIE_CLOCK_MODULE_EN);
> >  		break;
> > +	case IMX8MP_HSIOBLK_PD_PCIE_PHY:
> > +		regmap_clear_bits(bc->regmap, GPR_REG0,
> > +				  PCIE_PHY_APB_RST | PCIE_PHY_INIT_RST);
> > +		break;
> >  	default:
> >  		break;
> >  	}
> 

[PATCH v5 6/7] phy: freescale: imx8m-pcie: Add iMX8MP PCIe PHY support

[Richard Zhu]

Add i.MX8MP PCIe PHY support.

Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com>
Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Tested-by: Marek Vasut <marex@denx.de>
Tested-by: Richard Leitner <richard.leitner@skidata.com>
Tested-by: Alexander Stein <alexander.stein@ew.tq-group.com>
---
 drivers/phy/freescale/phy-fsl-imx8m-pcie.c | 137 +++++++++++++--------
 1 file changed, 89 insertions(+), 48 deletions(-)

diff --git a/drivers/phy/freescale/phy-fsl-imx8m-pcie.c b/drivers/phy/freescale/phy-fsl-imx8m-pcie.c
index ad7d2edfc414..c76e3a1a5f51 100644
--- a/drivers/phy/freescale/phy-fsl-imx8m-pcie.c
+++ b/drivers/phy/freescale/phy-fsl-imx8m-pcie.c
@@ -11,6 +11,9 @@
 #include <linux/mfd/syscon.h>
 #include <linux/mfd/syscon/imx7-iomuxc-gpr.h>
 #include <linux/module.h>
+#include <linux/of_address.h>
+#include <linux/of_device.h>
+#include <linux/of_device.h>
 #include <linux/phy/phy.h>
 #include <linux/platform_device.h>
 #include <linux/regmap.h>
@@ -31,12 +34,10 @@
 #define IMX8MM_PCIE_PHY_CMN_REG065	0x194
 #define  ANA_AUX_RX_TERM		(BIT(7) | BIT(4))
 #define  ANA_AUX_TX_LVL			GENMASK(3, 0)
-#define IMX8MM_PCIE_PHY_CMN_REG75	0x1D4
-#define  PCIE_PHY_CMN_REG75_PLL_DONE	0x3
+#define IMX8MM_PCIE_PHY_CMN_REG075	0x1D4
+#define  ANA_PLL_DONE			0x3
 #define PCIE_PHY_TRSV_REG5		0x414
-#define  PCIE_PHY_TRSV_REG5_GEN1_DEEMP	0x2D
 #define PCIE_PHY_TRSV_REG6		0x418
-#define  PCIE_PHY_TRSV_REG6_GEN2_DEEMP	0xF
 
 #define IMX8MM_GPR_PCIE_REF_CLK_SEL	GENMASK(25, 24)
 #define IMX8MM_GPR_PCIE_REF_CLK_PLL	FIELD_PREP(IMX8MM_GPR_PCIE_REF_CLK_SEL, 0x3)
@@ -47,16 +48,23 @@
 #define IMX8MM_GPR_PCIE_SSC_EN		BIT(16)
 #define IMX8MM_GPR_PCIE_AUX_EN_OVERRIDE	BIT(9)
 
+enum imx8_pcie_phy_type {
+	IMX8MM,
+	IMX8MP,
+};
+
 struct imx8_pcie_phy {
 	void __iomem		*base;
 	struct clk		*clk;
 	struct phy		*phy;
 	struct regmap		*iomuxc_gpr;
 	struct reset_control	*reset;
+	struct reset_control	*perst;
 	u32			refclk_pad_mode;
 	u32			tx_deemph_gen1;
 	u32			tx_deemph_gen2;
 	bool			clkreq_unused;
+	enum imx8_pcie_phy_type	variant;
 };
 
 static int imx8_pcie_phy_init(struct phy *phy)
@@ -68,31 +76,20 @@ static int imx8_pcie_phy_init(struct phy *phy)
 	reset_control_assert(imx8_phy->reset);
 
 	pad_mode = imx8_phy->refclk_pad_mode;
-	/* Set AUX_EN_OVERRIDE 1'b0, when the CLKREQ# isn't hooked */
-	regmap_update_bits(imx8_phy->iomuxc_gpr, IOMUXC_GPR14,
-			   IMX8MM_GPR_PCIE_AUX_EN_OVERRIDE,
-			   imx8_phy->clkreq_unused ?
-			   0 : IMX8MM_GPR_PCIE_AUX_EN_OVERRIDE);
-	regmap_update_bits(imx8_phy->iomuxc_gpr, IOMUXC_GPR14,
-			   IMX8MM_GPR_PCIE_AUX_EN,
-			   IMX8MM_GPR_PCIE_AUX_EN);
-	regmap_update_bits(imx8_phy->iomuxc_gpr, IOMUXC_GPR14,
-			   IMX8MM_GPR_PCIE_POWER_OFF, 0);
-	regmap_update_bits(imx8_phy->iomuxc_gpr, IOMUXC_GPR14,
-			   IMX8MM_GPR_PCIE_SSC_EN, 0);
-
-	regmap_update_bits(imx8_phy->iomuxc_gpr, IOMUXC_GPR14,
-			   IMX8MM_GPR_PCIE_REF_CLK_SEL,
-			   pad_mode == IMX8_PCIE_REFCLK_PAD_INPUT ?
-			   IMX8MM_GPR_PCIE_REF_CLK_EXT :
-			   IMX8MM_GPR_PCIE_REF_CLK_PLL);
-	usleep_range(100, 200);
-
-	/* Do the PHY common block reset */
-	regmap_update_bits(imx8_phy->iomuxc_gpr, IOMUXC_GPR14,
-			   IMX8MM_GPR_PCIE_CMN_RST,
-			   IMX8MM_GPR_PCIE_CMN_RST);
-	usleep_range(200, 500);
+	switch (imx8_phy->variant) {
+	case IMX8MM:
+		/* Tune PHY de-emphasis setting to pass PCIe compliance. */
+		if (imx8_phy->tx_deemph_gen1)
+			writel(imx8_phy->tx_deemph_gen1,
+			       imx8_phy->base + PCIE_PHY_TRSV_REG5);
+		if (imx8_phy->tx_deemph_gen2)
+			writel(imx8_phy->tx_deemph_gen2,
+			       imx8_phy->base + PCIE_PHY_TRSV_REG6);
+		break;
+	case IMX8MP:
+		reset_control_assert(imx8_phy->perst);
+		break;
+	}
 
 	if (pad_mode == IMX8_PCIE_REFCLK_PAD_INPUT ||
 	    pad_mode == IMX8_PCIE_REFCLK_PAD_UNUSED) {
@@ -120,20 +117,44 @@ static int imx8_pcie_phy_init(struct phy *phy)
 		       imx8_phy->base + IMX8MM_PCIE_PHY_CMN_REG065);
 	}
 
-	/* Tune PHY de-emphasis setting to pass PCIe compliance. */
-	if (imx8_phy->tx_deemph_gen1)
-		writel(imx8_phy->tx_deemph_gen1,
-		       imx8_phy->base + PCIE_PHY_TRSV_REG5);
-	if (imx8_phy->tx_deemph_gen2)
-		writel(imx8_phy->tx_deemph_gen2,
-		       imx8_phy->base + PCIE_PHY_TRSV_REG6);
+	/* Set AUX_EN_OVERRIDE 1'b0, when the CLKREQ# isn't hooked */
+	regmap_update_bits(imx8_phy->iomuxc_gpr, IOMUXC_GPR14,
+			   IMX8MM_GPR_PCIE_AUX_EN_OVERRIDE,
+			   imx8_phy->clkreq_unused ?
+			   0 : IMX8MM_GPR_PCIE_AUX_EN_OVERRIDE);
+	regmap_update_bits(imx8_phy->iomuxc_gpr, IOMUXC_GPR14,
+			   IMX8MM_GPR_PCIE_AUX_EN,
+			   IMX8MM_GPR_PCIE_AUX_EN);
+	regmap_update_bits(imx8_phy->iomuxc_gpr, IOMUXC_GPR14,
+			   IMX8MM_GPR_PCIE_POWER_OFF, 0);
+	regmap_update_bits(imx8_phy->iomuxc_gpr, IOMUXC_GPR14,
+			   IMX8MM_GPR_PCIE_SSC_EN, 0);
+
+	regmap_update_bits(imx8_phy->iomuxc_gpr, IOMUXC_GPR14,
+			   IMX8MM_GPR_PCIE_REF_CLK_SEL,
+			   pad_mode == IMX8_PCIE_REFCLK_PAD_INPUT ?
+			   IMX8MM_GPR_PCIE_REF_CLK_EXT :
+			   IMX8MM_GPR_PCIE_REF_CLK_PLL);
+	usleep_range(100, 200);
+
+	/* Do the PHY common block reset */
+	regmap_update_bits(imx8_phy->iomuxc_gpr, IOMUXC_GPR14,
+			   IMX8MM_GPR_PCIE_CMN_RST,
+			   IMX8MM_GPR_PCIE_CMN_RST);
 
-	reset_control_deassert(imx8_phy->reset);
+	switch (imx8_phy->variant) {
+	case IMX8MP:
+		reset_control_deassert(imx8_phy->perst);
+		fallthrough;
+	case IMX8MM:
+		reset_control_deassert(imx8_phy->reset);
+		usleep_range(200, 500);
+		break;
+	}
 
 	/* Polling to check the phy is ready or not. */
-	ret = readl_poll_timeout(imx8_phy->base + IMX8MM_PCIE_PHY_CMN_REG75,
-				 val, val == PCIE_PHY_CMN_REG75_PLL_DONE,
-				 10, 20000);
+	ret = readl_poll_timeout(imx8_phy->base + IMX8MM_PCIE_PHY_CMN_REG075,
+				 val, val == ANA_PLL_DONE, 10, 20000);
 	return ret;
 }
 
@@ -160,6 +181,13 @@ static const struct phy_ops imx8_pcie_phy_ops = {
 	.owner		= THIS_MODULE,
 };
 
+static const struct of_device_id imx8_pcie_phy_of_match[] = {
+	{.compatible = "fsl,imx8mm-pcie-phy", .data = (void *)IMX8MM},
+	{.compatible = "fsl,imx8mp-pcie-phy", .data = (void *)IMX8MP},
+	{ },
+};
+MODULE_DEVICE_TABLE(of, imx8_pcie_phy_of_match);
+
 static int imx8_pcie_phy_probe(struct platform_device *pdev)
 {
 	struct phy_provider *phy_provider;
@@ -172,6 +200,9 @@ static int imx8_pcie_phy_probe(struct platform_device *pdev)
 	if (!imx8_phy)
 		return -ENOMEM;
 
+	imx8_phy->variant =
+		(enum imx8_pcie_phy_type)of_device_get_match_data(dev);
+
 	/* get PHY refclk pad mode */
 	of_property_read_u32(np, "fsl,refclk-pad-mode",
 			     &imx8_phy->refclk_pad_mode);
@@ -196,8 +227,16 @@ static int imx8_pcie_phy_probe(struct platform_device *pdev)
 	}
 
 	/* Grab GPR config register range */
-	imx8_phy->iomuxc_gpr =
-		 syscon_regmap_lookup_by_compatible("fsl,imx6q-iomuxc-gpr");
+	switch (imx8_phy->variant) {
+	case IMX8MM:
+		imx8_phy->iomuxc_gpr =
+			 syscon_regmap_lookup_by_compatible("fsl,imx8mm-iomuxc-gpr");
+		break;
+	case IMX8MP:
+		imx8_phy->iomuxc_gpr =
+			 syscon_regmap_lookup_by_compatible("fsl,imx8mp-iomuxc-gpr");
+		break;
+	}
 	if (IS_ERR(imx8_phy->iomuxc_gpr)) {
 		dev_err(dev, "unable to find iomuxc registers\n");
 		return PTR_ERR(imx8_phy->iomuxc_gpr);
@@ -208,6 +247,14 @@ static int imx8_pcie_phy_probe(struct platform_device *pdev)
 		dev_err(dev, "Failed to get PCIEPHY reset control\n");
 		return PTR_ERR(imx8_phy->reset);
 	}
+	if (imx8_phy->variant == IMX8MP) {
+		imx8_phy->perst =
+			devm_reset_control_get_exclusive(dev, "perst");
+		if (IS_ERR(imx8_phy->perst)) {
+			dev_err(dev, "Failed to get PCIE PHY PERST control\n");
+			return PTR_ERR(imx8_phy->perst);
+		}
+	}
 
 	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 	imx8_phy->base = devm_ioremap_resource(dev, res);
@@ -225,12 +272,6 @@ static int imx8_pcie_phy_probe(struct platform_device *pdev)
 	return PTR_ERR_OR_ZERO(phy_provider);
 }
 
-static const struct of_device_id imx8_pcie_phy_of_match[] = {
-	{.compatible = "fsl,imx8mm-pcie-phy",},
-	{ },
-};
-MODULE_DEVICE_TABLE(of, imx8_pcie_phy_of_match);
-
 static struct platform_driver imx8_pcie_phy_driver = {
 	.probe	= imx8_pcie_phy_probe,
 	.driver = {
-- 
2.25.1

Re: [PATCH v5 6/7] phy: freescale: imx8m-pcie: Add iMX8MP PCIe PHY support

[Lucas Stach]

Am Dienstag, dem 30.08.2022 um 15:46 +0800 schrieb Richard Zhu:
> Add i.MX8MP PCIe PHY support.
> 
> Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com>
> Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
> Tested-by: Marek Vasut <marex@denx.de>
> Tested-by: Richard Leitner <richard.leitner@skidata.com>
> Tested-by: Alexander Stein <alexander.stein@ew.tq-group.com>
> ---
>  drivers/phy/freescale/phy-fsl-imx8m-pcie.c | 137 +++++++++++++--------
>  1 file changed, 89 insertions(+), 48 deletions(-)
> 
> diff --git a/drivers/phy/freescale/phy-fsl-imx8m-pcie.c b/drivers/phy/freescale/phy-fsl-imx8m-pcie.c
> index ad7d2edfc414..c76e3a1a5f51 100644
> --- a/drivers/phy/freescale/phy-fsl-imx8m-pcie.c
> +++ b/drivers/phy/freescale/phy-fsl-imx8m-pcie.c
> @@ -11,6 +11,9 @@
>  #include <linux/mfd/syscon.h>
>  #include <linux/mfd/syscon/imx7-iomuxc-gpr.h>
>  #include <linux/module.h>
> +#include <linux/of_address.h>
> +#include <linux/of_device.h>
> +#include <linux/of_device.h>
>  #include <linux/phy/phy.h>
>  #include <linux/platform_device.h>
>  #include <linux/regmap.h>
> @@ -31,12 +34,10 @@
>  #define IMX8MM_PCIE_PHY_CMN_REG065	0x194
>  #define  ANA_AUX_RX_TERM		(BIT(7) | BIT(4))
>  #define  ANA_AUX_TX_LVL			GENMASK(3, 0)
> -#define IMX8MM_PCIE_PHY_CMN_REG75	0x1D4
> -#define  PCIE_PHY_CMN_REG75_PLL_DONE	0x3
> +#define IMX8MM_PCIE_PHY_CMN_REG075	0x1D4
> +#define  ANA_PLL_DONE			0x3
>  #define PCIE_PHY_TRSV_REG5		0x414
> -#define  PCIE_PHY_TRSV_REG5_GEN1_DEEMP	0x2D
>  #define PCIE_PHY_TRSV_REG6		0x418
> -#define  PCIE_PHY_TRSV_REG6_GEN2_DEEMP	0xF
>  
>  #define IMX8MM_GPR_PCIE_REF_CLK_SEL	GENMASK(25, 24)
>  #define IMX8MM_GPR_PCIE_REF_CLK_PLL	FIELD_PREP(IMX8MM_GPR_PCIE_REF_CLK_SEL, 0x3)
> @@ -47,16 +48,23 @@
>  #define IMX8MM_GPR_PCIE_SSC_EN		BIT(16)
>  #define IMX8MM_GPR_PCIE_AUX_EN_OVERRIDE	BIT(9)
>  
> +enum imx8_pcie_phy_type {
> +	IMX8MM,
> +	IMX8MP,
> +};
> +
>  struct imx8_pcie_phy {
>  	void __iomem		*base;
>  	struct clk		*clk;
>  	struct phy		*phy;
>  	struct regmap		*iomuxc_gpr;
>  	struct reset_control	*reset;
> +	struct reset_control	*perst;
>  	u32			refclk_pad_mode;
>  	u32			tx_deemph_gen1;
>  	u32			tx_deemph_gen2;
>  	bool			clkreq_unused;
> +	enum imx8_pcie_phy_type	variant;
>  };
>  
>  static int imx8_pcie_phy_init(struct phy *phy)
> @@ -68,31 +76,20 @@ static int imx8_pcie_phy_init(struct phy *phy)
>  	reset_control_assert(imx8_phy->reset);
>  
>  	pad_mode = imx8_phy->refclk_pad_mode;
> -	/* Set AUX_EN_OVERRIDE 1'b0, when the CLKREQ# isn't hooked */
> -	regmap_update_bits(imx8_phy->iomuxc_gpr, IOMUXC_GPR14,
> -			   IMX8MM_GPR_PCIE_AUX_EN_OVERRIDE,
> -			   imx8_phy->clkreq_unused ?
> -			   0 : IMX8MM_GPR_PCIE_AUX_EN_OVERRIDE);
> -	regmap_update_bits(imx8_phy->iomuxc_gpr, IOMUXC_GPR14,
> -			   IMX8MM_GPR_PCIE_AUX_EN,
> -			   IMX8MM_GPR_PCIE_AUX_EN);
> -	regmap_update_bits(imx8_phy->iomuxc_gpr, IOMUXC_GPR14,
> -			   IMX8MM_GPR_PCIE_POWER_OFF, 0);
> -	regmap_update_bits(imx8_phy->iomuxc_gpr, IOMUXC_GPR14,
> -			   IMX8MM_GPR_PCIE_SSC_EN, 0);
> -
> -	regmap_update_bits(imx8_phy->iomuxc_gpr, IOMUXC_GPR14,
> -			   IMX8MM_GPR_PCIE_REF_CLK_SEL,
> -			   pad_mode == IMX8_PCIE_REFCLK_PAD_INPUT ?
> -			   IMX8MM_GPR_PCIE_REF_CLK_EXT :
> -			   IMX8MM_GPR_PCIE_REF_CLK_PLL);
> -	usleep_range(100, 200);
> -
> -	/* Do the PHY common block reset */
> -	regmap_update_bits(imx8_phy->iomuxc_gpr, IOMUXC_GPR14,
> -			   IMX8MM_GPR_PCIE_CMN_RST,
> -			   IMX8MM_GPR_PCIE_CMN_RST);
> -	usleep_range(200, 500);
> +	switch (imx8_phy->variant) {
> +	case IMX8MM:
> +		/* Tune PHY de-emphasis setting to pass PCIe compliance. */
> +		if (imx8_phy->tx_deemph_gen1)
> +			writel(imx8_phy->tx_deemph_gen1,
> +			       imx8_phy->base + PCIE_PHY_TRSV_REG5);
> +		if (imx8_phy->tx_deemph_gen2)
> +			writel(imx8_phy->tx_deemph_gen2,
> +			       imx8_phy->base + PCIE_PHY_TRSV_REG6);
> +		break;
> +	case IMX8MP:
> +		reset_control_assert(imx8_phy->perst);
> +		break;
> +	}
>  
>  	if (pad_mode == IMX8_PCIE_REFCLK_PAD_INPUT ||
>  	    pad_mode == IMX8_PCIE_REFCLK_PAD_UNUSED) {
> @@ -120,20 +117,44 @@ static int imx8_pcie_phy_init(struct phy *phy)
>  		       imx8_phy->base + IMX8MM_PCIE_PHY_CMN_REG065);
>  	}
>  
> -	/* Tune PHY de-emphasis setting to pass PCIe compliance. */
> -	if (imx8_phy->tx_deemph_gen1)
> -		writel(imx8_phy->tx_deemph_gen1,
> -		       imx8_phy->base + PCIE_PHY_TRSV_REG5);
> -	if (imx8_phy->tx_deemph_gen2)
> -		writel(imx8_phy->tx_deemph_gen2,
> -		       imx8_phy->base + PCIE_PHY_TRSV_REG6);
> +	/* Set AUX_EN_OVERRIDE 1'b0, when the CLKREQ# isn't hooked */
> +	regmap_update_bits(imx8_phy->iomuxc_gpr, IOMUXC_GPR14,
> +			   IMX8MM_GPR_PCIE_AUX_EN_OVERRIDE,
> +			   imx8_phy->clkreq_unused ?
> +			   0 : IMX8MM_GPR_PCIE_AUX_EN_OVERRIDE);
> +	regmap_update_bits(imx8_phy->iomuxc_gpr, IOMUXC_GPR14,
> +			   IMX8MM_GPR_PCIE_AUX_EN,
> +			   IMX8MM_GPR_PCIE_AUX_EN);
> +	regmap_update_bits(imx8_phy->iomuxc_gpr, IOMUXC_GPR14,
> +			   IMX8MM_GPR_PCIE_POWER_OFF, 0);
> +	regmap_update_bits(imx8_phy->iomuxc_gpr, IOMUXC_GPR14,
> +			   IMX8MM_GPR_PCIE_SSC_EN, 0);
> +
> +	regmap_update_bits(imx8_phy->iomuxc_gpr, IOMUXC_GPR14,
> +			   IMX8MM_GPR_PCIE_REF_CLK_SEL,
> +			   pad_mode == IMX8_PCIE_REFCLK_PAD_INPUT ?
> +			   IMX8MM_GPR_PCIE_REF_CLK_EXT :
> +			   IMX8MM_GPR_PCIE_REF_CLK_PLL);
> +	usleep_range(100, 200);
> +
> +	/* Do the PHY common block reset */
> +	regmap_update_bits(imx8_phy->iomuxc_gpr, IOMUXC_GPR14,
> +			   IMX8MM_GPR_PCIE_CMN_RST,
> +			   IMX8MM_GPR_PCIE_CMN_RST);
>  
> -	reset_control_deassert(imx8_phy->reset);
> +	switch (imx8_phy->variant) {
> +	case IMX8MP:
> +		reset_control_deassert(imx8_phy->perst);
> +		fallthrough;
> +	case IMX8MM:
> +		reset_control_deassert(imx8_phy->reset);
> +		usleep_range(200, 500);
> +		break;
> +	}
>  
>  	/* Polling to check the phy is ready or not. */
> -	ret = readl_poll_timeout(imx8_phy->base + IMX8MM_PCIE_PHY_CMN_REG75,
> -				 val, val == PCIE_PHY_CMN_REG75_PLL_DONE,
> -				 10, 20000);
> +	ret = readl_poll_timeout(imx8_phy->base + IMX8MM_PCIE_PHY_CMN_REG075,
> +				 val, val == ANA_PLL_DONE, 10, 20000);
>  	return ret;
>  }
>  
> @@ -160,6 +181,13 @@ static const struct phy_ops imx8_pcie_phy_ops = {
>  	.owner		= THIS_MODULE,
>  };
>  
> +static const struct of_device_id imx8_pcie_phy_of_match[] = {
> +	{.compatible = "fsl,imx8mm-pcie-phy", .data = (void *)IMX8MM},
> +	{.compatible = "fsl,imx8mp-pcie-phy", .data = (void *)IMX8MP},
> +	{ },
> +};
> +MODULE_DEVICE_TABLE(of, imx8_pcie_phy_of_match);
> +
>  static int imx8_pcie_phy_probe(struct platform_device *pdev)
>  {
>  	struct phy_provider *phy_provider;
> @@ -172,6 +200,9 @@ static int imx8_pcie_phy_probe(struct platform_device *pdev)
>  	if (!imx8_phy)
>  		return -ENOMEM;
>  
> +	imx8_phy->variant =
> +		(enum imx8_pcie_phy_type)of_device_get_match_data(dev);
> +
>  	/* get PHY refclk pad mode */
>  	of_property_read_u32(np, "fsl,refclk-pad-mode",
>  			     &imx8_phy->refclk_pad_mode);
> @@ -196,8 +227,16 @@ static int imx8_pcie_phy_probe(struct platform_device *pdev)
>  	}
>  
>  	/* Grab GPR config register range */
> -	imx8_phy->iomuxc_gpr =
> -		 syscon_regmap_lookup_by_compatible("fsl,imx6q-iomuxc-gpr");
> +	switch (imx8_phy->variant) {
> +	case IMX8MM:
> +		imx8_phy->iomuxc_gpr =
> +			 syscon_regmap_lookup_by_compatible("fsl,imx8mm-iomuxc-gpr");
> +		break;
> +	case IMX8MP:
> +		imx8_phy->iomuxc_gpr =
> +			 syscon_regmap_lookup_by_compatible("fsl,imx8mp-iomuxc-gpr");
> +		break;
> +	}

Oh, I had a real phandle in DT in mind for this, but I see how this
would be hard to introduce in a backward compatible manner for the 8MM.
At least this way it is fully contained in the driver and doesn't leak
into DT compatibles.

Maybe we could make this a little nicer by just having an const array
of iomux syscon compatibles indexed by imx8_phy->variant, to avoid the
switch and the resulting code (almost-)duplication.

Regards,
Lucas

>  	if (IS_ERR(imx8_phy->iomuxc_gpr)) {
>  		dev_err(dev, "unable to find iomuxc registers\n");
>  		return PTR_ERR(imx8_phy->iomuxc_gpr);
> @@ -208,6 +247,14 @@ static int imx8_pcie_phy_probe(struct platform_device *pdev)
>  		dev_err(dev, "Failed to get PCIEPHY reset control\n");
>  		return PTR_ERR(imx8_phy->reset);
>  	}
> +	if (imx8_phy->variant == IMX8MP) {
> +		imx8_phy->perst =
> +			devm_reset_control_get_exclusive(dev, "perst");
> +		if (IS_ERR(imx8_phy->perst)) {
> +			dev_err(dev, "Failed to get PCIE PHY PERST control\n");
> +			return PTR_ERR(imx8_phy->perst);
> +		}
> +	}
>  
>  	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
>  	imx8_phy->base = devm_ioremap_resource(dev, res);
> @@ -225,12 +272,6 @@ static int imx8_pcie_phy_probe(struct platform_device *pdev)
>  	return PTR_ERR_OR_ZERO(phy_provider);
>  }
>  
> -static const struct of_device_id imx8_pcie_phy_of_match[] = {
> -	{.compatible = "fsl,imx8mm-pcie-phy",},
> -	{ },
> -};
> -MODULE_DEVICE_TABLE(of, imx8_pcie_phy_of_match);
> -
>  static struct platform_driver imx8_pcie_phy_driver = {
>  	.probe	= imx8_pcie_phy_probe,
>  	.driver = {

RE: [PATCH v5 6/7] phy: freescale: imx8m-pcie: Add iMX8MP PCIe PHY support

[Hongxing Zhu]

> -----Original Message-----
> From: Lucas Stach <l.stach@pengutronix.de>
> Sent: 2022年8月30日 21:07
> To: Hongxing Zhu <hongxing.zhu@nxp.com>; p.zabel@pengutronix.de;
> bhelgaas@google.com; lorenzo.pieralisi@arm.com; robh@kernel.org;
> shawnguo@kernel.org; vkoul@kernel.org; alexander.stein@ew.tq-group.com;
> marex@denx.de; richard.leitner@linux.dev
> Cc: linux-phy@lists.infradead.org; devicetree@vger.kernel.org;
> linux-pci@vger.kernel.org; linux-arm-kernel@lists.infradead.org;
> linux-kernel@vger.kernel.org; kernel@pengutronix.de; dl-linux-imx
> <linux-imx@nxp.com>
> Subject: Re: [PATCH v5 6/7] phy: freescale: imx8m-pcie: Add iMX8MP PCIe PHY
> support
> 
> Am Dienstag, dem 30.08.2022 um 15:46 +0800 schrieb Richard Zhu:
> > Add i.MX8MP PCIe PHY support.
> >
> > Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com>
> > Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
> > Tested-by: Marek Vasut <marex@denx.de>
> > Tested-by: Richard Leitner <richard.leitner@skidata.com>
> > Tested-by: Alexander Stein <alexander.stein@ew.tq-group.com>
> > ---
> >  drivers/phy/freescale/phy-fsl-imx8m-pcie.c | 137
> > +++++++++++++--------
> >  1 file changed, 89 insertions(+), 48 deletions(-)
> >
> > diff --git a/drivers/phy/freescale/phy-fsl-imx8m-pcie.c
> > b/drivers/phy/freescale/phy-fsl-imx8m-pcie.c
> > index ad7d2edfc414..c76e3a1a5f51 100644
> > --- a/drivers/phy/freescale/phy-fsl-imx8m-pcie.c
> > +++ b/drivers/phy/freescale/phy-fsl-imx8m-pcie.c
> > @@ -11,6 +11,9 @@
> >  #include <linux/mfd/syscon.h>
> >  #include <linux/mfd/syscon/imx7-iomuxc-gpr.h>
> >  #include <linux/module.h>
> > +#include <linux/of_address.h>
> > +#include <linux/of_device.h>
> > +#include <linux/of_device.h>
> >  #include <linux/phy/phy.h>
> >  #include <linux/platform_device.h>
> >  #include <linux/regmap.h>
> > @@ -31,12 +34,10 @@
> >  #define IMX8MM_PCIE_PHY_CMN_REG065	0x194
> >  #define  ANA_AUX_RX_TERM		(BIT(7) | BIT(4))
> >  #define  ANA_AUX_TX_LVL			GENMASK(3, 0)
> > -#define IMX8MM_PCIE_PHY_CMN_REG75	0x1D4
> > -#define  PCIE_PHY_CMN_REG75_PLL_DONE	0x3
> > +#define IMX8MM_PCIE_PHY_CMN_REG075	0x1D4
> > +#define  ANA_PLL_DONE			0x3
> >  #define PCIE_PHY_TRSV_REG5		0x414
> > -#define  PCIE_PHY_TRSV_REG5_GEN1_DEEMP	0x2D
> >  #define PCIE_PHY_TRSV_REG6		0x418
> > -#define  PCIE_PHY_TRSV_REG6_GEN2_DEEMP	0xF
> >
> >  #define IMX8MM_GPR_PCIE_REF_CLK_SEL	GENMASK(25, 24)
> >  #define IMX8MM_GPR_PCIE_REF_CLK_PLL
> 	FIELD_PREP(IMX8MM_GPR_PCIE_REF_CLK_SEL, 0x3)
> > @@ -47,16 +48,23 @@
> >  #define IMX8MM_GPR_PCIE_SSC_EN		BIT(16)
> >  #define IMX8MM_GPR_PCIE_AUX_EN_OVERRIDE	BIT(9)
> >
> > +enum imx8_pcie_phy_type {
> > +	IMX8MM,
> > +	IMX8MP,
> > +};
> > +
> >  struct imx8_pcie_phy {
> >  	void __iomem		*base;
> >  	struct clk		*clk;
> >  	struct phy		*phy;
> >  	struct regmap		*iomuxc_gpr;
> >  	struct reset_control	*reset;
> > +	struct reset_control	*perst;
> >  	u32			refclk_pad_mode;
> >  	u32			tx_deemph_gen1;
> >  	u32			tx_deemph_gen2;
> >  	bool			clkreq_unused;
> > +	enum imx8_pcie_phy_type	variant;
> >  };
> >
> >  static int imx8_pcie_phy_init(struct phy *phy) @@ -68,31 +76,20 @@
> > static int imx8_pcie_phy_init(struct phy *phy)
> >  	reset_control_assert(imx8_phy->reset);
> >
> >  	pad_mode = imx8_phy->refclk_pad_mode;
> > -	/* Set AUX_EN_OVERRIDE 1'b0, when the CLKREQ# isn't hooked */
> > -	regmap_update_bits(imx8_phy->iomuxc_gpr, IOMUXC_GPR14,
> > -			   IMX8MM_GPR_PCIE_AUX_EN_OVERRIDE,
> > -			   imx8_phy->clkreq_unused ?
> > -			   0 : IMX8MM_GPR_PCIE_AUX_EN_OVERRIDE);
> > -	regmap_update_bits(imx8_phy->iomuxc_gpr, IOMUXC_GPR14,
> > -			   IMX8MM_GPR_PCIE_AUX_EN,
> > -			   IMX8MM_GPR_PCIE_AUX_EN);
> > -	regmap_update_bits(imx8_phy->iomuxc_gpr, IOMUXC_GPR14,
> > -			   IMX8MM_GPR_PCIE_POWER_OFF, 0);
> > -	regmap_update_bits(imx8_phy->iomuxc_gpr, IOMUXC_GPR14,
> > -			   IMX8MM_GPR_PCIE_SSC_EN, 0);
> > -
> > -	regmap_update_bits(imx8_phy->iomuxc_gpr, IOMUXC_GPR14,
> > -			   IMX8MM_GPR_PCIE_REF_CLK_SEL,
> > -			   pad_mode == IMX8_PCIE_REFCLK_PAD_INPUT ?
> > -			   IMX8MM_GPR_PCIE_REF_CLK_EXT :
> > -			   IMX8MM_GPR_PCIE_REF_CLK_PLL);
> > -	usleep_range(100, 200);
> > -
> > -	/* Do the PHY common block reset */
> > -	regmap_update_bits(imx8_phy->iomuxc_gpr, IOMUXC_GPR14,
> > -			   IMX8MM_GPR_PCIE_CMN_RST,
> > -			   IMX8MM_GPR_PCIE_CMN_RST);
> > -	usleep_range(200, 500);
> > +	switch (imx8_phy->variant) {
> > +	case IMX8MM:
> > +		/* Tune PHY de-emphasis setting to pass PCIe compliance. */
> > +		if (imx8_phy->tx_deemph_gen1)
> > +			writel(imx8_phy->tx_deemph_gen1,
> > +			       imx8_phy->base + PCIE_PHY_TRSV_REG5);
> > +		if (imx8_phy->tx_deemph_gen2)
> > +			writel(imx8_phy->tx_deemph_gen2,
> > +			       imx8_phy->base + PCIE_PHY_TRSV_REG6);
> > +		break;
> > +	case IMX8MP:
> > +		reset_control_assert(imx8_phy->perst);
> > +		break;
> > +	}
> >
> >  	if (pad_mode == IMX8_PCIE_REFCLK_PAD_INPUT ||
> >  	    pad_mode == IMX8_PCIE_REFCLK_PAD_UNUSED) { @@ -120,20
> +117,44 @@
> > static int imx8_pcie_phy_init(struct phy *phy)
> >  		       imx8_phy->base + IMX8MM_PCIE_PHY_CMN_REG065);
> >  	}
> >
> > -	/* Tune PHY de-emphasis setting to pass PCIe compliance. */
> > -	if (imx8_phy->tx_deemph_gen1)
> > -		writel(imx8_phy->tx_deemph_gen1,
> > -		       imx8_phy->base + PCIE_PHY_TRSV_REG5);
> > -	if (imx8_phy->tx_deemph_gen2)
> > -		writel(imx8_phy->tx_deemph_gen2,
> > -		       imx8_phy->base + PCIE_PHY_TRSV_REG6);
> > +	/* Set AUX_EN_OVERRIDE 1'b0, when the CLKREQ# isn't hooked */
> > +	regmap_update_bits(imx8_phy->iomuxc_gpr, IOMUXC_GPR14,
> > +			   IMX8MM_GPR_PCIE_AUX_EN_OVERRIDE,
> > +			   imx8_phy->clkreq_unused ?
> > +			   0 : IMX8MM_GPR_PCIE_AUX_EN_OVERRIDE);
> > +	regmap_update_bits(imx8_phy->iomuxc_gpr, IOMUXC_GPR14,
> > +			   IMX8MM_GPR_PCIE_AUX_EN,
> > +			   IMX8MM_GPR_PCIE_AUX_EN);
> > +	regmap_update_bits(imx8_phy->iomuxc_gpr, IOMUXC_GPR14,
> > +			   IMX8MM_GPR_PCIE_POWER_OFF, 0);
> > +	regmap_update_bits(imx8_phy->iomuxc_gpr, IOMUXC_GPR14,
> > +			   IMX8MM_GPR_PCIE_SSC_EN, 0);
> > +
> > +	regmap_update_bits(imx8_phy->iomuxc_gpr, IOMUXC_GPR14,
> > +			   IMX8MM_GPR_PCIE_REF_CLK_SEL,
> > +			   pad_mode == IMX8_PCIE_REFCLK_PAD_INPUT ?
> > +			   IMX8MM_GPR_PCIE_REF_CLK_EXT :
> > +			   IMX8MM_GPR_PCIE_REF_CLK_PLL);
> > +	usleep_range(100, 200);
> > +
> > +	/* Do the PHY common block reset */
> > +	regmap_update_bits(imx8_phy->iomuxc_gpr, IOMUXC_GPR14,
> > +			   IMX8MM_GPR_PCIE_CMN_RST,
> > +			   IMX8MM_GPR_PCIE_CMN_RST);
> >
> > -	reset_control_deassert(imx8_phy->reset);
> > +	switch (imx8_phy->variant) {
> > +	case IMX8MP:
> > +		reset_control_deassert(imx8_phy->perst);
> > +		fallthrough;
> > +	case IMX8MM:
> > +		reset_control_deassert(imx8_phy->reset);
> > +		usleep_range(200, 500);
> > +		break;
> > +	}
> >
> >  	/* Polling to check the phy is ready or not. */
> > -	ret = readl_poll_timeout(imx8_phy->base +
> IMX8MM_PCIE_PHY_CMN_REG75,
> > -				 val, val == PCIE_PHY_CMN_REG75_PLL_DONE,
> > -				 10, 20000);
> > +	ret = readl_poll_timeout(imx8_phy->base +
> IMX8MM_PCIE_PHY_CMN_REG075,
> > +				 val, val == ANA_PLL_DONE, 10, 20000);
> >  	return ret;
> >  }
> >
> > @@ -160,6 +181,13 @@ static const struct phy_ops imx8_pcie_phy_ops = {
> >  	.owner		= THIS_MODULE,
> >  };
> >
> > +static const struct of_device_id imx8_pcie_phy_of_match[] = {
> > +	{.compatible = "fsl,imx8mm-pcie-phy", .data = (void *)IMX8MM},
> > +	{.compatible = "fsl,imx8mp-pcie-phy", .data = (void *)IMX8MP},
> > +	{ },
> > +};
> > +MODULE_DEVICE_TABLE(of, imx8_pcie_phy_of_match);
> > +
> >  static int imx8_pcie_phy_probe(struct platform_device *pdev)  {
> >  	struct phy_provider *phy_provider;
> > @@ -172,6 +200,9 @@ static int imx8_pcie_phy_probe(struct
> platform_device *pdev)
> >  	if (!imx8_phy)
> >  		return -ENOMEM;
> >
> > +	imx8_phy->variant =
> > +		(enum imx8_pcie_phy_type)of_device_get_match_data(dev);
> > +
> >  	/* get PHY refclk pad mode */
> >  	of_property_read_u32(np, "fsl,refclk-pad-mode",
> >  			     &imx8_phy->refclk_pad_mode);
> > @@ -196,8 +227,16 @@ static int imx8_pcie_phy_probe(struct
> platform_device *pdev)
> >  	}
> >
> >  	/* Grab GPR config register range */
> > -	imx8_phy->iomuxc_gpr =
> > -		 syscon_regmap_lookup_by_compatible("fsl,imx6q-iomuxc-gpr");
> > +	switch (imx8_phy->variant) {
> > +	case IMX8MM:
> > +		imx8_phy->iomuxc_gpr =
> > +
> syscon_regmap_lookup_by_compatible("fsl,imx8mm-iomuxc-gpr");
> > +		break;
> > +	case IMX8MP:
> > +		imx8_phy->iomuxc_gpr =
> > +
> syscon_regmap_lookup_by_compatible("fsl,imx8mp-iomuxc-gpr");
> > +		break;
> > +	}
> 
> Oh, I had a real phandle in DT in mind for this, but I see how this would be
> hard to introduce in a backward compatible manner for the 8MM.
> At least this way it is fully contained in the driver and doesn't leak into DT
> compatibles.
> 
> Maybe we could make this a little nicer by just having an const array of iomux
> syscon compatibles indexed by imx8_phy->variant, to avoid the switch and the
> resulting code (almost-)duplication.
> 
Hi Lucas:
Thanks for your comments.
Do you mean a drvdata struct indexed by variant, and contains the const array
of iomux syscon compatible like below?

+static const struct imx8_pcie_phy_drvdata drvdata[] = {
+       [IMX8MM] = {
+               .variant = IMX8MM,
+               .gpr = "fsl,imx8mm-iomuxc-gpr",
+       },
+
+       [IMX8MP] = {
+               .variant = IMX8MP,
+               .gpr = "fsl,imx8mp-iomuxc-gpr",
+       },
+};
+

Then, we can get the drvdata, and find the according gpr syscon regmap below.

+       imx8_phy->drvdata = of_device_get_match_data(dev);
...
+       imx8_phy->iomuxc_gpr =
+                syscon_regmap_lookup_by_compatible(imx8_phy->drvdata->gpr);

If yes, I would do the changes, and issue the v6 later.

Best Regards
Richard Zhu

> Regards,
> Lucas
> 
> >  	if (IS_ERR(imx8_phy->iomuxc_gpr)) {
> >  		dev_err(dev, "unable to find iomuxc registers\n");
> >  		return PTR_ERR(imx8_phy->iomuxc_gpr); @@ -208,6 +247,14 @@
> static
> > int imx8_pcie_phy_probe(struct platform_device *pdev)
> >  		dev_err(dev, "Failed to get PCIEPHY reset control\n");
> >  		return PTR_ERR(imx8_phy->reset);
> >  	}
> > +	if (imx8_phy->variant == IMX8MP) {
> > +		imx8_phy->perst =
> > +			devm_reset_control_get_exclusive(dev, "perst");
> > +		if (IS_ERR(imx8_phy->perst)) {
> > +			dev_err(dev, "Failed to get PCIE PHY PERST control\n");
> > +			return PTR_ERR(imx8_phy->perst);
> > +		}
> > +	}
> >
> >  	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
> >  	imx8_phy->base = devm_ioremap_resource(dev, res); @@ -225,12 +272,6
> > @@ static int imx8_pcie_phy_probe(struct platform_device *pdev)
> >  	return PTR_ERR_OR_ZERO(phy_provider);  }
> >
> > -static const struct of_device_id imx8_pcie_phy_of_match[] = {
> > -	{.compatible = "fsl,imx8mm-pcie-phy",},
> > -	{ },
> > -};
> > -MODULE_DEVICE_TABLE(of, imx8_pcie_phy_of_match);
> > -
> >  static struct platform_driver imx8_pcie_phy_driver = {
> >  	.probe	= imx8_pcie_phy_probe,
> >  	.driver = {
> 

Re: [PATCH v5 6/7] phy: freescale: imx8m-pcie: Add iMX8MP PCIe PHY support

[Lucas Stach]

Am Mittwoch, dem 31.08.2022 um 06:16 +0000 schrieb Hongxing Zhu:
> > -----Original Message-----
> > From: Lucas Stach <l.stach@pengutronix.de>
> > Sent: 2022年8月30日 21:07
> > To: Hongxing Zhu <hongxing.zhu@nxp.com>; p.zabel@pengutronix.de;
> > bhelgaas@google.com; lorenzo.pieralisi@arm.com; robh@kernel.org;
> > shawnguo@kernel.org; vkoul@kernel.org;
> > alexander.stein@ew.tq-group.com;
> > marex@denx.de; richard.leitner@linux.dev
> > Cc: linux-phy@lists.infradead.org; devicetree@vger.kernel.org;
> > linux-pci@vger.kernel.org; linux-arm-kernel@lists.infradead.org;
> > linux-kernel@vger.kernel.org; kernel@pengutronix.de; dl-linux-imx
> > <linux-imx@nxp.com>
> > Subject: Re: [PATCH v5 6/7] phy: freescale: imx8m-pcie: Add iMX8MP
> > PCIe PHY
> > support
> > 
> > Am Dienstag, dem 30.08.2022 um 15:46 +0800 schrieb Richard Zhu:
> > > Add i.MX8MP PCIe PHY support.
> > > 
> > > Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com>
> > > Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
> > > Tested-by: Marek Vasut <marex@denx.de>
> > > Tested-by: Richard Leitner <richard.leitner@skidata.com>
> > > Tested-by: Alexander Stein <alexander.stein@ew.tq-group.com>
> > > ---
> > >  drivers/phy/freescale/phy-fsl-imx8m-pcie.c | 137
> > > +++++++++++++--------
> > >  1 file changed, 89 insertions(+), 48 deletions(-)
> > > 
> > > diff --git a/drivers/phy/freescale/phy-fsl-imx8m-pcie.c
> > > b/drivers/phy/freescale/phy-fsl-imx8m-pcie.c
> > > index ad7d2edfc414..c76e3a1a5f51 100644
> > > --- a/drivers/phy/freescale/phy-fsl-imx8m-pcie.c
> > > +++ b/drivers/phy/freescale/phy-fsl-imx8m-pcie.c
> > > @@ -11,6 +11,9 @@
> > >  #include <linux/mfd/syscon.h>
> > >  #include <linux/mfd/syscon/imx7-iomuxc-gpr.h>
> > >  #include <linux/module.h>
> > > +#include <linux/of_address.h>
> > > +#include <linux/of_device.h>
> > > +#include <linux/of_device.h>
> > >  #include <linux/phy/phy.h>
> > >  #include <linux/platform_device.h>
> > >  #include <linux/regmap.h>
> > > @@ -31,12 +34,10 @@
> > >  #define IMX8MM_PCIE_PHY_CMN_REG065	0x194
> > >  #define  ANA_AUX_RX_TERM		(BIT(7) | BIT(4))
> > >  #define  ANA_AUX_TX_LVL			GENMASK(3, 0)
> > > -#define IMX8MM_PCIE_PHY_CMN_REG75	0x1D4
> > > -#define  PCIE_PHY_CMN_REG75_PLL_DONE	0x3
> > > +#define IMX8MM_PCIE_PHY_CMN_REG075	0x1D4
> > > +#define  ANA_PLL_DONE			0x3
> > >  #define PCIE_PHY_TRSV_REG5		0x414
> > > -#define  PCIE_PHY_TRSV_REG5_GEN1_DEEMP	0x2D
> > >  #define PCIE_PHY_TRSV_REG6		0x418
> > > -#define  PCIE_PHY_TRSV_REG6_GEN2_DEEMP	0xF
> > > 
> > >  #define IMX8MM_GPR_PCIE_REF_CLK_SEL	GENMASK(25, 24)
> > >  #define IMX8MM_GPR_PCIE_REF_CLK_PLL
> > 	FIELD_PREP(IMX8MM_GPR_PCIE_REF_CLK_SEL, 0x3)
> > > @@ -47,16 +48,23 @@
> > >  #define IMX8MM_GPR_PCIE_SSC_EN		BIT(16)
> > >  #define IMX8MM_GPR_PCIE_AUX_EN_OVERRIDE	BIT(9)
> > > 
> > > +enum imx8_pcie_phy_type {
> > > +	IMX8MM,
> > > +	IMX8MP,
> > > +};
> > > +
> > >  struct imx8_pcie_phy {
> > >  	void __iomem		*base;
> > >  	struct clk		*clk;
> > >  	struct phy		*phy;
> > >  	struct regmap		*iomuxc_gpr;
> > >  	struct reset_control	*reset;
> > > +	struct reset_control	*perst;
> > >  	u32			refclk_pad_mode;
> > >  	u32			tx_deemph_gen1;
> > >  	u32			tx_deemph_gen2;
> > >  	bool			clkreq_unused;
> > > +	enum imx8_pcie_phy_type	variant;
> > >  };
> > > 
> > >  static int imx8_pcie_phy_init(struct phy *phy) @@ -68,31 +76,20
> > > @@
> > > static int imx8_pcie_phy_init(struct phy *phy)
> > >  	reset_control_assert(imx8_phy->reset);
> > > 
> > >  	pad_mode = imx8_phy->refclk_pad_mode;
> > > -	/* Set AUX_EN_OVERRIDE 1'b0, when the CLKREQ# isn't
> > > hooked */
> > > -	regmap_update_bits(imx8_phy->iomuxc_gpr, IOMUXC_GPR14,
> > > -			   IMX8MM_GPR_PCIE_AUX_EN_OVERRIDE,
> > > -			   imx8_phy->clkreq_unused ?
> > > -			   0 : IMX8MM_GPR_PCIE_AUX_EN_OVERRIDE);
> > > -	regmap_update_bits(imx8_phy->iomuxc_gpr, IOMUXC_GPR14,
> > > -			   IMX8MM_GPR_PCIE_AUX_EN,
> > > -			   IMX8MM_GPR_PCIE_AUX_EN);
> > > -	regmap_update_bits(imx8_phy->iomuxc_gpr, IOMUXC_GPR14,
> > > -			   IMX8MM_GPR_PCIE_POWER_OFF, 0);
> > > -	regmap_update_bits(imx8_phy->iomuxc_gpr, IOMUXC_GPR14,
> > > -			   IMX8MM_GPR_PCIE_SSC_EN, 0);
> > > -
> > > -	regmap_update_bits(imx8_phy->iomuxc_gpr, IOMUXC_GPR14,
> > > -			   IMX8MM_GPR_PCIE_REF_CLK_SEL,
> > > -			   pad_mode ==
> > > IMX8_PCIE_REFCLK_PAD_INPUT ?
> > > -			   IMX8MM_GPR_PCIE_REF_CLK_EXT :
> > > -			   IMX8MM_GPR_PCIE_REF_CLK_PLL);
> > > -	usleep_range(100, 200);
> > > -
> > > -	/* Do the PHY common block reset */
> > > -	regmap_update_bits(imx8_phy->iomuxc_gpr, IOMUXC_GPR14,
> > > -			   IMX8MM_GPR_PCIE_CMN_RST,
> > > -			   IMX8MM_GPR_PCIE_CMN_RST);
> > > -	usleep_range(200, 500);
> > > +	switch (imx8_phy->variant) {
> > > +	case IMX8MM:
> > > +		/* Tune PHY de-emphasis setting to pass PCIe
> > > compliance. */
> > > +		if (imx8_phy->tx_deemph_gen1)
> > > +			writel(imx8_phy->tx_deemph_gen1,
> > > +			       imx8_phy->base +
> > > PCIE_PHY_TRSV_REG5);
> > > +		if (imx8_phy->tx_deemph_gen2)
> > > +			writel(imx8_phy->tx_deemph_gen2,
> > > +			       imx8_phy->base +
> > > PCIE_PHY_TRSV_REG6);
> > > +		break;
> > > +	case IMX8MP:
> > > +		reset_control_assert(imx8_phy->perst);
> > > +		break;
> > > +	}
> > > 
> > >  	if (pad_mode == IMX8_PCIE_REFCLK_PAD_INPUT ||
> > >  	    pad_mode == IMX8_PCIE_REFCLK_PAD_UNUSED) { @@ -
> > > 120,20
> > +117,44 @@
> > > static int imx8_pcie_phy_init(struct phy *phy)
> > >  		       imx8_phy->base +
> > > IMX8MM_PCIE_PHY_CMN_REG065);
> > >  	}
> > > 
> > > -	/* Tune PHY de-emphasis setting to pass PCIe compliance.
> > > */
> > > -	if (imx8_phy->tx_deemph_gen1)
> > > -		writel(imx8_phy->tx_deemph_gen1,
> > > -		       imx8_phy->base + PCIE_PHY_TRSV_REG5);
> > > -	if (imx8_phy->tx_deemph_gen2)
> > > -		writel(imx8_phy->tx_deemph_gen2,
> > > -		       imx8_phy->base + PCIE_PHY_TRSV_REG6);
> > > +	/* Set AUX_EN_OVERRIDE 1'b0, when the CLKREQ# isn't
> > > hooked */
> > > +	regmap_update_bits(imx8_phy->iomuxc_gpr, IOMUXC_GPR14,
> > > +			   IMX8MM_GPR_PCIE_AUX_EN_OVERRIDE,
> > > +			   imx8_phy->clkreq_unused ?
> > > +			   0 : IMX8MM_GPR_PCIE_AUX_EN_OVERRIDE);
> > > +	regmap_update_bits(imx8_phy->iomuxc_gpr, IOMUXC_GPR14,
> > > +			   IMX8MM_GPR_PCIE_AUX_EN,
> > > +			   IMX8MM_GPR_PCIE_AUX_EN);
> > > +	regmap_update_bits(imx8_phy->iomuxc_gpr, IOMUXC_GPR14,
> > > +			   IMX8MM_GPR_PCIE_POWER_OFF, 0);
> > > +	regmap_update_bits(imx8_phy->iomuxc_gpr, IOMUXC_GPR14,
> > > +			   IMX8MM_GPR_PCIE_SSC_EN, 0);
> > > +
> > > +	regmap_update_bits(imx8_phy->iomuxc_gpr, IOMUXC_GPR14,
> > > +			   IMX8MM_GPR_PCIE_REF_CLK_SEL,
> > > +			   pad_mode ==
> > > IMX8_PCIE_REFCLK_PAD_INPUT ?
> > > +			   IMX8MM_GPR_PCIE_REF_CLK_EXT :
> > > +			   IMX8MM_GPR_PCIE_REF_CLK_PLL);
> > > +	usleep_range(100, 200);
> > > +
> > > +	/* Do the PHY common block reset */
> > > +	regmap_update_bits(imx8_phy->iomuxc_gpr, IOMUXC_GPR14,
> > > +			   IMX8MM_GPR_PCIE_CMN_RST,
> > > +			   IMX8MM_GPR_PCIE_CMN_RST);
> > > 
> > > -	reset_control_deassert(imx8_phy->reset);
> > > +	switch (imx8_phy->variant) {
> > > +	case IMX8MP:
> > > +		reset_control_deassert(imx8_phy->perst);
> > > +		fallthrough;
> > > +	case IMX8MM:
> > > +		reset_control_deassert(imx8_phy->reset);
> > > +		usleep_range(200, 500);
> > > +		break;
> > > +	}
> > > 
> > >  	/* Polling to check the phy is ready or not. */
> > > -	ret = readl_poll_timeout(imx8_phy->base +
> > IMX8MM_PCIE_PHY_CMN_REG75,
> > > -				 val, val ==
> > > PCIE_PHY_CMN_REG75_PLL_DONE,
> > > -				 10, 20000);
> > > +	ret = readl_poll_timeout(imx8_phy->base +
> > IMX8MM_PCIE_PHY_CMN_REG075,
> > > +				 val, val == ANA_PLL_DONE, 10,
> > > 20000);
> > >  	return ret;
> > >  }
> > > 
> > > @@ -160,6 +181,13 @@ static const struct phy_ops
> > > imx8_pcie_phy_ops = {
> > >  	.owner		= THIS_MODULE,
> > >  };
> > > 
> > > +static const struct of_device_id imx8_pcie_phy_of_match[] = {
> > > +	{.compatible = "fsl,imx8mm-pcie-phy", .data = (void
> > > *)IMX8MM},
> > > +	{.compatible = "fsl,imx8mp-pcie-phy", .data = (void
> > > *)IMX8MP},
> > > +	{ },
> > > +};
> > > +MODULE_DEVICE_TABLE(of, imx8_pcie_phy_of_match);
> > > +
> > >  static int imx8_pcie_phy_probe(struct platform_device *pdev)  {
> > >  	struct phy_provider *phy_provider;
> > > @@ -172,6 +200,9 @@ static int imx8_pcie_phy_probe(struct
> > platform_device *pdev)
> > >  	if (!imx8_phy)
> > >  		return -ENOMEM;
> > > 
> > > +	imx8_phy->variant =
> > > +		(enum
> > > imx8_pcie_phy_type)of_device_get_match_data(dev);
> > > +
> > >  	/* get PHY refclk pad mode */
> > >  	of_property_read_u32(np, "fsl,refclk-pad-mode",
> > >  			     &imx8_phy->refclk_pad_mode);
> > > @@ -196,8 +227,16 @@ static int imx8_pcie_phy_probe(struct
> > platform_device *pdev)
> > >  	}
> > > 
> > >  	/* Grab GPR config register range */
> > > -	imx8_phy->iomuxc_gpr =
> > > -		 syscon_regmap_lookup_by_compatible("fsl,imx6q-
> > > iomuxc-gpr");
> > > +	switch (imx8_phy->variant) {
> > > +	case IMX8MM:
> > > +		imx8_phy->iomuxc_gpr =
> > > +
> > syscon_regmap_lookup_by_compatible("fsl,imx8mm-iomuxc-gpr");
> > > +		break;
> > > +	case IMX8MP:
> > > +		imx8_phy->iomuxc_gpr =
> > > +
> > syscon_regmap_lookup_by_compatible("fsl,imx8mp-iomuxc-gpr");
> > > +		break;
> > > +	}
> > 
> > Oh, I had a real phandle in DT in mind for this, but I see how this
> > would be
> > hard to introduce in a backward compatible manner for the 8MM.
> > At least this way it is fully contained in the driver and doesn't
> > leak into DT
> > compatibles.
> > 
> > Maybe we could make this a little nicer by just having an const
> > array of iomux
> > syscon compatibles indexed by imx8_phy->variant, to avoid the
> > switch and the
> > resulting code (almost-)duplication.
> > 
> Hi Lucas:
> Thanks for your comments.
> Do you mean a drvdata struct indexed by variant, and contains the
> const array
> of iomux syscon compatible like below?
> 
> +static const struct imx8_pcie_phy_drvdata drvdata[] = {
> +       [IMX8MM] = {
> +               .variant = IMX8MM,
> +               .gpr = "fsl,imx8mm-iomuxc-gpr",
> +       },
> +
> +       [IMX8MP] = {
> +               .variant = IMX8MP,
> +               .gpr = "fsl,imx8mp-iomuxc-gpr",
> +       },
> +};
> +
> 
> Then, we can get the drvdata, and find the according gpr syscon
> regmap below.
> 
> +       imx8_phy->drvdata = of_device_get_match_data(dev);
> ...
> +       imx8_phy->iomuxc_gpr =
> +                syscon_regmap_lookup_by_compatible(imx8_phy-
> >drvdata->gpr);
> 
I had a simple array of GPR compatible strings in mind, so we could
lookup the compatible from the variant. But I think putting it directly
in drvdata, like done in your suggestion above, looks even better.

> If yes, I would do the changes, and issue the v6 later.

Yep, please change as suggested above. Same comment applies to the next
patch "PCI: imx6: Add iMX8MP PCIe support".

Also in both patches the dot between i and MX in i.MX8MP is missing in
the patch description subject line.

Regards,
Lucas

RE: [PATCH v5 6/7] phy: freescale: imx8m-pcie: Add iMX8MP PCIe PHY support

[Hongxing Zhu]

> -----Original Message-----
> From: Lucas Stach <l.stach@pengutronix.de>
> Sent: 2022年8月31日 16:34
> To: Hongxing Zhu <hongxing.zhu@nxp.com>; p.zabel@pengutronix.de;
> bhelgaas@google.com; lorenzo.pieralisi@arm.com; robh@kernel.org;
> shawnguo@kernel.org; vkoul@kernel.org; alexander.stein@ew.tq-group.com;
> marex@denx.de; richard.leitner@linux.dev
> Cc: linux-phy@lists.infradead.org; devicetree@vger.kernel.org;
> linux-pci@vger.kernel.org; linux-arm-kernel@lists.infradead.org;
> linux-kernel@vger.kernel.org; kernel@pengutronix.de; dl-linux-imx
> <linux-imx@nxp.com>
> Subject: Re: [PATCH v5 6/7] phy: freescale: imx8m-pcie: Add iMX8MP PCIe PHY
> support
> 
> Am Mittwoch, dem 31.08.2022 um 06:16 +0000 schrieb Hongxing Zhu:
> > > -----Original Message-----
> > > From: Lucas Stach <l.stach@pengutronix.de>
> > > Sent: 2022年8月30日 21:07
> > > To: Hongxing Zhu <hongxing.zhu@nxp.com>; p.zabel@pengutronix.de;
> > > bhelgaas@google.com; lorenzo.pieralisi@arm.com; robh@kernel.org;
> > > shawnguo@kernel.org; vkoul@kernel.org;
> > > alexander.stein@ew.tq-group.com; marex@denx.de;
> > > richard.leitner@linux.dev
> > > Cc: linux-phy@lists.infradead.org; devicetree@vger.kernel.org;
> > > linux-pci@vger.kernel.org; linux-arm-kernel@lists.infradead.org;
> > > linux-kernel@vger.kernel.org; kernel@pengutronix.de; dl-linux-imx
> > > <linux-imx@nxp.com>
> > > Subject: Re: [PATCH v5 6/7] phy: freescale: imx8m-pcie: Add iMX8MP
> > > PCIe PHY support
> > >
> > > Am Dienstag, dem 30.08.2022 um 15:46 +0800 schrieb Richard Zhu:
> > > > Add i.MX8MP PCIe PHY support.
> > > >
> > > > Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com>
> > > > Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
> > > > Tested-by: Marek Vasut <marex@denx.de>
> > > > Tested-by: Richard Leitner <richard.leitner@skidata.com>
> > > > Tested-by: Alexander Stein <alexander.stein@ew.tq-group.com>
> > > > ---
> > > >  drivers/phy/freescale/phy-fsl-imx8m-pcie.c | 137
> > > > +++++++++++++--------
> > > >  1 file changed, 89 insertions(+), 48 deletions(-)
> > > >
> > > > diff --git a/drivers/phy/freescale/phy-fsl-imx8m-pcie.c
> > > > b/drivers/phy/freescale/phy-fsl-imx8m-pcie.c
> > > > index ad7d2edfc414..c76e3a1a5f51 100644
> > > > --- a/drivers/phy/freescale/phy-fsl-imx8m-pcie.c
> > > > +++ b/drivers/phy/freescale/phy-fsl-imx8m-pcie.c
> > > > @@ -11,6 +11,9 @@
> > > >  #include <linux/mfd/syscon.h>
> > > >  #include <linux/mfd/syscon/imx7-iomuxc-gpr.h>
> > > >  #include <linux/module.h>
> > > > +#include <linux/of_address.h>
> > > > +#include <linux/of_device.h>
> > > > +#include <linux/of_device.h>
> > > >  #include <linux/phy/phy.h>
> > > >  #include <linux/platform_device.h>
> > > >  #include <linux/regmap.h>
> > > > @@ -31,12 +34,10 @@
> > > >  #define IMX8MM_PCIE_PHY_CMN_REG065	0x194
> > > >  #define  ANA_AUX_RX_TERM		(BIT(7) | BIT(4))
> > > >  #define  ANA_AUX_TX_LVL			GENMASK(3, 0)
> > > > -#define IMX8MM_PCIE_PHY_CMN_REG75	0x1D4
> > > > -#define  PCIE_PHY_CMN_REG75_PLL_DONE	0x3
> > > > +#define IMX8MM_PCIE_PHY_CMN_REG075	0x1D4
> > > > +#define  ANA_PLL_DONE			0x3
> > > >  #define PCIE_PHY_TRSV_REG5		0x414
> > > > -#define  PCIE_PHY_TRSV_REG5_GEN1_DEEMP	0x2D
> > > >  #define PCIE_PHY_TRSV_REG6		0x418
> > > > -#define  PCIE_PHY_TRSV_REG6_GEN2_DEEMP	0xF
> > > >
> > > >  #define IMX8MM_GPR_PCIE_REF_CLK_SEL	GENMASK(25, 24)
> > > >  #define IMX8MM_GPR_PCIE_REF_CLK_PLL
> > > 	FIELD_PREP(IMX8MM_GPR_PCIE_REF_CLK_SEL, 0x3)
> > > > @@ -47,16 +48,23 @@
> > > >  #define IMX8MM_GPR_PCIE_SSC_EN		BIT(16)
> > > >  #define IMX8MM_GPR_PCIE_AUX_EN_OVERRIDE	BIT(9)
> > > >
> > > > +enum imx8_pcie_phy_type {
> > > > +	IMX8MM,
> > > > +	IMX8MP,
> > > > +};
> > > > +
> > > >  struct imx8_pcie_phy {
> > > >  	void __iomem		*base;
> > > >  	struct clk		*clk;
> > > >  	struct phy		*phy;
> > > >  	struct regmap		*iomuxc_gpr;
> > > >  	struct reset_control	*reset;
> > > > +	struct reset_control	*perst;
> > > >  	u32			refclk_pad_mode;
> > > >  	u32			tx_deemph_gen1;
> > > >  	u32			tx_deemph_gen2;
> > > >  	bool			clkreq_unused;
> > > > +	enum imx8_pcie_phy_type	variant;
> > > >  };
> > > >
> > > >  static int imx8_pcie_phy_init(struct phy *phy) @@ -68,31 +76,20
> > > > @@ static int imx8_pcie_phy_init(struct phy *phy)
> > > >  	reset_control_assert(imx8_phy->reset);
> > > >
> > > >  	pad_mode = imx8_phy->refclk_pad_mode;
> > > > -	/* Set AUX_EN_OVERRIDE 1'b0, when the CLKREQ# isn't
> > > > hooked */
> > > > -	regmap_update_bits(imx8_phy->iomuxc_gpr, IOMUXC_GPR14,
> > > > -			   IMX8MM_GPR_PCIE_AUX_EN_OVERRIDE,
> > > > -			   imx8_phy->clkreq_unused ?
> > > > -			   0 : IMX8MM_GPR_PCIE_AUX_EN_OVERRIDE);
> > > > -	regmap_update_bits(imx8_phy->iomuxc_gpr, IOMUXC_GPR14,
> > > > -			   IMX8MM_GPR_PCIE_AUX_EN,
> > > > -			   IMX8MM_GPR_PCIE_AUX_EN);
> > > > -	regmap_update_bits(imx8_phy->iomuxc_gpr, IOMUXC_GPR14,
> > > > -			   IMX8MM_GPR_PCIE_POWER_OFF, 0);
> > > > -	regmap_update_bits(imx8_phy->iomuxc_gpr, IOMUXC_GPR14,
> > > > -			   IMX8MM_GPR_PCIE_SSC_EN, 0);
> > > > -
> > > > -	regmap_update_bits(imx8_phy->iomuxc_gpr, IOMUXC_GPR14,
> > > > -			   IMX8MM_GPR_PCIE_REF_CLK_SEL,
> > > > -			   pad_mode ==
> > > > IMX8_PCIE_REFCLK_PAD_INPUT ?
> > > > -			   IMX8MM_GPR_PCIE_REF_CLK_EXT :
> > > > -			   IMX8MM_GPR_PCIE_REF_CLK_PLL);
> > > > -	usleep_range(100, 200);
> > > > -
> > > > -	/* Do the PHY common block reset */
> > > > -	regmap_update_bits(imx8_phy->iomuxc_gpr, IOMUXC_GPR14,
> > > > -			   IMX8MM_GPR_PCIE_CMN_RST,
> > > > -			   IMX8MM_GPR_PCIE_CMN_RST);
> > > > -	usleep_range(200, 500);
> > > > +	switch (imx8_phy->variant) {
> > > > +	case IMX8MM:
> > > > +		/* Tune PHY de-emphasis setting to pass PCIe
> > > > compliance. */
> > > > +		if (imx8_phy->tx_deemph_gen1)
> > > > +			writel(imx8_phy->tx_deemph_gen1,
> > > > +			       imx8_phy->base +
> > > > PCIE_PHY_TRSV_REG5);
> > > > +		if (imx8_phy->tx_deemph_gen2)
> > > > +			writel(imx8_phy->tx_deemph_gen2,
> > > > +			       imx8_phy->base +
> > > > PCIE_PHY_TRSV_REG6);
> > > > +		break;
> > > > +	case IMX8MP:
> > > > +		reset_control_assert(imx8_phy->perst);
> > > > +		break;
> > > > +	}
> > > >
> > > >  	if (pad_mode == IMX8_PCIE_REFCLK_PAD_INPUT ||
> > > >  	    pad_mode == IMX8_PCIE_REFCLK_PAD_UNUSED) { @@ -
> > > > 120,20
> > > +117,44 @@
> > > > static int imx8_pcie_phy_init(struct phy *phy)
> > > >  		       imx8_phy->base +
> > > > IMX8MM_PCIE_PHY_CMN_REG065);
> > > >  	}
> > > >
> > > > -	/* Tune PHY de-emphasis setting to pass PCIe compliance.
> > > > */
> > > > -	if (imx8_phy->tx_deemph_gen1)
> > > > -		writel(imx8_phy->tx_deemph_gen1,
> > > > -		       imx8_phy->base + PCIE_PHY_TRSV_REG5);
> > > > -	if (imx8_phy->tx_deemph_gen2)
> > > > -		writel(imx8_phy->tx_deemph_gen2,
> > > > -		       imx8_phy->base + PCIE_PHY_TRSV_REG6);
> > > > +	/* Set AUX_EN_OVERRIDE 1'b0, when the CLKREQ# isn't
> > > > hooked */
> > > > +	regmap_update_bits(imx8_phy->iomuxc_gpr, IOMUXC_GPR14,
> > > > +			   IMX8MM_GPR_PCIE_AUX_EN_OVERRIDE,
> > > > +			   imx8_phy->clkreq_unused ?
> > > > +			   0 : IMX8MM_GPR_PCIE_AUX_EN_OVERRIDE);
> > > > +	regmap_update_bits(imx8_phy->iomuxc_gpr, IOMUXC_GPR14,
> > > > +			   IMX8MM_GPR_PCIE_AUX_EN,
> > > > +			   IMX8MM_GPR_PCIE_AUX_EN);
> > > > +	regmap_update_bits(imx8_phy->iomuxc_gpr, IOMUXC_GPR14,
> > > > +			   IMX8MM_GPR_PCIE_POWER_OFF, 0);
> > > > +	regmap_update_bits(imx8_phy->iomuxc_gpr, IOMUXC_GPR14,
> > > > +			   IMX8MM_GPR_PCIE_SSC_EN, 0);
> > > > +
> > > > +	regmap_update_bits(imx8_phy->iomuxc_gpr, IOMUXC_GPR14,
> > > > +			   IMX8MM_GPR_PCIE_REF_CLK_SEL,
> > > > +			   pad_mode ==
> > > > IMX8_PCIE_REFCLK_PAD_INPUT ?
> > > > +			   IMX8MM_GPR_PCIE_REF_CLK_EXT :
> > > > +			   IMX8MM_GPR_PCIE_REF_CLK_PLL);
> > > > +	usleep_range(100, 200);
> > > > +
> > > > +	/* Do the PHY common block reset */
> > > > +	regmap_update_bits(imx8_phy->iomuxc_gpr, IOMUXC_GPR14,
> > > > +			   IMX8MM_GPR_PCIE_CMN_RST,
> > > > +			   IMX8MM_GPR_PCIE_CMN_RST);
> > > >
> > > > -	reset_control_deassert(imx8_phy->reset);
> > > > +	switch (imx8_phy->variant) {
> > > > +	case IMX8MP:
> > > > +		reset_control_deassert(imx8_phy->perst);
> > > > +		fallthrough;
> > > > +	case IMX8MM:
> > > > +		reset_control_deassert(imx8_phy->reset);
> > > > +		usleep_range(200, 500);
> > > > +		break;
> > > > +	}
> > > >
> > > >  	/* Polling to check the phy is ready or not. */
> > > > -	ret = readl_poll_timeout(imx8_phy->base +
> > > IMX8MM_PCIE_PHY_CMN_REG75,
> > > > -				 val, val ==
> > > > PCIE_PHY_CMN_REG75_PLL_DONE,
> > > > -				 10, 20000);
> > > > +	ret = readl_poll_timeout(imx8_phy->base +
> > > IMX8MM_PCIE_PHY_CMN_REG075,
> > > > +				 val, val == ANA_PLL_DONE, 10,
> > > > 20000);
> > > >  	return ret;
> > > >  }
> > > >
> > > > @@ -160,6 +181,13 @@ static const struct phy_ops imx8_pcie_phy_ops
> > > > = {
> > > >  	.owner		= THIS_MODULE,
> > > >  };
> > > >
> > > > +static const struct of_device_id imx8_pcie_phy_of_match[] = {
> > > > +	{.compatible = "fsl,imx8mm-pcie-phy", .data = (void
> > > > *)IMX8MM},
> > > > +	{.compatible = "fsl,imx8mp-pcie-phy", .data = (void
> > > > *)IMX8MP},
> > > > +	{ },
> > > > +};
> > > > +MODULE_DEVICE_TABLE(of, imx8_pcie_phy_of_match);
> > > > +
> > > >  static int imx8_pcie_phy_probe(struct platform_device *pdev)  {
> > > >  	struct phy_provider *phy_provider; @@ -172,6 +200,9 @@ static
> > > > int imx8_pcie_phy_probe(struct
> > > platform_device *pdev)
> > > >  	if (!imx8_phy)
> > > >  		return -ENOMEM;
> > > >
> > > > +	imx8_phy->variant =
> > > > +		(enum
> > > > imx8_pcie_phy_type)of_device_get_match_data(dev);
> > > > +
> > > >  	/* get PHY refclk pad mode */
> > > >  	of_property_read_u32(np, "fsl,refclk-pad-mode",
> > > >  			     &imx8_phy->refclk_pad_mode); @@ -196,8 +227,16
> @@ static
> > > > int imx8_pcie_phy_probe(struct
> > > platform_device *pdev)
> > > >  	}
> > > >
> > > >  	/* Grab GPR config register range */
> > > > -	imx8_phy->iomuxc_gpr =
> > > > -		 syscon_regmap_lookup_by_compatible("fsl,imx6q-
> > > > iomuxc-gpr");
> > > > +	switch (imx8_phy->variant) {
> > > > +	case IMX8MM:
> > > > +		imx8_phy->iomuxc_gpr =
> > > > +
> > > syscon_regmap_lookup_by_compatible("fsl,imx8mm-iomuxc-gpr");
> > > > +		break;
> > > > +	case IMX8MP:
> > > > +		imx8_phy->iomuxc_gpr =
> > > > +
> > > syscon_regmap_lookup_by_compatible("fsl,imx8mp-iomuxc-gpr");
> > > > +		break;
> > > > +	}
> > >
> > > Oh, I had a real phandle in DT in mind for this, but I see how this
> > > would be hard to introduce in a backward compatible manner for the
> > > 8MM.
> > > At least this way it is fully contained in the driver and doesn't
> > > leak into DT compatibles.
> > >
> > > Maybe we could make this a little nicer by just having an const
> > > array of iomux syscon compatibles indexed by imx8_phy->variant, to
> > > avoid the switch and the resulting code (almost-)duplication.
> > >
> > Hi Lucas:
> > Thanks for your comments.
> > Do you mean a drvdata struct indexed by variant, and contains the
> > const array of iomux syscon compatible like below?
> >
> > +static const struct imx8_pcie_phy_drvdata drvdata[] = {
> > +       [IMX8MM] = {
> > +               .variant = IMX8MM,
> > +               .gpr = "fsl,imx8mm-iomuxc-gpr",
> > +       },
> > +
> > +       [IMX8MP] = {
> > +               .variant = IMX8MP,
> > +               .gpr = "fsl,imx8mp-iomuxc-gpr",
> > +       },
> > +};
> > +
> >
> > Then, we can get the drvdata, and find the according gpr syscon regmap
> > below.
> >
> > +       imx8_phy->drvdata = of_device_get_match_data(dev);
> > ...
> > +       imx8_phy->iomuxc_gpr =
> > +                syscon_regmap_lookup_by_compatible(imx8_phy-
> > >drvdata->gpr);
> >
> I had a simple array of GPR compatible strings in mind, so we could lookup the
> compatible from the variant. But I think putting it directly in drvdata, like done
> in your suggestion above, looks even better.
> 
> > If yes, I would do the changes, and issue the v6 later.
> 
> Yep, please change as suggested above. Same comment applies to the next
> patch "PCI: imx6: Add iMX8MP PCIe support".
> 
> Also in both patches the dot between i and MX in i.MX8MP is missing in the
> patch description subject line.

Okay, thanks.

Best Regards
Richard Zhu
> 
> Regards,
> Lucas

[PATCH v5 7/7] PCI: imx6: Add iMX8MP PCIe support

[Richard Zhu]

Add i.MX8MP PCIe support.

Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com>
Tested-by: Marek Vasut <marex@denx.de>
Tested-by: Richard Leitner <richard.leitner@skidata.com>
Tested-by: Alexander Stein <alexander.stein@ew.tq-group.com>
---
 drivers/pci/controller/dwc/pci-imx6.c | 29 ++++++++++++++++++++++++---
 1 file changed, 26 insertions(+), 3 deletions(-)

diff --git a/drivers/pci/controller/dwc/pci-imx6.c b/drivers/pci/controller/dwc/pci-imx6.c
index 6e5debdbc55b..0488ce752f34 100644
--- a/drivers/pci/controller/dwc/pci-imx6.c
+++ b/drivers/pci/controller/dwc/pci-imx6.c
@@ -51,6 +51,7 @@ enum imx6_pcie_variants {
 	IMX7D,
 	IMX8MQ,
 	IMX8MM,
+	IMX8MP,
 };
 
 #define IMX6_PCIE_FLAG_IMX6_PHY			BIT(0)
@@ -150,7 +151,8 @@ struct imx6_pcie {
 static unsigned int imx6_pcie_grp_offset(const struct imx6_pcie *imx6_pcie)
 {
 	WARN_ON(imx6_pcie->drvdata->variant != IMX8MQ &&
-		imx6_pcie->drvdata->variant != IMX8MM);
+		imx6_pcie->drvdata->variant != IMX8MM &&
+		imx6_pcie->drvdata->variant != IMX8MP);
 	return imx6_pcie->controller_id == 1 ? IOMUXC_GPR16 : IOMUXC_GPR14;
 }
 
@@ -301,6 +303,7 @@ static void imx6_pcie_init_phy(struct imx6_pcie *imx6_pcie)
 {
 	switch (imx6_pcie->drvdata->variant) {
 	case IMX8MM:
+	case IMX8MP:
 		/*
 		 * The PHY initialization had been done in the PHY
 		 * driver, break here directly.
@@ -558,6 +561,7 @@ static int imx6_pcie_enable_ref_clk(struct imx6_pcie *imx6_pcie)
 		break;
 	case IMX8MM:
 	case IMX8MQ:
+	case IMX8MP:
 		ret = clk_prepare_enable(imx6_pcie->pcie_aux);
 		if (ret) {
 			dev_err(dev, "unable to enable pcie_aux clock\n");
@@ -602,6 +606,7 @@ static void imx6_pcie_disable_ref_clk(struct imx6_pcie *imx6_pcie)
 		break;
 	case IMX8MM:
 	case IMX8MQ:
+	case IMX8MP:
 		clk_disable_unprepare(imx6_pcie->pcie_aux);
 		break;
 	default:
@@ -669,6 +674,7 @@ static void imx6_pcie_assert_core_reset(struct imx6_pcie *imx6_pcie)
 		reset_control_assert(imx6_pcie->pciephy_reset);
 		fallthrough;
 	case IMX8MM:
+	case IMX8MP:
 		reset_control_assert(imx6_pcie->apps_reset);
 		break;
 	case IMX6SX:
@@ -744,6 +750,7 @@ static int imx6_pcie_deassert_core_reset(struct imx6_pcie *imx6_pcie)
 		break;
 	case IMX6Q:		/* Nothing to do */
 	case IMX8MM:
+	case IMX8MP:
 		break;
 	}
 
@@ -793,6 +800,7 @@ static void imx6_pcie_ltssm_enable(struct device *dev)
 	case IMX7D:
 	case IMX8MQ:
 	case IMX8MM:
+	case IMX8MP:
 		reset_control_deassert(imx6_pcie->apps_reset);
 		break;
 	}
@@ -812,6 +820,7 @@ static void imx6_pcie_ltssm_disable(struct device *dev)
 	case IMX7D:
 	case IMX8MQ:
 	case IMX8MM:
+	case IMX8MP:
 		reset_control_assert(imx6_pcie->apps_reset);
 		break;
 	}
@@ -1179,6 +1188,7 @@ static int imx6_pcie_probe(struct platform_device *pdev)
 		}
 		break;
 	case IMX8MM:
+	case IMX8MP:
 		imx6_pcie->pcie_aux = devm_clk_get(dev, "pcie_aux");
 		if (IS_ERR(imx6_pcie->pcie_aux))
 			return dev_err_probe(dev, PTR_ERR(imx6_pcie->pcie_aux),
@@ -1215,8 +1225,16 @@ static int imx6_pcie_probe(struct platform_device *pdev)
 	}
 
 	/* Grab GPR config register range */
-	imx6_pcie->iomuxc_gpr =
-		 syscon_regmap_lookup_by_compatible("fsl,imx6q-iomuxc-gpr");
+	switch (imx6_pcie->drvdata->variant) {
+	case IMX8MP:
+		imx6_pcie->iomuxc_gpr =
+			 syscon_regmap_lookup_by_compatible("fsl,imx8mp-iomuxc-gpr");
+		break;
+	default:
+		imx6_pcie->iomuxc_gpr =
+			 syscon_regmap_lookup_by_compatible("fsl,imx6q-iomuxc-gpr");
+		break;
+	}
 	if (IS_ERR(imx6_pcie->iomuxc_gpr)) {
 		dev_err(dev, "unable to find iomuxc registers\n");
 		return PTR_ERR(imx6_pcie->iomuxc_gpr);
@@ -1320,6 +1338,10 @@ static const struct imx6_pcie_drvdata drvdata[] = {
 		.variant = IMX8MM,
 		.flags = IMX6_PCIE_FLAG_SUPPORTS_SUSPEND,
 	},
+	[IMX8MP] = {
+		.variant = IMX8MP,
+		.flags = IMX6_PCIE_FLAG_SUPPORTS_SUSPEND,
+	},
 };
 
 static const struct of_device_id imx6_pcie_of_match[] = {
@@ -1329,6 +1351,7 @@ static const struct of_device_id imx6_pcie_of_match[] = {
 	{ .compatible = "fsl,imx7d-pcie",  .data = &drvdata[IMX7D],  },
 	{ .compatible = "fsl,imx8mq-pcie", .data = &drvdata[IMX8MQ], },
 	{ .compatible = "fsl,imx8mm-pcie", .data = &drvdata[IMX8MM], },
+	{ .compatible = "fsl,imx8mp-pcie", .data = &drvdata[IMX8MP], },
 	{},
 };
 
-- 
2.25.1