* [PATCH 2/2] arm64: tegra: Add thermal support for Tegra234
2023-01-24 11:51 [PATCH 1/2] dt-bindings: thermal: Add Tegra234 BPMP thermal zones Jon Hunter
@ 2023-01-24 11:51 ` Jon Hunter
2023-01-25 11:05 ` Jon Hunter
2023-01-25 20:26 ` [PATCH 1/2] dt-bindings: thermal: Add Tegra234 BPMP thermal zones Rob Herring
1 sibling, 1 reply; 5+ messages in thread
From: Jon Hunter @ 2023-01-24 11:51 UTC (permalink / raw)
To: Rafael J . Wysocki, Daniel Lezcano, Rob Herring,
Krzysztof Kozlowski, Thierry Reding
Cc: linux-pm, devicetree, linux-tegra, Yi-Wei Wang, Jon Hunter
From: Yi-Wei Wang <yiweiw@nvidia.com>
Add the BPMP thermal device node and thermal-zones for Tegra234 and
enable thermal support for the Tegra234 Jetson AGX Orin board.
Signed-off-by: Yi-Wei Wang <yiweiw@nvidia.com>
Signed-off-by: Jon Hunter <jonathanh@nvidia.com>
---
.../boot/dts/nvidia/tegra234-p3701-0000.dtsi | 276 ++++++++++++++++++
.../nvidia/tegra234-p3737-0000+p3701-0000.dts | 32 ++
arch/arm64/boot/dts/nvidia/tegra234.dtsi | 59 ++++
3 files changed, 367 insertions(+)
diff --git a/arch/arm64/boot/dts/nvidia/tegra234-p3701-0000.dtsi b/arch/arm64/boot/dts/nvidia/tegra234-p3701-0000.dtsi
index 2378da324273..7f798742df43 100644
--- a/arch/arm64/boot/dts/nvidia/tegra234-p3701-0000.dtsi
+++ b/arch/arm64/boot/dts/nvidia/tegra234-p3701-0000.dtsi
@@ -80,6 +80,22 @@ pmc@c360000 {
};
};
+ bpmp {
+ i2c {
+ tegra_tmp451: thermal-sensor@4c {
+ compatible = "ti,tmp451";
+ reg = <0x4c>;
+ vcc-supply = <&vdd_1v8_ao>;
+ #thermal-sensor-cells = <1>;
+ status = "okay";
+ };
+ };
+
+ thermal {
+ status = "okay";
+ };
+ };
+
vdd_5v0_sys: regulator-vdd-5v0-sys {
compatible = "regulator-fixed";
regulator-name = "VIN_SYS_5V0";
@@ -139,4 +155,264 @@ vdd_12v_pcie: regulator-vdd-12v-pcie {
gpio = <&gpio TEGRA234_MAIN_GPIO(A, 1) GPIO_ACTIVE_LOW>;
regulator-boot-on;
};
+
+ thermal-zones {
+ cpu-thermal {
+ polling-delay = <1000>;
+ polling-delay-passive = <1000>;
+ thermal-sensors = <&{/bpmp/thermal} TEGRA234_THERMAL_ZONE_CPU>;
+ status = "okay";
+
+ trips {
+ cpu_sw_shutdown: cpu-sw-shutdown {
+ temperature = <104500>;
+ hysteresis = <0>;
+ type = "critical";
+ };
+
+ cpu_sw_throttle: cpu-sw-throttle {
+ temperature = <99000>;
+ hysteresis = <0>;
+ type = "passive";
+ };
+ };
+
+ cooling-maps {
+ map0 {
+ trip = <&cpu_sw_throttle>;
+ cooling-device = <&cpu0_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&cpu1_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&cpu2_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+ };
+ };
+ };
+
+ gpu-thermal {
+ polling-delay = <1000>;
+ polling-delay-passive = <1000>;
+ thermal-sensors = <&{/bpmp/thermal} TEGRA234_THERMAL_ZONE_GPU>;
+ status = "okay";
+ status = "disabled";
+
+ trips {
+ gpu_sw_shutdown: gpu-sw-shutdown {
+ temperature = <104500>;
+ hysteresis = <0>;
+ type = "critical";
+ };
+
+ gpu_sw_throttle: gpu-sw-throttle {
+ temperature = <99000>;
+ hysteresis = <0>;
+ type = "passive";
+ };
+ };
+
+ cooling-maps {
+ map0 {
+ trip = <&gpu_sw_throttle>;
+ cooling-device = <&cpu0_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&cpu1_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&cpu2_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+ };
+ };
+ };
+
+ cv0-thermal {
+ polling-delay = <1000>;
+ polling-delay-passive = <1000>;
+ thermal-sensors = <&{/bpmp/thermal} TEGRA234_THERMAL_ZONE_CV0>;
+ status = "okay";
+
+ trips {
+ cv0_sw_shutdown: cv0-sw-shutdown {
+ temperature = <104500>;
+ hysteresis = <0>;
+ type = "critical";
+ };
+
+ cv0_sw_throttle: cv0-sw-throttle {
+ temperature = <99000>;
+ hysteresis = <0>;
+ type = "passive";
+ };
+ };
+
+ cooling-maps {
+ map0 {
+ trip = <&cv0_sw_throttle>;
+ cooling-device = <&cpu0_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&cpu1_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&cpu2_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+ };
+ };
+ };
+
+
+ cv1-thermal {
+ polling-delay = <1000>;
+ polling-delay-passive = <1000>;
+ thermal-sensors = <&{/bpmp/thermal} TEGRA234_THERMAL_ZONE_CV1>;
+ status = "okay";
+ status = "disabled";
+
+ trips {
+ cv1_sw_shutdown: cv1-sw-shutdown {
+ temperature = <104500>;
+ hysteresis = <0>;
+ type = "critical";
+ };
+
+ cv1_sw_throttle: cv1-sw-throttle {
+ temperature = <99000>;
+ hysteresis = <0>;
+ type = "passive";
+ };
+ };
+
+ cooling-maps {
+ map0 {
+ trip = <&cv1_sw_throttle>;
+ cooling-device = <&cpu0_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&cpu1_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&cpu2_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+ };
+ };
+ };
+
+ cv2-thermal {
+ polling-delay = <1000>;
+ polling-delay-passive = <1000>;
+ thermal-sensors = <&{/bpmp/thermal} TEGRA234_THERMAL_ZONE_CV2>;
+ status = "okay";
+
+ trips {
+ cv2_sw_shutdown: cv2-sw-shutdown {
+ temperature = <104500>;
+ hysteresis = <0>;
+ type = "critical";
+ };
+
+ cv2_sw_throttle: cv2-sw-throttle {
+ temperature = <99000>;
+ hysteresis = <0>;
+ type = "passive";
+ };
+ };
+
+ cooling-maps {
+ map0 {
+ trip = <&cv2_sw_throttle>;
+ cooling-device = <&cpu0_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&cpu1_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&cpu2_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+ };
+ };
+ };
+
+ soc0-thermal {
+ polling-delay = <1000>;
+ polling-delay-passive = <1000>;
+ thermal-sensors = <&{/bpmp/thermal} TEGRA234_THERMAL_ZONE_SOC0>;
+ status = "okay";
+
+ trips {
+ soc0_sw_shutdown: soc0-sw-shutdown {
+ temperature = <104500>;
+ hysteresis = <0>;
+ type = "critical";
+ };
+
+ soc0_sw_throttle: soc0-sw-throttle {
+ temperature = <99000>;
+ hysteresis = <0>;
+ type = "passive";
+ };
+ };
+
+ cooling-maps {
+ map0 {
+ trip = <&soc0_sw_throttle>;
+ cooling-device = <&cpu0_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&cpu1_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&cpu2_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+ };
+ };
+ };
+
+ soc1-thermal {
+ polling-delay = <1000>;
+ polling-delay-passive = <1000>;
+ thermal-sensors = <&{/bpmp/thermal} TEGRA234_THERMAL_ZONE_SOC1>;
+ status = "okay";
+
+ trips {
+ soc1_sw_shutdown: soc1-sw-shutdown {
+ temperature = <104500>;
+ hysteresis = <0>;
+ type = "critical";
+ };
+
+ soc1_sw_throttle: soc1-sw-throttle {
+ temperature = <99000>;
+ hysteresis = <0>;
+ type = "passive";
+ };
+ };
+
+ cooling-maps {
+ map0 {
+ trip = <&soc1_sw_throttle>;
+ cooling-device = <&cpu0_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&cpu1_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&cpu2_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+ };
+ };
+ };
+
+ soc2-thermal {
+ polling-delay = <1000>;
+ polling-delay-passive = <1000>;
+ thermal-sensors = <&{/bpmp/thermal} TEGRA234_THERMAL_ZONE_SOC2>;
+ status = "okay";
+
+ trips {
+ soc2_sw_shutdown: soc2-sw-shutdown {
+ temperature = <104500>;
+ hysteresis = <0>;
+ type = "critical";
+ };
+
+ soc2_sw_throttle: soc2-sw-throttle {
+ temperature = <99000>;
+ hysteresis = <0>;
+ type = "passive";
+ };
+ };
+
+ cooling-maps {
+ map0 {
+ trip = <&soc2_sw_throttle>;
+ cooling-device = <&cpu0_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&cpu1_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&cpu2_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+ };
+ };
+ };
+
+ tj-thermal {
+ polling-delay = <1000>;
+ polling-delay-passive = <1000>;
+ thermal-sensors = <&{/bpmp/thermal} TEGRA234_THERMAL_ZONE_TJ_MAX>;
+ status = "okay";
+
+ trips {
+ tj_sw_shutdown: tj-sw-shutdown {
+ temperature = <104500>;
+ hysteresis = <0>;
+ type = "critical";
+ };
+ };
+ };
+ };
};
diff --git a/arch/arm64/boot/dts/nvidia/tegra234-p3737-0000+p3701-0000.dts b/arch/arm64/boot/dts/nvidia/tegra234-p3737-0000+p3701-0000.dts
index bfd935a86d19..b9c03a87fa5c 100644
--- a/arch/arm64/boot/dts/nvidia/tegra234-p3737-0000+p3701-0000.dts
+++ b/arch/arm64/boot/dts/nvidia/tegra234-p3737-0000+p3701-0000.dts
@@ -2377,4 +2377,36 @@ sound {
label = "NVIDIA Jetson AGX Orin APE";
};
+
+ thermal-zones {
+ tboard-thermal {
+ polling-delay = <1000>;
+ polling-delay-passive = <1000>;
+ thermal-sensors = <&tegra_tmp451 0>;
+ status = "okay";
+
+ trips {
+ tboard_sw_shutdown: tboard-sw-shutdown {
+ temperature = <107000>;
+ hysteresis = <0>;
+ type = "critical";
+ };
+ };
+ };
+
+ tdiode-thermal {
+ polling-delay = <1000>;
+ polling-delay-passive = <1000>;
+ thermal-sensors = <&tegra_tmp451 1>;
+ status = "okay";
+
+ trips {
+ tdiode_sw_shutdown: tdiode-sw-shutdown {
+ temperature = <107000>;
+ hysteresis = <0>;
+ type = "critical";
+ };
+ };
+ };
+ };
};
diff --git a/arch/arm64/boot/dts/nvidia/tegra234.dtsi b/arch/arm64/boot/dts/nvidia/tegra234.dtsi
index 7b7a57c90e3d..b92427e397af 100644
--- a/arch/arm64/boot/dts/nvidia/tegra234.dtsi
+++ b/arch/arm64/boot/dts/nvidia/tegra234.dtsi
@@ -8,6 +8,8 @@
#include <dt-bindings/pinctrl/pinctrl-tegra-io-pad.h>
#include <dt-bindings/power/tegra234-powergate.h>
#include <dt-bindings/reset/tegra234-reset.h>
+#include <dt-bindings/thermal/tegra234-bpmp-thermal.h>
+#include <dt-bindings/thermal/thermal.h>
/ {
compatible = "nvidia,tegra234";
@@ -3135,6 +3137,12 @@ bpmp_i2c: i2c {
#address-cells = <1>;
#size-cells = <0>;
};
+
+ thermal {
+ compatible = "nvidia,tegra186-bpmp-thermal";
+ #thermal-sensor-cells = <1>;
+ status = "disabled";
+ };
};
cpus {
@@ -3155,6 +3163,7 @@ cpu0_0: cpu@0 {
d-cache-line-size = <64>;
d-cache-sets = <256>;
next-level-cache = <&l2c0_0>;
+ #cooling-cells = <2>;
};
cpu0_1: cpu@100 {
@@ -3219,6 +3228,7 @@ cpu1_0: cpu@10000 {
d-cache-line-size = <64>;
d-cache-sets = <256>;
next-level-cache = <&l2c1_0>;
+ #cooling-cells = <2>;
};
cpu1_1: cpu@10100 {
@@ -3283,6 +3293,7 @@ cpu2_0: cpu@20000 {
d-cache-line-size = <64>;
d-cache-sets = <256>;
next-level-cache = <&l2c2_0>;
+ #cooling-cells = <2>;
};
cpu2_1: cpu@20100 {
@@ -3580,4 +3591,52 @@ timer {
interrupt-parent = <&gic>;
always-on;
};
+
+ thermal-zones {
+ cpu-thermal {
+ thermal-sensors = <&{/bpmp/thermal} TEGRA234_THERMAL_ZONE_CPU>;
+ status = "disabled";
+ };
+
+ gpu-thermal {
+ thermal-sensors = <&{/bpmp/thermal} TEGRA234_THERMAL_ZONE_GPU>;
+ status = "disabled";
+ };
+
+ cv0-thermal {
+ thermal-sensors = <&{/bpmp/thermal} TEGRA234_THERMAL_ZONE_CV0>;
+ status = "disabled";
+ };
+
+
+ cv1-thermal {
+ thermal-sensors = <&{/bpmp/thermal} TEGRA234_THERMAL_ZONE_CV1>;
+ status = "disabled";
+ };
+
+ cv2-thermal {
+ thermal-sensors = <&{/bpmp/thermal} TEGRA234_THERMAL_ZONE_CV2>;
+ status = "disabled";
+ };
+
+ soc0-thermal {
+ thermal-sensors = <&{/bpmp/thermal} TEGRA234_THERMAL_ZONE_SOC0>;
+ status = "disabled";
+ };
+
+ soc1-thermal {
+ thermal-sensors = <&{/bpmp/thermal} TEGRA234_THERMAL_ZONE_SOC1>;
+ status = "disabled";
+ };
+
+ soc2-thermal {
+ thermal-sensors = <&{/bpmp/thermal} TEGRA234_THERMAL_ZONE_SOC2>;
+ status = "disabled";
+ };
+
+ tj-thermal {
+ thermal-sensors = <&{/bpmp/thermal} TEGRA234_THERMAL_ZONE_TJ_MAX>;
+ status = "disabled";
+ };
+ };
};
--
2.25.1
^ permalink raw reply related [flat|nested] 5+ messages in thread* Re: [PATCH 1/2] dt-bindings: thermal: Add Tegra234 BPMP thermal zones
2023-01-24 11:51 [PATCH 1/2] dt-bindings: thermal: Add Tegra234 BPMP thermal zones Jon Hunter
2023-01-24 11:51 ` [PATCH 2/2] arm64: tegra: Add thermal support for Tegra234 Jon Hunter
@ 2023-01-25 20:26 ` Rob Herring
2023-01-25 21:18 ` Jon Hunter
1 sibling, 1 reply; 5+ messages in thread
From: Rob Herring @ 2023-01-25 20:26 UTC (permalink / raw)
To: Jon Hunter
Cc: Rafael J . Wysocki, Daniel Lezcano, Krzysztof Kozlowski,
Thierry Reding, linux-pm, devicetree, linux-tegra, Yi-Wei Wang
On Tue, Jan 24, 2023 at 11:51:18AM +0000, Jon Hunter wrote:
> From: Yi-Wei Wang <yiweiw@nvidia.com>
>
> Add BPMP thermal zone definitions for Tegra234.
>
> Signed-off-by: Yi-Wei Wang <yiweiw@nvidia.com>
> Signed-off-by: Jon Hunter <jonathanh@nvidia.com>
> ---
> .../thermal/tegra234-bpmp-thermal.h | 19 +++++++++++++++++++
Match the compatible name please.
> 1 file changed, 19 insertions(+)
> create mode 100644 include/dt-bindings/thermal/tegra234-bpmp-thermal.h
>
> diff --git a/include/dt-bindings/thermal/tegra234-bpmp-thermal.h b/include/dt-bindings/thermal/tegra234-bpmp-thermal.h
> new file mode 100644
> index 000000000000..41a5efebcc7a
> --- /dev/null
> +++ b/include/dt-bindings/thermal/tegra234-bpmp-thermal.h
> @@ -0,0 +1,19 @@
License? Dual please.
> +/*
> + * This header provides constants for binding nvidia,tegra234-bpmp-thermal.
> + */
> +
> +#ifndef _DT_BINDINGS_THERMAL_TEGRA234_BPMP_THERMAL_H
> +#define _DT_BINDINGS_THERMAL_TEGRA234_BPMP_THERMAL_H
> +
> +#define TEGRA234_THERMAL_ZONE_CPU 0
> +#define TEGRA234_THERMAL_ZONE_GPU 1
> +#define TEGRA234_THERMAL_ZONE_CV0 2
> +#define TEGRA234_THERMAL_ZONE_CV1 3
> +#define TEGRA234_THERMAL_ZONE_CV2 4
> +#define TEGRA234_THERMAL_ZONE_SOC0 5
> +#define TEGRA234_THERMAL_ZONE_SOC1 6
> +#define TEGRA234_THERMAL_ZONE_SOC2 7
> +#define TEGRA234_THERMAL_ZONE_TJ_MAX 8
> +#define TEGRA234_THERMAL_ZONE_COUNT 9
> +
> +#endif
> --
> 2.25.1
>
^ permalink raw reply [flat|nested] 5+ messages in thread