From: Krzysztof Kozlowski <krzk@kernel.org>
To: Changhuang Liang <changhuang.liang@starfivetech.com>
Cc: Michael Turquette <mturquette@baylibre.com>,
Rob Herring <robh@kernel.org>,
Krzysztof Kozlowski <krzk+dt@kernel.org>,
Conor Dooley <conor+dt@kernel.org>,
Stephen Boyd <sboyd@kernel.org>, Paul Walmsley <pjw@kernel.org>,
Palmer Dabbelt <palmer@dabbelt.com>,
Albert Ou <aou@eecs.berkeley.edu>,
Alexandre Ghiti <alex@ghiti.fr>,
Philipp Zabel <p.zabel@pengutronix.de>,
Emil Renner Berthing <kernel@esmil.dk>,
Chen Wang <unicorn_wang@outlook.com>,
Inochi Amaoto <inochiama@gmail.com>,
Alexey Charkov <alchark@gmail.com>,
Thomas Bogendoerfer <tsbogend@alpha.franken.de>,
Keguang Zhang <keguang.zhang@gmail.com>,
"linux-clk@vger.kernel.org" <linux-clk@vger.kernel.org>,
"linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>,
"devicetree@vger.kernel.org" <devicetree@vger.kernel.org>,
"linux-riscv@lists.infradead.org"
<linux-riscv@lists.infradead.org>,
Leyfoon Tan <leyfoon.tan@starfivetech.com>
Subject: Re: [PATCH v1 02/13] dt-bindings: clock: Add system-0 domain PLL clock
Date: Tue, 7 Apr 2026 09:02:28 +0200 [thread overview]
Message-ID: <5f2a1946-9ca7-414c-a764-60f46f3b3cf5@kernel.org> (raw)
In-Reply-To: <ZQ4PR01MB120275BC5277C4FF18A738E6F25A2@ZQ4PR01MB1202.CHNPR01.prod.partner.outlook.cn>
On 07/04/2026 08:56, Changhuang Liang wrote:
> Hi, Krzysztof
>
> Thanks for the review.
>
>> On Thu, Apr 02, 2026 at 10:49:34PM -0700, Changhuang Liang wrote:
>>> Add system-0 domain PLL clock for StarFive JHB100 SoC.
>>>
>>> Signed-off-by: Changhuang Liang <changhuang.liang@starfivetech.com>
>>> ---
>>> .../bindings/clock/starfive,jhb100-pll.yaml | 44 +++++++++++++++++++
>>> .../dt-bindings/clock/starfive,jhb100-crg.h | 6 +++
>>
>> You did not test your code. Apply patch #1 and test it. Do you see build-level
>> errors?
>
> I'm very sorry about this. I will reorganize my patch to avoid the related errors.
>
Anyway this one should be folded into the parent. You have one generic,
system-wide clock as input, so as well this can be the resource of the
parent. And no address spaces.
Other examples have one-register address spaces, so these are not really
separate devices.
Best regards,
Krzysztof
next prev parent reply other threads:[~2026-04-07 7:02 UTC|newest]
Thread overview: 26+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-04-03 5:49 [PATCH v1 00/13] Add StarFive JHB100 syscon modules Changhuang Liang
2026-04-03 5:49 ` [PATCH v1 01/13] dt-bindings: soc: starfive: " Changhuang Liang
2026-04-05 7:17 ` Krzysztof Kozlowski
2026-04-07 7:34 ` Changhuang Liang
2026-04-07 7:37 ` Krzysztof Kozlowski
2026-04-03 5:49 ` [PATCH v1 02/13] dt-bindings: clock: Add system-0 domain PLL clock Changhuang Liang
2026-04-05 7:18 ` Krzysztof Kozlowski
2026-04-07 6:56 ` Changhuang Liang
2026-04-07 7:02 ` Krzysztof Kozlowski [this message]
2026-04-03 5:49 ` [PATCH v1 03/13] clk: starfive: Add system-0 domain PLL clock driver Changhuang Liang
2026-04-03 16:10 ` Brian Masney
2026-04-07 1:17 ` Changhuang Liang
2026-04-03 5:49 ` [PATCH v1 04/13] dt-bindings: clock: Add peripheral-0 domain PLL clock Changhuang Liang
2026-04-03 5:49 ` [PATCH v1 05/13] clk: starfive: Add peripheral-0 domain PLL clock driver Changhuang Liang
2026-04-03 5:49 ` [PATCH v1 06/13] dt-bindings: clock: Add peripheral-1 domain PLL clock Changhuang Liang
2026-04-03 5:49 ` [PATCH v1 07/13] clk: starfive: Add Peripheral-1 domain PLL clock driver Changhuang Liang
2026-04-03 5:49 ` [PATCH v1 08/13] dt-bindings: reset: Add StarFive JHB100 reset generator Changhuang Liang
2026-04-03 5:49 ` [PATCH v1 09/13] reset: starfive: Introduce assert_polarity Changhuang Liang
2026-04-03 5:49 ` [PATCH v1 10/13] reset: starfive: Add syscon reset driver support Changhuang Liang
2026-04-03 5:49 ` [PATCH v1 11/13] dt-bindings: hwinfo: Add starfive,jhb100-socinfo Changhuang Liang
2026-04-05 7:19 ` Krzysztof Kozlowski
2026-04-07 6:49 ` Changhuang Liang
2026-04-07 7:06 ` Krzysztof Kozlowski
2026-04-03 5:49 ` [PATCH v1 12/13] soc: starfive: Add socinfo driver for JHB100 SoC Changhuang Liang
2026-04-03 5:49 ` [PATCH v1 13/13] riscv: dts: starfive: jhb100: Add syscon nodes Changhuang Liang
2026-04-05 7:18 ` [PATCH v1 00/13] Add StarFive JHB100 syscon modules Krzysztof Kozlowski
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