From mboxrd@z Thu Jan 1 00:00:00 1970 From: Sergey Suloev Subject: Re: [PATCH v4 02/11] clk: sunxi-ng: a64: Add max. rate constraint to video PLLs Date: Wed, 5 Sep 2018 13:17:48 +0300 Message-ID: <5f350a8f-b73e-a866-b22c-76b9176d3be1@orpaltech.com> References: <20180904044053.15425-1-icenowy@aosc.io> <20180904044053.15425-3-icenowy@aosc.io> <20180905071645.ibhcuq5coc6gl6k3@flea> Mime-Version: 1.0 Content-Type: multipart/mixed; boundary="===============1366032647==" Return-path: In-Reply-To: <20180905071645.ibhcuq5coc6gl6k3@flea> Content-Language: en-US List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" To: Maxime Ripard , Icenowy Zheng Cc: devicetree@vger.kernel.org, Jernej Skrabec , linux-sunxi@googlegroups.com, dri-devel@lists.freedesktop.org, linux-kernel@vger.kernel.org, Chen-Yu Tsai , Jagan Teki , linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org List-Id: devicetree@vger.kernel.org This is a multi-part message in MIME format. --===============1366032647== Content-Type: multipart/alternative; boundary="------------DAE953FD6AED7CFFE08B834C" Content-Language: en-US This is a multi-part message in MIME format. --------------DAE953FD6AED7CFFE08B834C Content-Type: text/plain; charset=windows-1252; format=flowed Content-Transfer-Encoding: 8bit Hi, On 09/05/2018 10:16 AM, Maxime Ripard wrote: > On Tue, Sep 04, 2018 at 12:40:44PM +0800, Icenowy Zheng wrote: >> Video PLLs on A64 can be set to higher rate that it is actually >> supported by HW. >> >> Limit maximum rate to 1008 MHz. This is the maximum allowed rate by BSP >> clock driver. Interestengly, user manual specifies maximum frequency to >> be 600 MHz. Historically, this data was wrong in some user manuals for >> other SoCs, so more faith is put in BSP clock driver. >> >> Signed-off-by: Icenowy Zheng > Applied, thanks! > Maxime > > > > _______________________________________________ > linux-arm-kernel mailing list > linux-arm-kernel@lists.infradead.org > http://lists.infradead.org/mailman/listinfo/linux-arm-kernel what source tree this patch is supposed to apply for ? I can't find  the SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK_MIN_MAX declaration in 4.19 Thank you Sergey --------------DAE953FD6AED7CFFE08B834C Content-Type: text/html; charset=windows-1252 Content-Transfer-Encoding: 8bit Hi,
On 09/05/2018 10:16 AM, Maxime Ripard wrote:
On Tue, Sep 04, 2018 at 12:40:44PM +0800, Icenowy Zheng wrote:

Video PLLs on A64 can be set to higher rate that it is actually
supported by HW.

Limit maximum rate to 1008 MHz. This is the maximum allowed rate by BSP
clock driver. Interestengly, user manual specifies maximum frequency to
be 600 MHz. Historically, this data was wrong in some user manuals for
other SoCs, so more faith is put in BSP clock driver.

Signed-off-by: Icenowy Zheng <icenowy@aosc.io>

Applied, thanks!
Maxime




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linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
what source tree this patch is supposed to apply for ?
I can't find  the SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK_MIN_MAX declaration in 4.19

Thank you
Sergey
--------------DAE953FD6AED7CFFE08B834C-- --===============1366032647== Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: base64 Content-Disposition: inline X19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX18KZHJpLWRldmVs IG1haWxpbmcgbGlzdApkcmktZGV2ZWxAbGlzdHMuZnJlZWRlc2t0b3Aub3JnCmh0dHBzOi8vbGlz dHMuZnJlZWRlc2t0b3Aub3JnL21haWxtYW4vbGlzdGluZm8vZHJpLWRldmVsCg== --===============1366032647==--