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Thu, 21 Dec 2023 01:32:39 -0800 (PST) Received: from [192.168.0.22] ([78.10.206.178]) by smtp.gmail.com with ESMTPSA id i21-20020a0564020f1500b0055344b92fb6sm915795eda.75.2023.12.21.01.32.38 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Thu, 21 Dec 2023 01:32:39 -0800 (PST) Message-ID: <5f64cd0d-3a64-41bf-ac12-3a73f7cc2dbf@linaro.org> Date: Thu, 21 Dec 2023 10:32:37 +0100 Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [RFC PATCH net-next 1/8] dt-bindings: net: Add support for AM65x SR1.0 in ICSSG Content-Language: en-US To: Diogo Ivo , danishanwar@ti.com, rogerq@kernel.org, davem@davemloft.net, edumazet@google.com, kuba@kernel.org, pabeni@redhat.com, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, conor+dt@kernel.org, linux-arm-kernel@lists.infradead.org, netdev@vger.kernel.org, devicetree@vger.kernel.org Cc: Jan Kiszka References: <20231219174548.3481-1-diogo.ivo@siemens.com> <20231219174548.3481-2-diogo.ivo@siemens.com> From: Krzysztof Kozlowski Autocrypt: addr=krzysztof.kozlowski@linaro.org; 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charset=UTF-8 Content-Transfer-Encoding: 7bit On 19/12/2023 18:45, Diogo Ivo wrote: > Silicon Revision 1.0 of the AM65x came with a slightly different ICSSG > support: Only 2 PRUs per slice are available and instead 2 additional > DMA channels are used for management purposes. We have no restrictions > on specified PRUs, but the DMA channels need to be adjusted. > > Signed-off-by: Jan Kiszka > Signed-off-by: Diogo Ivo > --- > .../bindings/net/ti,icssg-prueth.yaml | 62 +++++++++++++------ > 1 file changed, 44 insertions(+), 18 deletions(-) > > diff --git a/Documentation/devicetree/bindings/net/ti,icssg-prueth.yaml b/Documentation/devicetree/bindings/net/ti,icssg-prueth.yaml > index 229c8f32019f..fbe51731854a 100644 > --- a/Documentation/devicetree/bindings/net/ti,icssg-prueth.yaml > +++ b/Documentation/devicetree/bindings/net/ti,icssg-prueth.yaml > @@ -19,30 +19,15 @@ allOf: > properties: > compatible: > enum: > - - ti,am642-icssg-prueth # for AM64x SoC family > - - ti,am654-icssg-prueth # for AM65x SoC family > + - ti,am642-icssg-prueth # for AM64x SoC family > + - ti,am654-icssg-prueth # for AM65x SoC family, SR2.x > + - ti,am654-icssg-prueth-sr1 # for AM65x SoC family, SR1.0 sr1 is revision of am654, so it should be added to SoC name, not at the end of binding. > > sram: > $ref: /schemas/types.yaml#/definitions/phandle > description: > phandle to MSMC SRAM node > > - dmas: > - maxItems: 10 Why are you removing top-level properties? They must stay here in widest constrains. > - > - dma-names: > - items: > - - const: tx0-0 > - - const: tx0-1 > - - const: tx0-2 > - - const: tx0-3 > - - const: tx1-0 > - - const: tx1-1 > - - const: tx1-2 > - - const: tx1-3 > - - const: rx0 > - - const: rx1 Grow it and use minItems. > - > ti,mii-g-rt: > $ref: /schemas/types.yaml#/definitions/phandle > description: > @@ -122,6 +107,47 @@ properties: > - required: > - port@1 > Missing allOf and then it goes after required block. > +if: > + properties: > + compatible: > + contains: > + enum: > + - ti,am654-icssg-prueth-sr1 > +then: > + properties: > + dmas: minItems > + maxItems: 12 > + dma-names: > + items: minItems instead > + - const: tx0-0 > + - const: tx0-1 > + - const: tx0-2 > + - const: tx0-3 > + - const: tx1-0 > + - const: tx1-1 > + - const: tx1-2 > + - const: tx1-3 > + - const: rx0 > + - const: rx1 > + - const: rxmgm0 > + - const: rxmgm1 > +else: > + properties: > + dmas: > + maxItems: 10 > + dma-names: > + items: maxItems instead Best regards, Krzysztof