From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id BB195C433F5 for ; Mon, 14 Mar 2022 10:18:32 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S238235AbiCNKTk (ORCPT ); Mon, 14 Mar 2022 06:19:40 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:39932 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S238486AbiCNKTj (ORCPT ); Mon, 14 Mar 2022 06:19:39 -0400 Received: from bhuna.collabora.co.uk (bhuna.collabora.co.uk [IPv6:2a00:1098:0:82:1000:25:2eeb:e3e3]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 603BDE30; Mon, 14 Mar 2022 03:18:29 -0700 (PDT) Received: from [127.0.0.1] (localhost [127.0.0.1]) (Authenticated sender: kholk11) with ESMTPSA id 9BB481F43E42 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1647253108; bh=Xhm3zTCf6fMF/1xTFWS49KczB8qcaMTMqtJUqaWvAOQ=; h=Date:Subject:To:Cc:References:From:In-Reply-To:From; b=HebpY9GHsh4/EF1tb4cHCYjdHjqFoVaMStCWf+GYjxlRAznKIX3amuZoiYtQxjE8M IIUk+s1KDRkDTFgsSTXfphKdFlww+OayPkTXu+Jf3EYt5xxqmqgguuIIvvuTOVcZVZ ln9nTOWYrtlF0uoLsEngQLKneKZsZQUE6nB4ez+0c6/gAsrYLdxLLcF9B2yaj47abM Qn150wl9SlffmS6MUiRrpGFpuTBJctTNO79R6IRtJtPfKlyg377hLtWqpE3kLermgu 3YlGn4WBRNl4DkHPKZuUZmVqhXH219FD3YThf3h7kDgqzlJkB08my6jvOx9f7vHvdV Hx/+EuJRSsfLQ== Message-ID: <5f79e76b-1333-159c-2dc7-0f7e8927e4df@collabora.com> Date: Mon, 14 Mar 2022 11:18:25 +0100 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:91.0) Gecko/20100101 Thunderbird/91.5.1 Subject: Re: [v3 03/19] ASoC: mediatek: mt8186: support audsys clock control Content-Language: en-US To: Jiaxin Yu , broonie@kernel.org, robh+dt@kernel.org Cc: aaronyu@google.com, matthias.bgg@gmail.com, trevor.wu@mediatek.com, tzungbi@google.com, julianbraha@gmail.com, alsa-devel@alsa-project.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, linux-kernel@vger.kernel.org, Project_Global_Chrome_Upstream_Group@mediatek.com References: <20220313151023.21229-1-jiaxin.yu@mediatek.com> <20220313151023.21229-4-jiaxin.yu@mediatek.com> From: AngeloGioacchino Del Regno In-Reply-To: <20220313151023.21229-4-jiaxin.yu@mediatek.com> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Il 13/03/22 16:10, Jiaxin Yu ha scritto: > Add mt8186 audio cg control. Audio clock gates are registered to > CCF for reference count and clock parent management. > > Signed-off-by: Jiaxin Yu Reviewed-by: AngeloGioacchino Del Regno > --- > sound/soc/mediatek/mt8186/mt8186-audsys-clk.c | 150 ++++++++++++++++++ > sound/soc/mediatek/mt8186/mt8186-audsys-clk.h | 15 ++ > .../soc/mediatek/mt8186/mt8186-audsys-clkid.h | 45 ++++++ > 3 files changed, 210 insertions(+) > create mode 100644 sound/soc/mediatek/mt8186/mt8186-audsys-clk.c > create mode 100644 sound/soc/mediatek/mt8186/mt8186-audsys-clk.h > create mode 100644 sound/soc/mediatek/mt8186/mt8186-audsys-clkid.h >