From: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
To: Kunihiko Hayashi <hayashi.kunihiko@socionext.com>,
Vinod Koul <vkoul@kernel.org>,
Kishon Vijay Abraham I <kishon@ti.com>,
Rob Herring <robh+dt@kernel.org>,
Krzysztof Kozlowski <krzk+dt@kernel.org>
Cc: Masami Hiramatsu <mhiramat@kernel.org>,
linux-phy@lists.infradead.org, devicetree@vger.kernel.org,
linux-arm-kernel@lists.infradead.org,
linux-kernel@vger.kernel.org
Subject: Re: [PATCH v3 5/5] dt-bindings: phy: uniphier: Clean up clocks, resets, and their names using compatible string
Date: Thu, 31 Mar 2022 07:53:50 +0200 [thread overview]
Message-ID: <5fa843d2-f07c-3bc0-22f1-8a2ae234e9aa@linaro.org> (raw)
In-Reply-To: <d32191fc-1302-89e4-8b24-40fe33867b98@socionext.com>
On 31/03/2022 02:50, Kunihiko Hayashi wrote:
> Hi Krzysztof,
>
> On 2022/03/31 2:40, Krzysztof Kozlowski wrote:
>> On 30/03/2022 12:55, Kunihiko Hayashi wrote:
>>> Instead of "oneOf:" choices, use "allOf:" and "if:" to define clocks,
>>> clock-names, resets, and reset-names that can be taken by the compatible
>>> string.
>>>
>>> The order of clock-names and reset-names doesn't change here.
>>>
>>> Signed-off-by: Kunihiko Hayashi <hayashi.kunihiko@socionext.com>
>>> ---
>>> .../phy/socionext,uniphier-ahci-phy.yaml | 90 +++++++++++++-----
>>> .../phy/socionext,uniphier-pcie-phy.yaml | 47 ++++++---
>>> .../phy/socionext,uniphier-usb3hs-phy.yaml | 93 ++++++++++++++----
>>> .../phy/socionext,uniphier-usb3ss-phy.yaml | 95 +++++++++++++++----
>>> 4 files changed, 251 insertions(+), 74 deletions(-)
>>>
>>
>> (...)
>>
>>> diff --git
>>> a/Documentation/devicetree/bindings/phy/socionext,uniphier-usb3hs-phy.yaml
>>> b/Documentation/devicetree/bindings/phy/socionext,uniphier-usb3hs-phy.yaml
>>> index 1bbd164f2527..21e4414eea60 100644
>>> ---
>>> a/Documentation/devicetree/bindings/phy/socionext,uniphier-usb3hs-phy.yaml
>>> +++
>>> b/Documentation/devicetree/bindings/phy/socionext,uniphier-usb3hs-phy.yaml
>>> @@ -34,30 +34,12 @@ properties:
>>> minItems: 2
>>> maxItems: 3
>>>
>>> - clock-names:
>>> - oneOf:
>>> - - items: # for Pro5
>>> - - const: gio
>>> - - const: link
>>> - - items: # for PXs3 with phy-ext
>>> - - const: link
>>> - - const: phy
>>> - - const: phy-ext
>>> - - items: # for others
>>> - - const: link
>>> - - const: phy
>>> + clock-names: true
>>>
>>> resets:
>>> maxItems: 2
>>>
>>> - reset-names:
>>> - oneOf:
>>> - - items: # for Pro5
>>> - - const: gio
>>> - - const: link
>>> - - items: # for others
>>> - - const: link
>>> - - const: phy
>>> + reset-names: true
>>>
>>> vbus-supply:
>>> description: A phandle to the regulator for USB VBUS
>>> @@ -80,6 +62,77 @@ properties:
>>> required for each port, if any one is omitted, the trimming data
>>> of the port will not be set at all.
>>>
>>> +allOf:
>>> + - if:
>>> + properties:
>>> + compatible:
>>> + contains:
>>> + const: socionext,uniphier-pro5-usb3-hsphy
>>> + then:
>>> + properties:
>>> + clocks:
>>> + minItems: 2
>>> + maxItems: 2
>>> + clock-names:
>>> + items:
>>> + - const: gio
>>> + - const: link
>>> + resets:
>>> + minItems: 2
>>> + maxItems: 2
>>> + reset-names:
>>> + items:
>>> + - const: gio
>>> + - const: link
>>> + - if:
>>> + properties:
>>> + compatible:
>>> + contains:
>>> + enum:
>>> + - socionext,uniphier-pxs2-usb3-hsphy
>>> + - socionext,uniphier-ld20-usb3-hsphy
>>> + then:
>>> + properties:
>>> + clocks:
>>> + minItems: 2
>>> + maxItems: 2
>>> + clock-names:
>>> + items:
>>> + - const: link
>>> + - const: phy
>>> + resets:
>>> + minItems: 2
>>> + maxItems: 2
>>> + reset-names:
>>> + items:
>>> + - const: link
>>> + - const: phy
>>> + - if:
>>> + properties:
>>> + compatible:
>>> + contains:
>>> + enum:
>>> + - socionext,uniphier-pxs3-usb3-hsphy
>>> + - socionext,uniphier-nx1-usb3-hsphy
>>> + then:
>>> + properties:
>>> + clocks:
>>> + minItems: 2
>>
>> Why minItems:2? Is the last phy-ext clock optional?
>
> In an SoC with two controllers, there is a controller that requires extra
> clock and a controller that does not. For example, PXs3 USB3 controller 1
> needs "phy-ext" clock, but the controller 0 doesn't.
>
> This difference is related to the phy configuration, where the controller 1
> requires more clocks because it shares the phy with other subsystems.
>
> So I think the last phy-ext clock should be optional.
>
OK, thanks for explanation. I assume we talk about the hardware, not
about Linux driver needs. :)
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Best regards,
Krzysztof
next prev parent reply other threads:[~2022-03-31 5:53 UTC|newest]
Thread overview: 10+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-03-30 10:55 [PATCH v3 0/5] dt-bindings: phy: Fix uniphier descriptions Kunihiko Hayashi
2022-03-30 10:55 ` [PATCH v3 1/5] dt-bindings: phy: uniphier-usb2: Add vbus-supply Kunihiko Hayashi
2022-03-30 10:55 ` [PATCH v3 2/5] dt-bindings: phy: uniphier-usb3ss: Treat vbus-supply as optional Kunihiko Hayashi
2022-03-30 10:55 ` [PATCH v3 3/5] dt-bindings: phy: uniphier-ahci: Fix missing reset-names Kunihiko Hayashi
2022-03-30 10:55 ` [PATCH v3 4/5] dt-bindings: phy: uniphier-usb3hs: Fix incorrect clock-names and reset-names Kunihiko Hayashi
2022-03-30 10:55 ` [PATCH v3 5/5] dt-bindings: phy: uniphier: Clean up clocks, resets, and their names using compatible string Kunihiko Hayashi
2022-03-30 17:40 ` Krzysztof Kozlowski
2022-03-31 0:50 ` Kunihiko Hayashi
2022-03-31 5:53 ` Krzysztof Kozlowski [this message]
2022-04-13 6:42 ` [PATCH v3 0/5] dt-bindings: phy: Fix uniphier descriptions Vinod Koul
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