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[188.155.201.27]) by smtp.gmail.com with ESMTPSA id dm11-20020a170907948b00b006cf488e72e3sm9041961ejc.25.2022.03.30.22.53.51 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Wed, 30 Mar 2022 22:53:51 -0700 (PDT) Message-ID: <5fa843d2-f07c-3bc0-22f1-8a2ae234e9aa@linaro.org> Date: Thu, 31 Mar 2022 07:53:50 +0200 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:91.0) Gecko/20100101 Thunderbird/91.7.0 Subject: Re: [PATCH v3 5/5] dt-bindings: phy: uniphier: Clean up clocks, resets, and their names using compatible string Content-Language: en-US To: Kunihiko Hayashi , Vinod Koul , Kishon Vijay Abraham I , Rob Herring , Krzysztof Kozlowski Cc: Masami Hiramatsu , linux-phy@lists.infradead.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org References: <1648637715-19262-1-git-send-email-hayashi.kunihiko@socionext.com> <1648637715-19262-6-git-send-email-hayashi.kunihiko@socionext.com> From: Krzysztof Kozlowski In-Reply-To: Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org On 31/03/2022 02:50, Kunihiko Hayashi wrote: > Hi Krzysztof, > > On 2022/03/31 2:40, Krzysztof Kozlowski wrote: >> On 30/03/2022 12:55, Kunihiko Hayashi wrote: >>> Instead of "oneOf:" choices, use "allOf:" and "if:" to define clocks, >>> clock-names, resets, and reset-names that can be taken by the compatible >>> string. >>> >>> The order of clock-names and reset-names doesn't change here. >>> >>> Signed-off-by: Kunihiko Hayashi >>> --- >>> .../phy/socionext,uniphier-ahci-phy.yaml | 90 +++++++++++++----- >>> .../phy/socionext,uniphier-pcie-phy.yaml | 47 ++++++--- >>> .../phy/socionext,uniphier-usb3hs-phy.yaml | 93 ++++++++++++++---- >>> .../phy/socionext,uniphier-usb3ss-phy.yaml | 95 +++++++++++++++---- >>> 4 files changed, 251 insertions(+), 74 deletions(-) >>> >> >> (...) >> >>> diff --git >>> a/Documentation/devicetree/bindings/phy/socionext,uniphier-usb3hs-phy.yaml >>> b/Documentation/devicetree/bindings/phy/socionext,uniphier-usb3hs-phy.yaml >>> index 1bbd164f2527..21e4414eea60 100644 >>> --- >>> a/Documentation/devicetree/bindings/phy/socionext,uniphier-usb3hs-phy.yaml >>> +++ >>> b/Documentation/devicetree/bindings/phy/socionext,uniphier-usb3hs-phy.yaml >>> @@ -34,30 +34,12 @@ properties: >>> minItems: 2 >>> maxItems: 3 >>> >>> - clock-names: >>> - oneOf: >>> - - items: # for Pro5 >>> - - const: gio >>> - - const: link >>> - - items: # for PXs3 with phy-ext >>> - - const: link >>> - - const: phy >>> - - const: phy-ext >>> - - items: # for others >>> - - const: link >>> - - const: phy >>> + clock-names: true >>> >>> resets: >>> maxItems: 2 >>> >>> - reset-names: >>> - oneOf: >>> - - items: # for Pro5 >>> - - const: gio >>> - - const: link >>> - - items: # for others >>> - - const: link >>> - - const: phy >>> + reset-names: true >>> >>> vbus-supply: >>> description: A phandle to the regulator for USB VBUS >>> @@ -80,6 +62,77 @@ properties: >>> required for each port, if any one is omitted, the trimming data >>> of the port will not be set at all. >>> >>> +allOf: >>> + - if: >>> + properties: >>> + compatible: >>> + contains: >>> + const: socionext,uniphier-pro5-usb3-hsphy >>> + then: >>> + properties: >>> + clocks: >>> + minItems: 2 >>> + maxItems: 2 >>> + clock-names: >>> + items: >>> + - const: gio >>> + - const: link >>> + resets: >>> + minItems: 2 >>> + maxItems: 2 >>> + reset-names: >>> + items: >>> + - const: gio >>> + - const: link >>> + - if: >>> + properties: >>> + compatible: >>> + contains: >>> + enum: >>> + - socionext,uniphier-pxs2-usb3-hsphy >>> + - socionext,uniphier-ld20-usb3-hsphy >>> + then: >>> + properties: >>> + clocks: >>> + minItems: 2 >>> + maxItems: 2 >>> + clock-names: >>> + items: >>> + - const: link >>> + - const: phy >>> + resets: >>> + minItems: 2 >>> + maxItems: 2 >>> + reset-names: >>> + items: >>> + - const: link >>> + - const: phy >>> + - if: >>> + properties: >>> + compatible: >>> + contains: >>> + enum: >>> + - socionext,uniphier-pxs3-usb3-hsphy >>> + - socionext,uniphier-nx1-usb3-hsphy >>> + then: >>> + properties: >>> + clocks: >>> + minItems: 2 >> >> Why minItems:2? Is the last phy-ext clock optional? > > In an SoC with two controllers, there is a controller that requires extra > clock and a controller that does not. For example, PXs3 USB3 controller 1 > needs "phy-ext" clock, but the controller 0 doesn't. > > This difference is related to the phy configuration, where the controller 1 > requires more clocks because it shares the phy with other subsystems. > > So I think the last phy-ext clock should be optional. > OK, thanks for explanation. I assume we talk about the hardware, not about Linux driver needs. :) Reviewed-by: Krzysztof Kozlowski Best regards, Krzysztof