[PATCH next-next v4 0/2] Add support for partial store and forward

[PATCH next-next v4 0/2] Add support for partial store and forward

[Pranavi Somisetty]

Add support for partial store and forward mode in Cadence MACB.

Link for v1:
https://lore.kernel.org/all/20221213121245.13981-1-pranavi.somisetty@amd.com/

Changes v2:
1. Removed all the changes related to validating FCS when Rx checksum
offload is disabled.
2. Instead of using a platform dependent number (0xFFF) for the reset
value of rx watermark, derive it from designcfg_debug2 register.
3. Added a check to see if partial s/f is supported, by reading the
designcfg_debug6 register.
4. Added devicetree bindings for "rx-watermark" property.
Link for v2:
https://lore.kernel.org/all/20230511071214.18611-1-pranavi.somisetty@amd.com/

Changes v3:
1. Fixed DT schema error: "scalar properties shouldn't have array keywords"
2. Modified description of rx-watermark in to include units of the watermark value
3. Modified the DT property name corresponding to rx_watermark in pbuf_rxcutthru to
"cdns,rx-watermark".
4. Followed reverse christmas tree pattern in declaring variables.
5. Return -EINVAL when an invalid watermark value is set.
6. Removed netdev_info when partial store and forward is not enabled.
7. Validating the rx-watermark value in probe itself and only write to the register
in init.
8. Writing a reset value to the pbuf_cuthru register before disabing partial store
and forward is redundant. So removing it.
9. Removed the platform caps flag.
10. Instead of reading rx-watermark from DT in macb_configure_caps,
reading it in probe.
11. Changed Signed-Off-By and author names on the macb driver patch.
Link for v3:
https://lore.kernel.org/all/20230530095138.1302-1-pranavi.somisetty@amd.com/

Changes v4:
1. Modified description for "rx-watermark" property in the DT bindings.
2. Changed the width of the rx-watermark property to uint32.
3. Removed redundant code and unused variables.
4. When the rx-watermark value is invalid, instead of returning EINVAL,
do not enable partial store and forward. 

Maulik Jodhani (1):
  net: macb: Add support for partial store and forward

Pranavi Somisetty (1):
  dt-bindings: net: cdns,macb: Add rx-watermark property

 .../devicetree/bindings/net/cdns,macb.yaml    | 11 ++++++++
 drivers/net/ethernet/cadence/macb.h           | 12 +++++++++
 drivers/net/ethernet/cadence/macb_main.c      | 27 +++++++++++++++++++
 3 files changed, 50 insertions(+)

-- 
2.36.1

[PATCH net-next v4 1/2] dt-bindings: net: cdns,macb: Add rx-watermark property

[Pranavi Somisetty]

watermark value is the minimum amount of packet data
required to activate the forwarding process. The watermark
implementation and maximum size is dependent on the device
where Cadence MACB/GEM is used.

Signed-off-by: Pranavi Somisetty <pranavi.somisetty@amd.com>
---
Changes v2:
None (patch added in v2)

Changes v3:
1. Fixed DT schema error: "scalar properties shouldn't have array keywords".
2. Modified description of rx-watermark to include units of the watermark value.
3. Modified the DT property name corresponding to rx_watermark in
pbuf_rxcutthru to "cdns,rx-watermark".
4. Modified commit description to remove references to Xilinx platforms,
since the changes aren't platform specific.

Changes v4:
1. Modified description for "rx-watermark" property in the DT bindings.
2. Changed the width of the rx-watermark property to uint32.
---
 Documentation/devicetree/bindings/net/cdns,macb.yaml | 11 +++++++++++
 1 file changed, 11 insertions(+)

diff --git a/Documentation/devicetree/bindings/net/cdns,macb.yaml b/Documentation/devicetree/bindings/net/cdns,macb.yaml
index bef5e0f895be..bf8894a0257e 100644
--- a/Documentation/devicetree/bindings/net/cdns,macb.yaml
+++ b/Documentation/devicetree/bindings/net/cdns,macb.yaml
@@ -109,6 +109,16 @@ properties:
   power-domains:
     maxItems: 1
 
+  cdns,rx-watermark:
+    $ref: /schemas/types.yaml#/definitions/uint32
+    description:
+      When the receive partial store and forward mode is activated,
+      the receiver will only begin to forward the packet to the external
+      AHB or AXI slave when enough packet data is stored in the SRAM packet buffer.
+      rx-watermark corresponds to the number of SRAM buffer locations,
+      that need to be filled, before the forwarding process is activated.
+      Width of the SRAM is platform dependent, and can be 4, 8 or 16 bytes.
+
   '#address-cells':
     const: 1
 
@@ -166,6 +176,7 @@ examples:
             compatible = "cdns,macb";
             reg = <0xfffc4000 0x4000>;
             interrupts = <21>;
+            cdns,rx-watermark = <0x44>;
             phy-mode = "rmii";
             local-mac-address = [3a 0e 03 04 05 06];
             clock-names = "pclk", "hclk", "tx_clk";
-- 
2.36.1

Re: [PATCH net-next v4 1/2] dt-bindings: net: cdns,macb: Add rx-watermark property

[Krzysztof Kozlowski]

On 13/06/2023 07:43, Pranavi Somisetty wrote:
> watermark value is the minimum amount of packet data
> required to activate the forwarding process. The watermark
> implementation and maximum size is dependent on the device
> where Cadence MACB/GEM is used.
> 
> Signed-off-by: Pranavi Somisetty <pranavi.somisetty@amd.com>
> ---
> Changes v2:


Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>

Best regards,
Krzysztof

Re: [PATCH net-next v4 1/2] dt-bindings: net: cdns,macb: Add rx-watermark property

[Nicolas Ferre]

On 15/06/2023 at 10:23, Krzysztof Kozlowski wrote:
> EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe
> 
> On 13/06/2023 07:43, Pranavi Somisetty wrote:
>> watermark value is the minimum amount of packet data
>> required to activate the forwarding process. The watermark
>> implementation and maximum size is dependent on the device
>> where Cadence MACB/GEM is used.
>>
>> Signed-off-by: Pranavi Somisetty <pranavi.somisetty@amd.com>
>> ---
>> Changes v2:
> 
> 
> Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>

If mine is needed as well:
Acked-by: Nicolas Ferre <nicolas.ferre@microchip.com>


-- 
Nicolas Ferre

[PATCH net-next v4 2/2] net: macb: Add support for partial store and forward

[Pranavi Somisetty]

From: Maulik Jodhani <maulik.jodhani@xilinx.com>

When the receive partial store and forward mode is activated, the
receiver will only begin to forward the packet to the external AHB
or AXI slave when enough packet data is stored in the packet buffer.
The amount of packet data required to activate the forwarding process
is programmable via watermark registers which are located at the same
address as the partial store and forward enable bits. Adding support to
read this rx-watermark value from device-tree, to program the watermark
registers and enable partial store and forwarding.

Signed-off-by: Maulik Jodhani <maulik.jodhani@xilinx.com>
Signed-off-by: Pranavi Somisetty <pranavi.somisetty@amd.com>
---
Changes v2:
1. Removed all the changes related to validating FCS when Rx checksum offload is disabled.
2. Instead of using a platform dependent number (0xFFF) for the reset value of rx watermark,
derive it from designcfg_debug2 register.
3. Added a check to see if partial s/f is supported, by reading the
designcfg_debug6 register.

Changes v3:
1. Followed reverse christmas tree pattern in declaring variables.
2. Return -EINVAL when an invalid watermark value is set.
3. Removed netdev_info when partial store and forward is not enabled.
4. Validating the rx-watermark value in probe itself and only write to the register
in init.
5. Writing a reset value to the pbuf_cuthru register before disabing partial store
and forward is redundant. So removing it.
6. Removed the platform caps flag.
7. Instead of reading rx-watermark from DT in macb_configure_caps,
reading it in probe.
8. Changed Signed-Off-By and author names on this patch.

Changes v4:
1. Removed redundant code and unused variables.
2. When the rx-watermark value is invalid, instead of returning EINVAL,
do not enable partial store and forward.
3. Change rx-watermark variable's size to u32 instead of u16.
---
 drivers/net/ethernet/cadence/macb.h      | 12 +++++++++++
 drivers/net/ethernet/cadence/macb_main.c | 27 ++++++++++++++++++++++++
 2 files changed, 39 insertions(+)

diff --git a/drivers/net/ethernet/cadence/macb.h b/drivers/net/ethernet/cadence/macb.h
index 14dfec4db8f9..39d53117a8ce 100644
--- a/drivers/net/ethernet/cadence/macb.h
+++ b/drivers/net/ethernet/cadence/macb.h
@@ -82,6 +82,7 @@
 #define GEM_NCFGR		0x0004 /* Network Config */
 #define GEM_USRIO		0x000c /* User IO */
 #define GEM_DMACFG		0x0010 /* DMA Configuration */
+#define GEM_PBUFRXCUT		0x0044 /* RX Partial Store and Forward */
 #define GEM_JML			0x0048 /* Jumbo Max Length */
 #define GEM_HS_MAC_CONFIG	0x0050 /* GEM high speed config */
 #define GEM_HRB			0x0080 /* Hash Bottom */
@@ -343,6 +344,10 @@
 #define GEM_ADDR64_SIZE		1
 
 
+/* Bitfields in PBUFRXCUT */
+#define GEM_ENCUTTHRU_OFFSET	31 /* Enable RX partial store and forward */
+#define GEM_ENCUTTHRU_SIZE	1
+
 /* Bitfields in NSR */
 #define MACB_NSR_LINK_OFFSET	0 /* pcs_link_state */
 #define MACB_NSR_LINK_SIZE	1
@@ -509,6 +514,8 @@
 #define GEM_TX_PKT_BUFF_OFFSET			21
 #define GEM_TX_PKT_BUFF_SIZE			1
 
+#define GEM_RX_PBUF_ADDR_OFFSET			22
+#define GEM_RX_PBUF_ADDR_SIZE			4
 
 /* Bitfields in DCFG5. */
 #define GEM_TSU_OFFSET				8
@@ -517,6 +524,8 @@
 /* Bitfields in DCFG6. */
 #define GEM_PBUF_LSO_OFFSET			27
 #define GEM_PBUF_LSO_SIZE			1
+#define GEM_PBUF_CUTTHRU_OFFSET			25
+#define GEM_PBUF_CUTTHRU_SIZE			1
 #define GEM_DAW64_OFFSET			23
 #define GEM_DAW64_SIZE				1
 
@@ -1283,6 +1292,9 @@ struct macb {
 
 	u32			wol;
 
+	/* holds value of rx watermark value for pbuf_rxcutthru register */
+	u32			rx_watermark;
+
 	struct macb_ptp_info	*ptp_info;	/* macb-ptp interface */
 
 	struct phy		*sgmii_phy;	/* for ZynqMP SGMII mode */
diff --git a/drivers/net/ethernet/cadence/macb_main.c b/drivers/net/ethernet/cadence/macb_main.c
index 41964fd02452..7d023b92b169 100644
--- a/drivers/net/ethernet/cadence/macb_main.c
+++ b/drivers/net/ethernet/cadence/macb_main.c
@@ -2617,6 +2617,9 @@ static void macb_reset_hw(struct macb *bp)
 	macb_writel(bp, TSR, -1);
 	macb_writel(bp, RSR, -1);
 
+	/* Disable RX partial store and forward and reset watermark value */
+	gem_writel(bp, PBUFRXCUT, 0);
+
 	/* Disable all interrupts */
 	for (q = 0, queue = bp->queues; q < bp->num_queues; ++q, ++queue) {
 		queue_writel(queue, IDR, -1);
@@ -2770,6 +2773,10 @@ static void macb_init_hw(struct macb *bp)
 		bp->rx_frm_len_mask = MACB_RX_JFRMLEN_MASK;
 
 	macb_configure_dma(bp);
+
+	/* Enable RX partial store and forward and set watermark */
+	if (bp->rx_watermark)
+		gem_writel(bp, PBUFRXCUT, (bp->rx_watermark | GEM_BIT(ENCUTTHRU)));
 }
 
 /* The hash address register is 64 bits long and takes up two
@@ -4923,6 +4930,7 @@ static int macb_probe(struct platform_device *pdev)
 	phy_interface_t interface;
 	struct net_device *dev;
 	struct resource *regs;
+	u32 wtrmrk_rst_val;
 	void __iomem *mem;
 	struct macb *bp;
 	int err, val;
@@ -4995,6 +5003,25 @@ static int macb_probe(struct platform_device *pdev)
 
 	bp->usrio = macb_config->usrio;
 
+	/* By default we set to partial store and forward mode for zynqmp.
+	 * Disable if not set in devicetree.
+	 */
+	if (GEM_BFEXT(PBUF_CUTTHRU, gem_readl(bp, DCFG6))) {
+		err = of_property_read_u32(bp->pdev->dev.of_node,
+					   "cdns,rx-watermark",
+					   &bp->rx_watermark);
+
+		if (!err) {
+			/* Disable partial store and forward in case of error or
+			 * invalid watermark value
+			 */
+			wtrmrk_rst_val = (1 << (GEM_BFEXT(RX_PBUF_ADDR, gem_readl(bp, DCFG2)))) - 1;
+			if (bp->rx_watermark > wtrmrk_rst_val || !bp->rx_watermark) {
+				dev_info(&bp->pdev->dev, "Invalid watermark value\n");
+				bp->rx_watermark = 0;
+			}
+		}
+	}
 	spin_lock_init(&bp->lock);
 
 	/* setup capabilities */
-- 
2.36.1

Re: [PATCH net-next v4 2/2] net: macb: Add support for partial store and forward

[Claudiu.Beznea]

On 13.06.2023 08:43, Pranavi Somisetty wrote:
> EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe
> 
> From: Maulik Jodhani <maulik.jodhani@xilinx.com>
> 
> When the receive partial store and forward mode is activated, the
> receiver will only begin to forward the packet to the external AHB
> or AXI slave when enough packet data is stored in the packet buffer.
> The amount of packet data required to activate the forwarding process
> is programmable via watermark registers which are located at the same
> address as the partial store and forward enable bits. Adding support to
> read this rx-watermark value from device-tree, to program the watermark
> registers and enable partial store and forwarding.
> 
> Signed-off-by: Maulik Jodhani <maulik.jodhani@xilinx.com>
> Signed-off-by: Pranavi Somisetty <pranavi.somisetty@amd.com>

Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com>


> ---
> Changes v2:
> 1. Removed all the changes related to validating FCS when Rx checksum offload is disabled.
> 2. Instead of using a platform dependent number (0xFFF) for the reset value of rx watermark,
> derive it from designcfg_debug2 register.
> 3. Added a check to see if partial s/f is supported, by reading the
> designcfg_debug6 register.
> 
> Changes v3:
> 1. Followed reverse christmas tree pattern in declaring variables.
> 2. Return -EINVAL when an invalid watermark value is set.
> 3. Removed netdev_info when partial store and forward is not enabled.
> 4. Validating the rx-watermark value in probe itself and only write to the register
> in init.
> 5. Writing a reset value to the pbuf_cuthru register before disabing partial store
> and forward is redundant. So removing it.
> 6. Removed the platform caps flag.
> 7. Instead of reading rx-watermark from DT in macb_configure_caps,
> reading it in probe.
> 8. Changed Signed-Off-By and author names on this patch.
> 
> Changes v4:
> 1. Removed redundant code and unused variables.
> 2. When the rx-watermark value is invalid, instead of returning EINVAL,
> do not enable partial store and forward.
> 3. Change rx-watermark variable's size to u32 instead of u16.
> ---
>  drivers/net/ethernet/cadence/macb.h      | 12 +++++++++++
>  drivers/net/ethernet/cadence/macb_main.c | 27 ++++++++++++++++++++++++
>  2 files changed, 39 insertions(+)
> 
> diff --git a/drivers/net/ethernet/cadence/macb.h b/drivers/net/ethernet/cadence/macb.h
> index 14dfec4db8f9..39d53117a8ce 100644
> --- a/drivers/net/ethernet/cadence/macb.h
> +++ b/drivers/net/ethernet/cadence/macb.h
> @@ -82,6 +82,7 @@
>  #define GEM_NCFGR              0x0004 /* Network Config */
>  #define GEM_USRIO              0x000c /* User IO */
>  #define GEM_DMACFG             0x0010 /* DMA Configuration */
> +#define GEM_PBUFRXCUT          0x0044 /* RX Partial Store and Forward */
>  #define GEM_JML                        0x0048 /* Jumbo Max Length */
>  #define GEM_HS_MAC_CONFIG      0x0050 /* GEM high speed config */
>  #define GEM_HRB                        0x0080 /* Hash Bottom */
> @@ -343,6 +344,10 @@
>  #define GEM_ADDR64_SIZE                1
> 
> 
> +/* Bitfields in PBUFRXCUT */
> +#define GEM_ENCUTTHRU_OFFSET   31 /* Enable RX partial store and forward */
> +#define GEM_ENCUTTHRU_SIZE     1
> +
>  /* Bitfields in NSR */
>  #define MACB_NSR_LINK_OFFSET   0 /* pcs_link_state */
>  #define MACB_NSR_LINK_SIZE     1
> @@ -509,6 +514,8 @@
>  #define GEM_TX_PKT_BUFF_OFFSET                 21
>  #define GEM_TX_PKT_BUFF_SIZE                   1
> 
> +#define GEM_RX_PBUF_ADDR_OFFSET                        22
> +#define GEM_RX_PBUF_ADDR_SIZE                  4
> 
>  /* Bitfields in DCFG5. */
>  #define GEM_TSU_OFFSET                         8
> @@ -517,6 +524,8 @@
>  /* Bitfields in DCFG6. */
>  #define GEM_PBUF_LSO_OFFSET                    27
>  #define GEM_PBUF_LSO_SIZE                      1
> +#define GEM_PBUF_CUTTHRU_OFFSET                        25
> +#define GEM_PBUF_CUTTHRU_SIZE                  1
>  #define GEM_DAW64_OFFSET                       23
>  #define GEM_DAW64_SIZE                         1
> 
> @@ -1283,6 +1292,9 @@ struct macb {
> 
>         u32                     wol;
> 
> +       /* holds value of rx watermark value for pbuf_rxcutthru register */
> +       u32                     rx_watermark;
> +
>         struct macb_ptp_info    *ptp_info;      /* macb-ptp interface */
> 
>         struct phy              *sgmii_phy;     /* for ZynqMP SGMII mode */
> diff --git a/drivers/net/ethernet/cadence/macb_main.c b/drivers/net/ethernet/cadence/macb_main.c
> index 41964fd02452..7d023b92b169 100644
> --- a/drivers/net/ethernet/cadence/macb_main.c
> +++ b/drivers/net/ethernet/cadence/macb_main.c
> @@ -2617,6 +2617,9 @@ static void macb_reset_hw(struct macb *bp)
>         macb_writel(bp, TSR, -1);
>         macb_writel(bp, RSR, -1);
> 
> +       /* Disable RX partial store and forward and reset watermark value */
> +       gem_writel(bp, PBUFRXCUT, 0);
> +
>         /* Disable all interrupts */
>         for (q = 0, queue = bp->queues; q < bp->num_queues; ++q, ++queue) {
>                 queue_writel(queue, IDR, -1);
> @@ -2770,6 +2773,10 @@ static void macb_init_hw(struct macb *bp)
>                 bp->rx_frm_len_mask = MACB_RX_JFRMLEN_MASK;
> 
>         macb_configure_dma(bp);
> +
> +       /* Enable RX partial store and forward and set watermark */
> +       if (bp->rx_watermark)
> +               gem_writel(bp, PBUFRXCUT, (bp->rx_watermark | GEM_BIT(ENCUTTHRU)));
>  }
> 
>  /* The hash address register is 64 bits long and takes up two
> @@ -4923,6 +4930,7 @@ static int macb_probe(struct platform_device *pdev)
>         phy_interface_t interface;
>         struct net_device *dev;
>         struct resource *regs;
> +       u32 wtrmrk_rst_val;
>         void __iomem *mem;
>         struct macb *bp;
>         int err, val;
> @@ -4995,6 +5003,25 @@ static int macb_probe(struct platform_device *pdev)
> 
>         bp->usrio = macb_config->usrio;
> 
> +       /* By default we set to partial store and forward mode for zynqmp.
> +        * Disable if not set in devicetree.
> +        */
> +       if (GEM_BFEXT(PBUF_CUTTHRU, gem_readl(bp, DCFG6))) {
> +               err = of_property_read_u32(bp->pdev->dev.of_node,
> +                                          "cdns,rx-watermark",
> +                                          &bp->rx_watermark);
> +
> +               if (!err) {
> +                       /* Disable partial store and forward in case of error or
> +                        * invalid watermark value
> +                        */
> +                       wtrmrk_rst_val = (1 << (GEM_BFEXT(RX_PBUF_ADDR, gem_readl(bp, DCFG2)))) - 1;
> +                       if (bp->rx_watermark > wtrmrk_rst_val || !bp->rx_watermark) {
> +                               dev_info(&bp->pdev->dev, "Invalid watermark value\n");
> +                               bp->rx_watermark = 0;
> +                       }
> +               }
> +       }
>         spin_lock_init(&bp->lock);
> 
>         /* setup capabilities */
> --
> 2.36.1
> 

Re: [PATCH net-next v4 2/2] net: macb: Add support for partial store and forward

[Nicolas Ferre]

On 13/06/2023 at 07:43, Pranavi Somisetty wrote:
> EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe
> 
> From: Maulik Jodhani <maulik.jodhani@xilinx.com>
> 
> When the receive partial store and forward mode is activated, the
> receiver will only begin to forward the packet to the external AHB
> or AXI slave when enough packet data is stored in the packet buffer.
> The amount of packet data required to activate the forwarding process
> is programmable via watermark registers which are located at the same
> address as the partial store and forward enable bits. Adding support to
> read this rx-watermark value from device-tree, to program the watermark
> registers and enable partial store and forwarding.
> 
> Signed-off-by: Maulik Jodhani <maulik.jodhani@xilinx.com>
> Signed-off-by: Pranavi Somisetty <pranavi.somisetty@amd.com>

Looks good to me:
Acked-by: Nicolas Ferre <nicolas.ferre@microchip.com>

Thanks for your patch and effort to address comments Pranavi.

Best regards,
   Nicolas

> ---
> Changes v2:
> 1. Removed all the changes related to validating FCS when Rx checksum offload is disabled.
> 2. Instead of using a platform dependent number (0xFFF) for the reset value of rx watermark,
> derive it from designcfg_debug2 register.
> 3. Added a check to see if partial s/f is supported, by reading the
> designcfg_debug6 register.
> 
> Changes v3:
> 1. Followed reverse christmas tree pattern in declaring variables.
> 2. Return -EINVAL when an invalid watermark value is set.
> 3. Removed netdev_info when partial store and forward is not enabled.
> 4. Validating the rx-watermark value in probe itself and only write to the register
> in init.
> 5. Writing a reset value to the pbuf_cuthru register before disabing partial store
> and forward is redundant. So removing it.
> 6. Removed the platform caps flag.
> 7. Instead of reading rx-watermark from DT in macb_configure_caps,
> reading it in probe.
> 8. Changed Signed-Off-By and author names on this patch.
> 
> Changes v4:
> 1. Removed redundant code and unused variables.
> 2. When the rx-watermark value is invalid, instead of returning EINVAL,
> do not enable partial store and forward.
> 3. Change rx-watermark variable's size to u32 instead of u16.
> ---
>   drivers/net/ethernet/cadence/macb.h      | 12 +++++++++++
>   drivers/net/ethernet/cadence/macb_main.c | 27 ++++++++++++++++++++++++
>   2 files changed, 39 insertions(+)
> 
> diff --git a/drivers/net/ethernet/cadence/macb.h b/drivers/net/ethernet/cadence/macb.h
> index 14dfec4db8f9..39d53117a8ce 100644
> --- a/drivers/net/ethernet/cadence/macb.h
> +++ b/drivers/net/ethernet/cadence/macb.h
> @@ -82,6 +82,7 @@
>   #define GEM_NCFGR              0x0004 /* Network Config */
>   #define GEM_USRIO              0x000c /* User IO */
>   #define GEM_DMACFG             0x0010 /* DMA Configuration */
> +#define GEM_PBUFRXCUT          0x0044 /* RX Partial Store and Forward */
>   #define GEM_JML                        0x0048 /* Jumbo Max Length */
>   #define GEM_HS_MAC_CONFIG      0x0050 /* GEM high speed config */
>   #define GEM_HRB                        0x0080 /* Hash Bottom */
> @@ -343,6 +344,10 @@
>   #define GEM_ADDR64_SIZE                1
> 
> 
> +/* Bitfields in PBUFRXCUT */
> +#define GEM_ENCUTTHRU_OFFSET   31 /* Enable RX partial store and forward */
> +#define GEM_ENCUTTHRU_SIZE     1
> +
>   /* Bitfields in NSR */
>   #define MACB_NSR_LINK_OFFSET   0 /* pcs_link_state */
>   #define MACB_NSR_LINK_SIZE     1
> @@ -509,6 +514,8 @@
>   #define GEM_TX_PKT_BUFF_OFFSET                 21
>   #define GEM_TX_PKT_BUFF_SIZE                   1
> 
> +#define GEM_RX_PBUF_ADDR_OFFSET                        22
> +#define GEM_RX_PBUF_ADDR_SIZE                  4
> 
>   /* Bitfields in DCFG5. */
>   #define GEM_TSU_OFFSET                         8
> @@ -517,6 +524,8 @@
>   /* Bitfields in DCFG6. */
>   #define GEM_PBUF_LSO_OFFSET                    27
>   #define GEM_PBUF_LSO_SIZE                      1
> +#define GEM_PBUF_CUTTHRU_OFFSET                        25
> +#define GEM_PBUF_CUTTHRU_SIZE                  1
>   #define GEM_DAW64_OFFSET                       23
>   #define GEM_DAW64_SIZE                         1
> 
> @@ -1283,6 +1292,9 @@ struct macb {
> 
>          u32                     wol;
> 
> +       /* holds value of rx watermark value for pbuf_rxcutthru register */
> +       u32                     rx_watermark;
> +
>          struct macb_ptp_info    *ptp_info;      /* macb-ptp interface */
> 
>          struct phy              *sgmii_phy;     /* for ZynqMP SGMII mode */
> diff --git a/drivers/net/ethernet/cadence/macb_main.c b/drivers/net/ethernet/cadence/macb_main.c
> index 41964fd02452..7d023b92b169 100644
> --- a/drivers/net/ethernet/cadence/macb_main.c
> +++ b/drivers/net/ethernet/cadence/macb_main.c
> @@ -2617,6 +2617,9 @@ static void macb_reset_hw(struct macb *bp)
>          macb_writel(bp, TSR, -1);
>          macb_writel(bp, RSR, -1);
> 
> +       /* Disable RX partial store and forward and reset watermark value */
> +       gem_writel(bp, PBUFRXCUT, 0);
> +
>          /* Disable all interrupts */
>          for (q = 0, queue = bp->queues; q < bp->num_queues; ++q, ++queue) {
>                  queue_writel(queue, IDR, -1);
> @@ -2770,6 +2773,10 @@ static void macb_init_hw(struct macb *bp)
>                  bp->rx_frm_len_mask = MACB_RX_JFRMLEN_MASK;
> 
>          macb_configure_dma(bp);
> +
> +       /* Enable RX partial store and forward and set watermark */
> +       if (bp->rx_watermark)
> +               gem_writel(bp, PBUFRXCUT, (bp->rx_watermark | GEM_BIT(ENCUTTHRU)));
>   }
> 
>   /* The hash address register is 64 bits long and takes up two
> @@ -4923,6 +4930,7 @@ static int macb_probe(struct platform_device *pdev)
>          phy_interface_t interface;
>          struct net_device *dev;
>          struct resource *regs;
> +       u32 wtrmrk_rst_val;
>          void __iomem *mem;
>          struct macb *bp;
>          int err, val;
> @@ -4995,6 +5003,25 @@ static int macb_probe(struct platform_device *pdev)
> 
>          bp->usrio = macb_config->usrio;
> 
> +       /* By default we set to partial store and forward mode for zynqmp.
> +        * Disable if not set in devicetree.
> +        */
> +       if (GEM_BFEXT(PBUF_CUTTHRU, gem_readl(bp, DCFG6))) {
> +               err = of_property_read_u32(bp->pdev->dev.of_node,
> +                                          "cdns,rx-watermark",
> +                                          &bp->rx_watermark);
> +
> +               if (!err) {
> +                       /* Disable partial store and forward in case of error or
> +                        * invalid watermark value
> +                        */
> +                       wtrmrk_rst_val = (1 << (GEM_BFEXT(RX_PBUF_ADDR, gem_readl(bp, DCFG2)))) - 1;
> +                       if (bp->rx_watermark > wtrmrk_rst_val || !bp->rx_watermark) {
> +                               dev_info(&bp->pdev->dev, "Invalid watermark value\n");
> +                               bp->rx_watermark = 0;
> +                       }
> +               }
> +       }
>          spin_lock_init(&bp->lock);
> 
>          /* setup capabilities */
> --
> 2.36.1
> 

-- 
Nicolas Ferre

Re: [PATCH next-next v4 0/2] Add support for partial store and forward

[patchwork-bot+netdevbpf]

Hello:

This series was applied to netdev/net-next.git (main)
by David S. Miller <davem@davemloft.net>:

On Mon, 12 Jun 2023 23:43:38 -0600 you wrote:
> Add support for partial store and forward mode in Cadence MACB.
> 
> Link for v1:
> https://lore.kernel.org/all/20221213121245.13981-1-pranavi.somisetty@amd.com/
> 
> Changes v2:
> 1. Removed all the changes related to validating FCS when Rx checksum
> offload is disabled.
> 2. Instead of using a platform dependent number (0xFFF) for the reset
> value of rx watermark, derive it from designcfg_debug2 register.
> 3. Added a check to see if partial s/f is supported, by reading the
> designcfg_debug6 register.
> 4. Added devicetree bindings for "rx-watermark" property.
> Link for v2:
> https://lore.kernel.org/all/20230511071214.18611-1-pranavi.somisetty@amd.com/
> 
> [...]

Here is the summary with links:
  - [net-next,v4,1/2] dt-bindings: net: cdns,macb: Add rx-watermark property
    https://git.kernel.org/netdev/net-next/c/5b32c61a2dac
  - [net-next,v4,2/2] net: macb: Add support for partial store and forward
    https://git.kernel.org/netdev/net-next/c/cae4bc06b3e4

You are awesome, thank you!
-- 
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