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[78.88.45.245]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-a9b307b5375sm99385966b.155.2024.10.25.12.24.46 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Fri, 25 Oct 2024 12:24:49 -0700 (PDT) Message-ID: <5fe37609-ed58-4617-bd5f-90edc90f5d8b@oss.qualcomm.com> Date: Fri, 25 Oct 2024 21:24:46 +0200 Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v1 3/4] arm64: dts: qcom: qcs615: add UFS node To: Xin Liu , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Manivannan Sadhasivam , Bjorn Andersson , Konrad Dybcio Cc: Vinod Koul , Kishon Vijay Abraham I , Alim Akhtar , Avri Altman , Bart Van Assche , Andy Gross , linux-arm-msm@vger.kernel.org, linux-phy@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-scsi@vger.kernel.org, quic_jiegan@quicinc.com, quic_aiquny@quicinc.com, quic_tingweiz@quicinc.com, quic_sayalil@quicinc.com References: <20241017042300.872963-1-quic_liuxin@quicinc.com> <20241017042300.872963-4-quic_liuxin@quicinc.com> Content-Language: en-US From: Konrad Dybcio In-Reply-To: <20241017042300.872963-4-quic_liuxin@quicinc.com> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit X-Proofpoint-GUID: AVonWI9sdNuyNBTkarMq86oLLGQnxvyA X-Proofpoint-ORIG-GUID: AVonWI9sdNuyNBTkarMq86oLLGQnxvyA X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.680,FMLib:17.12.60.29 definitions=2024-09-06_09,2024-09-06_01,2024-09-02_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 clxscore=1015 mlxscore=0 lowpriorityscore=0 phishscore=0 adultscore=0 mlxlogscore=999 priorityscore=1501 impostorscore=0 bulkscore=0 spamscore=0 malwarescore=0 suspectscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2409260000 definitions=main-2410250149 On 17.10.2024 6:22 AM, Xin Liu wrote: > From: Sayali Lokhande > > Add the UFS Host Controller node and its PHY for QCS615 SoC. > > Signed-off-by: Sayali Lokhande > Co-developed-by: Xin Liu > Signed-off-by: Xin Liu > --- + Taniya (see below) > arch/arm64/boot/dts/qcom/qcs615.dtsi | 74 ++++++++++++++++++++++++++++ > 1 file changed, 74 insertions(+) > > diff --git a/arch/arm64/boot/dts/qcom/qcs615.dtsi b/arch/arm64/boot/dts/qcom/qcs615.dtsi > index fcba83fca7cf..689418466dc2 100644 > --- a/arch/arm64/boot/dts/qcom/qcs615.dtsi > +++ b/arch/arm64/boot/dts/qcom/qcs615.dtsi > @@ -458,6 +458,80 @@ mmss_noc: interconnect@1740000 { > qcom,bcm-voters = <&apps_bcm_voter>; > }; > > + ufs_mem_hc: ufs@1d84000 { ufshc@ would be consistent with other files in dts/qcom > + compatible = "qcom,qcs615-ufshc", "qcom,ufshc", "jedec,ufs-2.0"; > + reg = <0x0 0x01d84000 0x0 0x3000>, <0x0 0x01d90000 0x0 0x8000>; > + reg-names = "std", "ice"; One per line, please > + interrupts = ; > + phys = <&ufs_mem_phy>; > + phy-names = "ufsphy"; > + lanes-per-direction = <1>; > + #reset-cells = <1>; > + resets = <&gcc GCC_UFS_PHY_BCR>; > + reset-names = "rst"; > + > + power-domains = <&gcc UFS_PHY_GDSC>; > + required-opps = <&rpmhpd_opp_nom>; > + > + iommus = <&apps_smmu 0x300 0x0>; > + dma-coherent; > + > + interconnects = <&aggre1_noc MASTER_UFS_MEM QCOM_ICC_TAG_ALWAYS > + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, > + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS > + &config_noc SLAVE_UFS_MEM_CFG QCOM_ICC_TAG_ALWAYS>; > + interconnect-names = "ufs-ddr", > + "cpu-ufs"; > + > + clocks = <&gcc GCC_UFS_PHY_AXI_CLK>, > + <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>, > + <&gcc GCC_UFS_PHY_AHB_CLK>, > + <&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>, > + <&rpmhcc RPMH_CXO_CLK>, > + <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>, > + <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>, > + <&gcc GCC_UFS_PHY_ICE_CORE_CLK>; > + clock-names = "core_clk", > + "bus_aggr_clk", > + "iface_clk", > + "core_clk_unipro", > + "ref_clk", > + "tx_lane0_sync_clk", > + "rx_lane0_sync_clk", > + "ice_core_clk"; > + freq-table-hz = <50000000 200000000>, > + <0 0>, > + <0 0>, > + <37500000 150000000>, > + <0 0>, > + <0 0>, > + <0 0>, > + <75000000 300000000>; Please try to match the order of properties present in sm8650.dtsi And please use an OPP table instead of freq-table-hz (see sm8*5*50.dtsi) > + > + status = "disabled"; > + }; > + > + ufs_mem_phy: phy@1d87000 { > + compatible = "qcom,qcs615-qmp-ufs-phy", "qcom,sm6115-qmp-ufs-phy"; > + reg = <0x0 0x01d87000 0x0 0xe00>; This register region is a bit longer > + clocks = <&rpmhcc RPMH_CXO_CLK>, > + <&gcc GCC_UFS_PHY_PHY_AUX_CLK>, > + <&gcc GCC_UFS_MEM_CLKREF_CLK>; > + clock-names = "ref", > + "ref_aux", > + "qref"; > + > + power-domains = <&gcc UFS_PHY_GDSC>; > + > + resets = <&ufs_mem_hc 0>; > + reset-names = "ufsphy"; > + > + #clock-cells = <1>; The PHY is a clock provider. Normally, it's a parent of gcc_ufs_phy_[rt]x_symbol_n clocks. Taniya, could you please wire that up in your patchset? Konrad