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[78.88.45.245]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-ac7196dcf14sm216078866b.156.2025.03.28.14.53.20 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Fri, 28 Mar 2025 14:53:22 -0700 (PDT) Message-ID: <5fece4ac-2899-4e7d-8205-3b1ebba4b56b@oss.qualcomm.com> Date: Fri, 28 Mar 2025 22:53:19 +0100 Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v8 4/4] PCI: dwc: Add support for configuring lane equalization presets To: Manivannan Sadhasivam , Krishna Chaitanya Chundru Cc: Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Bjorn Helgaas , Jingoo Han , Lorenzo Pieralisi , =?UTF-8?Q?Krzysztof_Wilczy=C5=84ski?= , linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-pci@vger.kernel.org, quic_mrana@quicinc.com, quic_vbadigan@quicinc.com References: <20250316-preset_v6-v8-0-0703a78cb355@oss.qualcomm.com> <20250316-preset_v6-v8-4-0703a78cb355@oss.qualcomm.com> <3sbflmznjfqpcja52v6bso74vhouv7ncuikrba5zlb74tqqb5u@ovndmib3kgqf> <92c4854d-033e-c7b5-ca92-cf44a1a8c0cc@oss.qualcomm.com> Content-Language: en-US From: Konrad Dybcio In-Reply-To: Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit X-Authority-Analysis: v=2.4 cv=aZRhnQot c=1 sm=1 tr=0 ts=67e71a54 cx=c_pps a=HLyN3IcIa5EE8TELMZ618Q==:117 a=FpWmc02/iXfjRdCD7H54yg==:17 a=IkcTkHD0fZMA:10 a=Vs1iUdzkB0EA:10 a=EUspDBNiAAAA:8 a=DNeSK06HdlTfY3YWmTgA:9 a=QEXdDO2ut3YA:10 a=bTQJ7kPSJx9SKPbeHEYW:22 X-Proofpoint-GUID: scDyLFeEAxHHaTo4Uah5POQOj0iFTTgV X-Proofpoint-ORIG-GUID: scDyLFeEAxHHaTo4Uah5POQOj0iFTTgV X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1095,Hydra:6.0.680,FMLib:17.12.68.34 definitions=2025-03-28_10,2025-03-27_02,2024-11-22_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 lowpriorityscore=0 clxscore=1015 bulkscore=0 mlxlogscore=999 suspectscore=0 spamscore=0 mlxscore=0 phishscore=0 malwarescore=0 impostorscore=0 adultscore=0 priorityscore=1501 classifier=spam authscore=0 authtc=n/a authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2502280000 definitions=main-2503280145 On 3/28/25 7:45 AM, Manivannan Sadhasivam wrote: > On Fri, Mar 28, 2025 at 11:04:11AM +0530, Krishna Chaitanya Chundru wrote: >> >> >> On 3/28/2025 10:23 AM, Manivannan Sadhasivam wrote: >>> On Sun, Mar 16, 2025 at 09:39:04AM +0530, Krishna Chaitanya Chundru wrote: >>>> PCIe equalization presets are predefined settings used to optimize >>>> signal integrity by compensating for signal loss and distortion in >>>> high-speed data transmission. >>>> >>>> Based upon the number of lanes and the data rate supported, write >>>> the preset data read from the device tree in to the lane equalization >>>> control registers. >>>> >>>> Signed-off-by: Krishna Chaitanya Chundru >>>> --- >>>> drivers/pci/controller/dwc/pcie-designware-host.c | 60 +++++++++++++++++++++++ >>>> drivers/pci/controller/dwc/pcie-designware.h | 3 ++ >>>> include/uapi/linux/pci_regs.h | 3 ++ >>>> 3 files changed, 66 insertions(+) >>>> >>>> diff --git a/drivers/pci/controller/dwc/pcie-designware-host.c b/drivers/pci/controller/dwc/pcie-designware-host.c >>>> index dd56cc02f4ef..7c6e6a74383b 100644 >>>> --- a/drivers/pci/controller/dwc/pcie-designware-host.c >>>> +++ b/drivers/pci/controller/dwc/pcie-designware-host.c >>>> @@ -507,6 +507,10 @@ int dw_pcie_host_init(struct dw_pcie_rp *pp) >>>> if (pci->num_lanes < 1) >>>> pci->num_lanes = dw_pcie_link_get_max_link_width(pci); >>>> + ret = of_pci_get_equalization_presets(dev, &pp->presets, pci->num_lanes); >>>> + if (ret) >>>> + goto err_free_msi; >>>> + >>>> /* >>>> * Allocate the resource for MSG TLP before programming the iATU >>>> * outbound window in dw_pcie_setup_rc(). Since the allocation depends >>>> @@ -808,6 +812,61 @@ static int dw_pcie_iatu_setup(struct dw_pcie_rp *pp) >>>> return 0; >>>> } >>>> +static void dw_pcie_program_presets(struct dw_pcie_rp *pp, enum pci_bus_speed speed) >>>> +{ >>>> + struct dw_pcie *pci = to_dw_pcie_from_pp(pp); >>>> + u8 lane_eq_offset, lane_reg_size, cap_id; >>>> + u8 *presets; >>>> + u32 cap; >>>> + int i; >>>> + >>>> + if (speed == PCIE_SPEED_8_0GT) { >>>> + presets = (u8 *)pp->presets.eq_presets_8gts; >>>> + lane_eq_offset = PCI_SECPCI_LE_CTRL; >>>> + cap_id = PCI_EXT_CAP_ID_SECPCI; >>>> + /* For data rate of 8 GT/S each lane equalization control is 16bits wide*/ >>>> + lane_reg_size = 0x2; >>>> + } else if (speed == PCIE_SPEED_16_0GT) { >>>> + presets = pp->presets.eq_presets_Ngts[EQ_PRESET_TYPE_16GTS - 1]; >>>> + lane_eq_offset = PCI_PL_16GT_LE_CTRL; >>>> + cap_id = PCI_EXT_CAP_ID_PL_16GT; >>>> + lane_reg_size = 0x1; >>>> + } else { >>> >>> Can you add conditions for other data rates also? Like 32, 64 GT/s. If >>> controller supports them and if the presets property is defined in DT, then you >>> should apply the preset values. >>> >>> If the presets property is not present in DT, then below 'PCI_EQ_RESV' will >>> safely return. >>> >> I am fine to add it, but there is no GEN5 or GEN6 controller support >> added in dwc, isn't it best to add when that support is added and >> tested. >> > > What is the guarantee that this part of the code will be updated once the > capable controllers start showing up? I don't think there will be any issue in > writing to these registers. Let's not make assumptions about the spec of a cross-vendor mass-deployed IP Konrad