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[188.155.176.92]) by smtp.gmail.com with ESMTPSA id w14-20020a1709060a0e00b006f01e581668sm8019551ejf.209.2022.04.28.02.25.43 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Thu, 28 Apr 2022 02:25:43 -0700 (PDT) Message-ID: <5ff66242-31a6-113d-d49a-091b82b42a37@linaro.org> Date: Thu, 28 Apr 2022 11:25:42 +0200 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:91.0) Gecko/20100101 Thunderbird/91.7.0 Subject: Re: [PATCH 01/11] dt-bindings: iommu: arm,smmu-v3: make PRI IRQ optional Content-Language: en-US To: Robin Murphy , Andre Przywara , Rob Herring , Krzysztof Kozlowski Cc: Liviu Dudau , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Will Deacon , iommu@lists.linux-foundation.org References: <20220427112528.4097815-1-andre.przywara@arm.com> <20220427112528.4097815-2-andre.przywara@arm.com> <4d37f41c-4463-73e4-7271-8d191e9953af@linaro.org> <7c5d39b2-7016-b6c6-ae88-b0f4a517f255@arm.com> From: Krzysztof Kozlowski In-Reply-To: <7c5d39b2-7016-b6c6-ae88-b0f4a517f255@arm.com> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org On 28/04/2022 11:23, Robin Murphy wrote: > On 2022-04-28 07:56, Krzysztof Kozlowski wrote: >> On 27/04/2022 13:25, Andre Przywara wrote: >>> The Page Request Interface (PRI) is an optional PCIe feature. As such, a >>> SMMU would not need to handle it if the PCIe host bridge or the SMMU >>> itself do not implement it. Also an SMMU could be connected to a platform >>> device, without any PRI functionality whatsoever. >>> In all cases there would be no SMMU PRI queue interrupt to be wired up >>> to an interrupt controller. >>> >>> Relax the binding to allow specifying three interrupts, omitting the PRI >>> IRQ. At the moment, with the "eventq,gerror,priq,cmdq-sync" order, we >>> would need to sacrifice the command queue sync interrupt as well, which >>> might not be desired. >>> The Linux driver does not care about any order at all, just picks IRQs >>> based on their names, and treats all (wired) IRQs as optional. >> >> The last sentence is not a good explanation for the bindings. They are >> not about Linux and are used in other projects as well. >> >>> >>> Signed-off-by: Andre Przywara >>> --- >>> .../bindings/iommu/arm,smmu-v3.yaml | 21 ++++++++++++++----- >>> 1 file changed, 16 insertions(+), 5 deletions(-) >>> >>> diff --git a/Documentation/devicetree/bindings/iommu/arm,smmu-v3.yaml b/Documentation/devicetree/bindings/iommu/arm,smmu-v3.yaml >>> index e87bfbcc69135..6b3111f1f06ce 100644 >>> --- a/Documentation/devicetree/bindings/iommu/arm,smmu-v3.yaml >>> +++ b/Documentation/devicetree/bindings/iommu/arm,smmu-v3.yaml >>> @@ -37,12 +37,23 @@ properties: >>> hardware supports just a single, combined interrupt line. >>> If provided, then the combined interrupt will be used in preference to >>> any others. >>> - - minItems: 2 >>> + - minItems: 1 >>> items: >>> - - const: eventq # Event Queue not empty >>> - - const: gerror # Global Error activated >>> - - const: priq # PRI Queue not empty >>> - - const: cmdq-sync # CMD_SYNC complete >>> + - enum: >>> + - eventq # Event Queue not empty >>> + - gerror # Global Error activated >>> + - cmdq-sync # CMD_SYNC complete >>> + - priq # PRI Queue not empty >>> + - enum: >>> + - gerror >>> + - cmdq-sync >>> + - priq >>> + - enum: >>> + - cmdq-sync >>> + - priq >>> + - enum: >>> + - cmdq-sync >>> + - priq >> >> The order should be strict, so if you want the first interrupt optional, >> then: >> oneOf: >> - items: >> ... 4 items list >> - items >> ... 3 items list > > All 4 interrupts are optional, though, since any of them could > potentially use an MSI instead. Do we really want to list out all 15 > combinations? Bah, I missed that part from commit msg. It's fine then. Best regards, Krzysztof