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[86.58.6.171]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-391253b3e23sm1792217f8f.76.2025.03.05.09.50.35 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 05 Mar 2025 09:50:36 -0800 (PST) From: Jernej =?UTF-8?B?xaBrcmFiZWM=?= To: Linus Walleij , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Chen-Yu Tsai , Samuel Holland , Andre Przywara Cc: linux-gpio@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-sunxi@lists.linux.dev, linux-kernel@vger.kernel.org Subject: Re: [PATCH v3 4/8] pinctrl: sunxi: support moved power configuration registers Date: Wed, 05 Mar 2025 18:50:34 +0100 Message-ID: <6028746.MhkbZ0Pkbq@jernej-laptop> In-Reply-To: <20250227231447.20161-5-andre.przywara@arm.com> References: <20250227231447.20161-1-andre.przywara@arm.com> <20250227231447.20161-5-andre.przywara@arm.com> Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Dne petek, 28. februar 2025 ob 00:14:43 Srednjeevropski standardni =C4=8Das= je Andre Przywara napisal(a): > The Allwinner pincontroller IP features some registers to control the > withstand voltage of each pin group. So far those registers were always > located at the same offset, but the A523 SoC has moved them (probably to > accommodate all eleven pin banks). >=20 > Add a flag to note this feature, and use that to program the registers > either at offset 0x340 or 0x380. So far no pincontroller driver uses > this flag, but we need it for the upcoming A523 support. >=20 > Signed-off-by: Andre Przywara > --- > drivers/pinctrl/sunxi/pinctrl-sunxi.c | 15 +++++++++++---- > drivers/pinctrl/sunxi/pinctrl-sunxi.h | 7 +++++-- > 2 files changed, 16 insertions(+), 6 deletions(-) >=20 > diff --git a/drivers/pinctrl/sunxi/pinctrl-sunxi.c b/drivers/pinctrl/sunx= i/pinctrl-sunxi.c > index 83a031ceb29f2..fc12e6f807e4d 100644 > --- a/drivers/pinctrl/sunxi/pinctrl-sunxi.c > +++ b/drivers/pinctrl/sunxi/pinctrl-sunxi.c > @@ -736,9 +736,9 @@ static int sunxi_pinctrl_set_io_bias_cfg(struct sunxi= _pinctrl *pctl, > val =3D uV > 1800000 && uV <=3D 2500000 ? BIT(bank) : 0; > =20 > raw_spin_lock_irqsave(&pctl->lock, flags); > - reg =3D readl(pctl->membase + PIO_POW_MOD_CTL_REG); > + reg =3D readl(pctl->membase + pctl->pow_mod_sel_offset); > reg &=3D ~BIT(bank); > - writel(reg | val, pctl->membase + PIO_POW_MOD_CTL_REG); > + writel(reg | val, pctl->membase + pctl->pow_mod_sel_offset); These two are missing "+ PIO_POW_MOD_CTL_OFS" right? > raw_spin_unlock_irqrestore(&pctl->lock, flags); > =20 > fallthrough; > @@ -746,9 +746,12 @@ static int sunxi_pinctrl_set_io_bias_cfg(struct sunx= i_pinctrl *pctl, > val =3D uV <=3D 1800000 ? 1 : 0; > =20 > raw_spin_lock_irqsave(&pctl->lock, flags); > - reg =3D readl(pctl->membase + PIO_POW_MOD_SEL_REG); > + reg =3D readl(pctl->membase + pctl->pow_mod_sel_offset + > + PIO_POW_MOD_CTL_OFS); > reg &=3D ~(1 << bank); > - writel(reg | val << bank, pctl->membase + PIO_POW_MOD_SEL_REG); > + writel(reg | val << bank, > + pctl->membase + pctl->pow_mod_sel_offset + > + PIO_POW_MOD_CTL_OFS); And these two have "+ PIO_POW_MOD_CTL_OFS" too much, right? Best regards, Jernej > raw_spin_unlock_irqrestore(&pctl->lock, flags); > return 0; > default: > @@ -1520,6 +1523,10 @@ int sunxi_pinctrl_init_with_flags(struct platform_= device *pdev, > pctl->pull_regs_offset =3D PULL_REGS_OFFSET; > pctl->dlevel_field_width =3D DLEVEL_FIELD_WIDTH; > } > + if (flags & SUNXI_PINCTRL_ELEVEN_BANKS) > + pctl->pow_mod_sel_offset =3D PIO_11B_POW_MOD_SEL_REG; > + else > + pctl->pow_mod_sel_offset =3D PIO_POW_MOD_SEL_REG; > =20 > pctl->irq_array =3D devm_kcalloc(&pdev->dev, > IRQ_PER_BANK * pctl->desc->irq_banks, > diff --git a/drivers/pinctrl/sunxi/pinctrl-sunxi.h b/drivers/pinctrl/sunx= i/pinctrl-sunxi.h > index 6cf721876d89d..742fc795c7664 100644 > --- a/drivers/pinctrl/sunxi/pinctrl-sunxi.h > +++ b/drivers/pinctrl/sunxi/pinctrl-sunxi.h > @@ -87,9 +87,11 @@ > #define SUNXI_PINCTRL_VARIANT_MASK GENMASK(7, 0) > #define SUNXI_PINCTRL_NEW_REG_LAYOUT BIT(8) > #define SUNXI_PINCTRL_PORTF_SWITCH BIT(9) > +#define SUNXI_PINCTRL_ELEVEN_BANKS BIT(10) > =20 > -#define PIO_POW_MOD_SEL_REG 0x340 > -#define PIO_POW_MOD_CTL_REG 0x344 > +#define PIO_POW_MOD_SEL_REG 0x340 > +#define PIO_11B_POW_MOD_SEL_REG 0x380 > +#define PIO_POW_MOD_CTL_OFS 0x004 > =20 > #define PIO_BANK_K_OFFSET 0x500 > =20 > @@ -173,6 +175,7 @@ struct sunxi_pinctrl { > u32 bank_mem_size; > u32 pull_regs_offset; > u32 dlevel_field_width; > + u32 pow_mod_sel_offset; > }; > =20 > #define SUNXI_PIN(_pin, ...) \ >=20