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Tue, 23 Jul 2024 22:56:38 +0000 (GMT) Received: from nalasex01a.na.qualcomm.com (nalasex01a.na.qualcomm.com [10.47.209.196]) by NALASPPMTA02.qualcomm.com (8.17.1.19/8.17.1.19) with ESMTPS id 46NMuawk032209 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Tue, 23 Jul 2024 22:56:36 GMT Received: from [10.110.63.227] (10.80.80.8) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.9; Tue, 23 Jul 2024 15:56:35 -0700 Message-ID: <6038632d-92ec-4034-bc68-add9d47f2bad@quicinc.com> Date: Tue, 23 Jul 2024 15:56:35 -0700 Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH V2 7/7] PCI: host-generic: Add dwc PCIe controller based MSI controller usage From: Mayank Rana To: Rob Herring , Will Deacon CC: , , , , , , , , , , , , , , , , , , , , , , , , , , , References: <1721067215-5832-1-git-send-email-quic_mrana@quicinc.com> <1721067215-5832-8-git-send-email-quic_mrana@quicinc.com> <20240716085811.GA19348@willie-the-truck> <20240716134210.GA3534018-robh@kernel.org> <9b6eac04-f377-4afa-8712-ab916f831bba@quicinc.com> Content-Language: en-US In-Reply-To: <9b6eac04-f377-4afa-8712-ab916f831bba@quicinc.com> Content-Type: text/plain; charset="UTF-8"; format=flowed Content-Transfer-Encoding: 8bit X-ClientProxiedBy: nasanex01a.na.qualcomm.com (10.52.223.231) To nalasex01a.na.qualcomm.com (10.47.209.196) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: yMIb1vZTjHzgrE0Sw94Z46179o6FJvrl X-Proofpoint-ORIG-GUID: yMIb1vZTjHzgrE0Sw94Z46179o6FJvrl X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.680,FMLib:17.12.28.16 definitions=2024-07-23_15,2024-07-23_02,2024-05-17_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 phishscore=0 suspectscore=0 mlxlogscore=999 adultscore=0 bulkscore=0 mlxscore=0 spamscore=0 priorityscore=1501 lowpriorityscore=0 clxscore=1015 malwarescore=0 impostorscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2407110000 definitions=main-2407230160 Hi Rob On 7/16/2024 3:32 PM, Mayank Rana wrote: > Hi Will and Rob > > Thank you for your quick review comments. > > On 7/16/2024 6:42 AM, Rob Herring wrote: >> On Tue, Jul 16, 2024 at 09:58:12AM +0100, Will Deacon wrote: >>> On Mon, Jul 15, 2024 at 11:13:35AM -0700, Mayank Rana wrote: >>>> Add usage of Synopsys Designware PCIe controller based MSI >>>> controller to >>>> support MSI functionality with ECAM compliant Synopsys Designware PCIe >>>> controller. To use this functionality add device compatible string as >>>> "snps,dw-pcie-ecam-msi". >>>> >>>> Signed-off-by: Mayank Rana >>>> --- >>>>   drivers/pci/controller/pci-host-generic.c | 92 >>>> ++++++++++++++++++++++++++++++- >>>>   1 file changed, 91 insertions(+), 1 deletion(-) >>>> >>>> diff --git a/drivers/pci/controller/pci-host-generic.c >>>> b/drivers/pci/controller/pci-host-generic.c >>>> index c2c027f..457ae44 100644 >>>> --- a/drivers/pci/controller/pci-host-generic.c >>>> +++ b/drivers/pci/controller/pci-host-generic.c >>>> @@ -8,13 +8,73 @@ >>>>    * Author: Will Deacon >>>>    */ >>>> -#include >>>>   #include >>>> +#include >>>>   #include >>>> +#include >>>>   #include >>>>   #include >>>>   #include >>>> +#include "dwc/pcie-designware-msi.h" >>>> + >>>> +struct dw_ecam_pcie { >>>> +    void __iomem *cfg; >>>> +    struct dw_msi *msi; >>>> +    struct pci_host_bridge *bridge; >>>> +}; >>>> + >>>> +static u32 dw_ecam_pcie_readl(void *p_data, u32 reg) >>>> +{ >>>> +    struct dw_ecam_pcie *ecam_pcie = (struct dw_ecam_pcie *)p_data; >>>> + >>>> +    return readl(ecam_pcie->cfg + reg); >>>> +} >>>> + >>>> +static void dw_ecam_pcie_writel(void *p_data, u32 reg, u32 val) >>>> +{ >>>> +    struct dw_ecam_pcie *ecam_pcie = (struct dw_ecam_pcie *)p_data; >>>> + >>>> +    writel(val, ecam_pcie->cfg + reg); >>>> +} >>>> + >>>> +static struct dw_ecam_pcie *dw_pcie_ecam_msi(struct platform_device >>>> *pdev) >>>> +{ >>>> +    struct device *dev = &pdev->dev; >>>> +    struct dw_ecam_pcie *ecam_pcie; >>>> +    struct dw_msi_ops *msi_ops; >>>> +    u64 addr; >>>> + >>>> +    ecam_pcie = devm_kzalloc(dev, sizeof(*ecam_pcie), GFP_KERNEL); >>>> +    if (!ecam_pcie) >>>> +        return ERR_PTR(-ENOMEM); >>>> + >>>> +    if (of_property_read_reg(dev->of_node, 0, &addr, NULL) < 0) { >> >> Using this function on MMIO addresses is wrong. It is an untranslated >> address. > ok. do you prefer me to use of_address_to_resource() instead here ? > >>>> +        dev_err(dev, "Failed to get reg address\n"); >>>> +        return ERR_PTR(-ENODEV); >>>> +    } >>>> + >>>> +    ecam_pcie->cfg = devm_ioremap(dev, addr, PAGE_SIZE); >>>> +    if (ecam_pcie->cfg == NULL) >>>> +        return ERR_PTR(-ENOMEM); >>>> + >>>> +    msi_ops = devm_kzalloc(dev, sizeof(*msi_ops), GFP_KERNEL); >>>> +    if (!msi_ops) >>>> +        return ERR_PTR(-ENOMEM); >>>> + >>>> +    msi_ops->readl_msi = dw_ecam_pcie_readl; >>>> +    msi_ops->writel_msi = dw_ecam_pcie_writel; >>>> +    msi_ops->pp = ecam_pcie; >>>> +    ecam_pcie->msi = dw_pcie_msi_host_init(pdev, msi_ops, 0); >>>> +    if (IS_ERR(ecam_pcie->msi)) { >>>> +        dev_err(dev, "dw_pcie_msi_host_init() failed\n"); >>>> +        return ERR_PTR(-EINVAL); >>>> +    } >>>> + >>>> +    dw_pcie_msi_init(ecam_pcie->msi); >>>> +    return ecam_pcie; >>>> +} >>> >>> Hmm. This looks like quite a lot of not-very-generic code to be adding >>> to pci-host-generic.c. The file is now, what, 50% designware logic? >> >> Agreed. >> >> I would suggest you add ECAM support to the DW/QCom driver reusing some >> of the common ECAM support code. > I can try although there is very limited reusage of code with > pcie-qcom.c and pcie-designware-host.c except reusing MSI functionality. > That would make more new OPs within pcie-designware-host.c and > pcie-qcom.c just to perform few operation. As now MSI functionality is > available outside pcie core designware driver (although those changes > are under review), will you be ok to allow separate Qualcomm PCIe ECAM > driver as previously submitted RFC as > https://lore.kernel.org/all/d10199df-5fb3-407b-b404-a0a4d067341f@quicinc.com/T/ > > I can modify above ECAM driver to call into PCIe designware module based > MSI ops as doing here and that would allow reusing of MSI functionality > at same time allowing separate driver for handling firmware VM based > implementation. Can you consider above request to have separate driver here ? Please suggest on this. >> >> I suppose another option would be to define a node and driver which is >> just the DW MSI controller. That might not work given the power domain >> being added (which is not very generic either). > yes, I did consider this approach, and haven't used this due to concern > as you mentioned, and also that ask for modifying devicetree usage for > existing user of PCIe Designware controller based MSI controller. > > Regards, > Mayank >