From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 65F1C1B78F3; Mon, 23 Feb 2026 07:25:18 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1771831518; cv=none; b=CWDcI/7XYEO58yY2wjyIuZK5/EUOA8V2RXGdJdF2tjmDYVM97K/AIC/ryO002IhWTmAnli/LkTKxbl/U+cNNuKIGLzPUT68d9pfgDENp3JLjtrlDRFxdHwjV1gltvv817rL8hMM/FWJvKlm4NS5zkb9qfcmDR6Wt7yPa2ZSK6pU= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1771831518; c=relaxed/simple; bh=B/JSg3mmxUxtQY5FEWXW+Zfs41VnSj6TnKcjeLeK4vE=; h=Message-ID:Date:MIME-Version:Subject:To:Cc:References:From: In-Reply-To:Content-Type; b=HtZIBCUsFY5W4rS327HreVkm2b60LpP8dd81eglgGlNoxQDx5u1fK9ZRVtVjKdKoPYylV1J0shN0/OTNFS4Kwd43zE7G4sCjGM3k82Fai6rsVI9TP4/V6cXqtFviw6cWAWVzlCYQHPq2DOPbF9S7CU0LrO17f6oHXeOS33yyo7c= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=RFeBtOap; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="RFeBtOap" Received: by smtp.kernel.org (Postfix) with ESMTPSA id EB650C116C6; Mon, 23 Feb 2026 07:25:13 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1771831518; bh=B/JSg3mmxUxtQY5FEWXW+Zfs41VnSj6TnKcjeLeK4vE=; h=Date:Subject:To:Cc:References:From:In-Reply-To:From; b=RFeBtOapPTJX/nDxRHbivHpIM5zWXH9mfUmFxXDS9HLyNRoKkzGbLq2qpyyRhaipw jb5KqSkPtXo63lSOYa6Sjr5z6OfVh42In8EBX8MtbnwCOI5+dExlRwhZ2gEAfF8KkT r5vQBV4kHYE8Icxc3Eb8rLHiqCFLJR7m77iALicUSYoNffgWGr6n5AzUBS3oQ3N0I8 TrIXlE6ZpPVL1O5wuoucYNy0XePo0CiOyb5LtSpyaioxfCrFWaYeZVI/k/KNzOwVNM kI3YArCgapRB8aM+utSrkjPgYylS7KWg9m2COYc4V+Bq0qVXHCNyvfHTDLY4KdtAj/ Yo3PnaF4bj4UA== Message-ID: <6048d1cc-5e64-4f5d-be72-ff3feae5232e@kernel.org> Date: Mon, 23 Feb 2026 08:25:12 +0100 Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v8 3/4] arm64: dts: qcom: Introduce Glymur base dtsi To: Pankaj Patil , Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Raviteja Laggyshetty , Jyothi Kumar Seerapu , Maulik Shah , Sibi Sankar , Taniya Das , Kamal Wadhwa , Qiang Yu , Manaf Meethalavalappu Pallikunhi , Jishnu Prakash , Konrad Dybcio , Abel Vesa References: <20260219-upstream_v3_glymur_introduction-v8-0-8ce4e489ebb6@oss.qualcomm.com> <20260219-upstream_v3_glymur_introduction-v8-3-8ce4e489ebb6@oss.qualcomm.com> From: Krzysztof Kozlowski Content-Language: en-US Autocrypt: addr=krzk@kernel.org; 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charset=UTF-8 Content-Transfer-Encoding: 8bit On 19/02/2026 14:23, Pankaj Patil wrote: > Introduce the base device tree support for Glymur – Qualcomm's > next-generation compute SoC. The new glymur.dtsi describes the core SoC > components, including: > > - CPUs and CPU topology > - Interrupt controller and TLMM > - GCC,DISPCC and RPMHCC clock controllers > - Reserved memory and interconnects > - APPS and PCIe SMMU and firmware SCM > - Watchdog, RPMHPD, APPS RSC and SRAM > - PSCI and PMU nodes > - QUPv3 serial engines > - CPU power domains and idle states, plus SCMI/ SRAM pieces for CPU DVFS > - PDP0 mailbox, IPCC and AOSS > - Display clock controller > - SPMI PMIC arbiter with SPMI0/1/2 buses > - SMP2P nodes > - TSENS and thermal zones (8 instances, 92 sensors) > > Add dtsi files for PMH0101, PMK8850, PMCX0102, SMB2370, PMH0104, > PMH0110, PMIC's along with temp-alarm and GPIO nodes needed on Glymur > > Enabled PCIe controllers and associated PHY to support boot to > shell with nvme storage, > List of PCIe instances enabled: > > - PCIe3b > - PCIe4 > - PCIe5 > - PCIe6 > > Co-developed-by: Raviteja Laggyshetty > Signed-off-by: Raviteja Laggyshetty > Co-developed-by: Jyothi Kumar Seerapu > Signed-off-by: Jyothi Kumar Seerapu > Co-developed-by: Maulik Shah > Signed-off-by: Maulik Shah > Co-developed-by: Sibi Sankar > Signed-off-by: Sibi Sankar > Co-developed-by: Taniya Das > Signed-off-by: Taniya Das > Co-developed-by: Kamal Wadhwa > Signed-off-by: Kamal Wadhwa > Co-developed-by: Qiang Yu > Signed-off-by: Qiang Yu > Co-developed-by: Abel Vesa > Signed-off-by: Abel Vesa > Co-developed-by: Manaf Meethalavalappu Pallikunhi > Signed-off-by: Manaf Meethalavalappu Pallikunhi > Co-developed-by: Jishnu Prakash > Signed-off-by: Jishnu Prakash > Reviewed-by: Konrad Dybcio > Signed-off-by: Pankaj Patil > --- > arch/arm64/boot/dts/qcom/glymur.dtsi | 5913 ++++++++++++++++++++++++++ > arch/arm64/boot/dts/qcom/pmcx0102.dtsi | 187 + > arch/arm64/boot/dts/qcom/pmh0101.dtsi | 68 + > arch/arm64/boot/dts/qcom/pmh0104-glymur.dtsi | 144 + > arch/arm64/boot/dts/qcom/pmh0110-glymur.dtsi | 144 + > arch/arm64/boot/dts/qcom/pmk8850.dtsi | 70 + > arch/arm64/boot/dts/qcom/smb2370.dtsi | 45 + > 7 files changed, 6571 insertions(+) > > diff --git a/arch/arm64/boot/dts/qcom/glymur.dtsi b/arch/arm64/boot/dts/qcom/glymur.dtsi > new file mode 100644 > index 000000000000..e269cec7942c > --- /dev/null > +++ b/arch/arm64/boot/dts/qcom/glymur.dtsi > @@ -0,0 +1,5913 @@ > +// SPDX-License-Identifier: BSD-3-Clause > +/* > + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. > + */ > + > +#include > +#include > +#include > +#include > +#include > +#include > +#include > +#include > +#include > +#include > +#include > +#include > +#include > +#include > +#include > +#include > + > +#include "glymur-ipcc.h" > + > +/ { > + interrupt-parent = <&intc>; > + #address-cells = <2>; > + #size-cells = <2>; > + > + cpus { > + #address-cells = <2>; > + #size-cells = <0>; > + > + cpu0: cpu@0 { > + device_type = "cpu"; > + compatible = "qcom,oryon"; This is an incorrect compatible. We had extensive talks offlist and we reached consensus, so I do not understand why you are not implementing it. Also, this was already discussed and ACCEPTED as deprecated. you cannot use deprecated compatibles. Best regards, Krzysztof