[PATCH 0/9] PCI: rockchip: Cleanups against v10

[PATCH 0/9] PCI: rockchip: Cleanups against v10

[Bjorn Helgaas]

These are cleanups against 2098142ae87d, the current pci/host-rockchip
head in my tree.  This is basically the v10 driver posting (it's not
identical because I had already tweaked a few things and squashed in
Brian's bug fix).

These haven't been compiled so I'm sure the 0-day builder will find some
errors.  After fixing those, I intend to squash everything into one commit,
since this driver hasn't been merged yet.  I'm just posting these split out
patches in case anybody wants to review them.

These address most of Guenter's review comments.  I didn't change anything
related to -EPROBE_DEFER because it wasn't obvious to me what to do.

I also made several other changes -- mostly renaming functions and
variables so they're more consistent with other PCI host drivers.

These are in git as pci/host-rockchip-wip.

---

Bjorn Helgaas (9):
      Remove unused symbols, unnecessary parens, other minor comments from
      Rename pcie_read() and pcie_write() to rockchip_pcie_read() and
      Always use "rockchip" as the pointer to per-device struct.
      Rename struct rockchip_pcie_port to struct rockchip_pcie.
      Use a local "dev" to avoid repetition of "rockchip->dev".
      Add comment about why 32-bit read/modify/write isn't safe.
      Simplify the confusing HIWORD_UPDATE scheme.
      Simplify testing of link status and speed testing.
      Move msleeps to address Guenter's comments.


 drivers/pci/host/pcie-rockchip.c |  680 +++++++++++++++++---------------------
 1 file changed, 307 insertions(+), 373 deletions(-)

[PATCH 1/9] Remove unused symbols, unnecessary parens, other minor comments from

[Bjorn Helgaas]

Guenter.
---
 drivers/pci/host/pcie-rockchip.c |   69 ++++++++++++--------------------------
 1 file changed, 21 insertions(+), 48 deletions(-)

diff --git a/drivers/pci/host/pcie-rockchip.c b/drivers/pci/host/pcie-rockchip.c
index e77aec3..a7006be 100644
--- a/drivers/pci/host/pcie-rockchip.c
+++ b/drivers/pci/host/pcie-rockchip.c
@@ -38,7 +38,6 @@
 #include <linux/regmap.h>
 
 #define PCIE_CLIENT_BASE			0x0
-#define PCIE_RC_CONFIG_NORMAL_BASE		0x800000
 #define PCIE_RC_CONFIG_BASE			0xa00000
 #define PCIE_RC_CONFIG_L1_SUBSTATE_CTRL2	0x90c
 #define PCIE_RC_CONFIG_LCSR			0xd0
@@ -126,9 +125,6 @@
 #define RC_REGION_0_ADDR_TRANS_H		0x00000000
 #define RC_REGION_0_ADDR_TRANS_L		0x00000000
 #define RC_REGION_0_PASS_BITS			(25 - 1)
-#define RC_REGION_1_ADDR_TRANS_H		0x00000000
-#define RC_REGION_1_ADDR_TRANS_L		0x00400000
-#define RC_REGION_1_PASS_BITS			(20 - 1)
 #define MAX_AXI_WRAPPER_REGION_NUM		33
 #define PCIE_CORE_LCSR_RETRAIN_LINK		BIT(5)
 #define PCIE_CLIENT_CONF_ENABLE			BIT(0)
@@ -147,15 +143,12 @@
 #define PCIE_CLIENT_MODE_SHIFT			6
 #define PCIE_CLIENT_MODE_MASK			0x1
 #define PCIE_CLIENT_GEN_SEL_2			1
-#define PCIE_CLIENT_GEN_SEL_1			0
 #define PCIE_CLIENT_GEN_SEL_SHIFT		7
 #define PCIE_CLIENT_GEN_SEL_MASK		0x1
 #define PCIE_CLIENT_LINK_STATUS_UP		0x3
 #define PCIE_CLIENT_LINK_STATUS_SHIFT		20
 #define PCIE_CLIENT_LINK_STATUS_MASK		0x3
-#define PCIE_CORE_PL_CONF_SPEED_2_5G		0x0
 #define PCIE_CORE_PL_CONF_SPEED_5G		0x1
-#define PCIE_CORE_PL_CONF_SPEED_8G		0x2
 #define PCIE_CORE_PL_CONF_SPEED_SHIFT		3
 #define PCIE_CORE_PL_CONF_SPEED_MASK		0x3
 #define PCIE_CORE_PL_CONF_LANE_SHIFT		1
@@ -174,11 +167,6 @@
 		 PCIE_CORE_INT_CT | PCIE_CORE_INT_UTC | \
 		 PCIE_CORE_INT_MMVC)
 
-#define PCIE_CLIENT_INT_SUBSYSTEM \
-	(PCIE_CLIENT_INT_PWR_STCG | PCIE_CLIENT_INT_HOT_PLUG | \
-	PCIE_CLIENT_INT_PHY | PCIE_CLIENT_INT_UDMA | \
-	PCIE_CLIENT_INT_LOCAL)
-
 #define PCIE_CLIENT_INT_LEGACY \
 	(PCIE_CLIENT_INT_INTA | PCIE_CLIENT_INT_INTB | \
 	PCIE_CLIENT_INT_INTC | PCIE_CLIENT_INT_INTD)
@@ -191,8 +179,8 @@
 	PCIE_CLIENT_INT_PHY)
 
 struct rockchip_pcie_port {
-	void	__iomem *reg_base;
-	void	__iomem *apb_base;
+	void	__iomem *reg_base;		/* DT axi-base */
+	void	__iomem *apb_base;		/* DT apb-base */
 	struct	phy *phy;
 	struct	reset_control *core_rst;
 	struct	reset_control *mgmt_rst;
@@ -240,7 +228,7 @@ static void rockchip_pcie_clr_bw_int(struct rockchip_pcie_port *port)
 	pcie_write(port, status, PCIE_RC_CONFIG_BASE + PCIE_RC_CONFIG_LCSR);
 }
 
-static int rockchip_pcie_valid_config(struct rockchip_pcie_port *pp,
+static int rockchip_pcie_valid_device(struct rockchip_pcie_port *pp,
 				      struct pci_bus *bus, int dev)
 {
 	/* access only one slot on each root port */
@@ -286,7 +274,7 @@ static int rockchip_pcie_wr_own_conf(struct rockchip_pcie_port *pp,
 {
 	u32 mask, tmp, offset;
 
-	offset = (where & (~0x3));
+	offset = where & ~0x3;
 
 	if (size == 4) {
 		writel(val, pp->apb_base + PCIE_RC_CONFIG_BASE + offset);
@@ -357,7 +345,7 @@ static int rockchip_pcie_rd_conf(struct pci_bus *bus, u32 devfn, int where,
 {
 	struct rockchip_pcie_port *pp = bus->sysdata;
 
-	if (!rockchip_pcie_valid_config(pp, bus, PCI_SLOT(devfn))) {
+	if (!rockchip_pcie_valid_device(pp, bus, PCI_SLOT(devfn))) {
 		*val = 0xffffffff;
 		return PCIBIOS_DEVICE_NOT_FOUND;
 	}
@@ -366,7 +354,6 @@ static int rockchip_pcie_rd_conf(struct pci_bus *bus, u32 devfn, int where,
 		return rockchip_pcie_rd_own_conf(pp, where, size, val);
 
 	return rockchip_pcie_rd_other_conf(pp, bus, devfn, where, size, val);
-
 }
 
 static int rockchip_pcie_wr_conf(struct pci_bus *bus, u32 devfn,
@@ -374,7 +361,7 @@ static int rockchip_pcie_wr_conf(struct pci_bus *bus, u32 devfn,
 {
 	struct rockchip_pcie_port *pp = bus->sysdata;
 
-	if (!rockchip_pcie_valid_config(pp, bus, PCI_SLOT(devfn)))
+	if (!rockchip_pcie_valid_device(pp, bus, PCI_SLOT(devfn)))
 		return PCIBIOS_DEVICE_NOT_FOUND;
 
 	if (bus->number == pp->root_bus_nr)
@@ -516,7 +503,6 @@ static int rockchip_pcie_init_port(struct rockchip_pcie_port *port)
 			err = -ETIMEDOUT;
 			break;
 		}
-
 	}
 
 	/* Double check gen1 training */
@@ -744,11 +730,6 @@ static int rockchip_pcie_parse_dt(struct rockchip_pcie_port *port)
 	regs = platform_get_resource_byname(pdev,
 					    IORESOURCE_MEM,
 					    "axi-base");
-	if (!regs) {
-		dev_err(dev, "missing axi-base property\n");
-		return -ENODEV;
-	}
-
 	port->reg_base = devm_ioremap_resource(dev, regs);
 	if (IS_ERR(port->reg_base))
 		return PTR_ERR(port->reg_base);
@@ -756,11 +737,6 @@ static int rockchip_pcie_parse_dt(struct rockchip_pcie_port *port)
 	regs = platform_get_resource_byname(pdev,
 					    IORESOURCE_MEM,
 					    "apb-base");
-	if (!regs) {
-		dev_err(dev, "missing apb-base property\n");
-		return -ENODEV;
-	}
-
 	port->apb_base = devm_ioremap_resource(dev, regs);
 	if (IS_ERR(port->apb_base))
 		return PTR_ERR(port->apb_base);
@@ -774,38 +750,38 @@ static int rockchip_pcie_parse_dt(struct rockchip_pcie_port *port)
 
 	port->lanes = 1;
 	err = of_property_read_u32(node, "num-lanes", &port->lanes);
-	if (!err && ((port->lanes == 0) ||
-		     (port->lanes == 3) ||
-		     (port->lanes > 4))) {
-		dev_warn(dev, "invalid num-lanes, default use one lane\n");
+	if (!err && (port->lanes == 0 ||
+		     port->lanes == 3 ||
+		     port->lanes > 4)) {
+		dev_warn(dev, "invalid num-lanes, default to use one lane\n");
 		port->lanes = 1;
 	}
 
 	port->core_rst = devm_reset_control_get(dev, "core");
 	if (IS_ERR(port->core_rst)) {
 		if (PTR_ERR(port->core_rst) != -EPROBE_DEFER)
-			dev_err(dev, "missing core rst property in node\n");
+			dev_err(dev, "missing core reset property in node\n");
 		return PTR_ERR(port->core_rst);
 	}
 
 	port->mgmt_rst = devm_reset_control_get(dev, "mgmt");
 	if (IS_ERR(port->mgmt_rst)) {
 		if (PTR_ERR(port->mgmt_rst) != -EPROBE_DEFER)
-			dev_err(dev, "missing mgmt rst property in node\n");
+			dev_err(dev, "missing mgmt reset property in node\n");
 		return PTR_ERR(port->mgmt_rst);
 	}
 
 	port->mgmt_sticky_rst = devm_reset_control_get(dev, "mgmt-sticky");
 	if (IS_ERR(port->mgmt_sticky_rst)) {
 		if (PTR_ERR(port->mgmt_sticky_rst) != -EPROBE_DEFER)
-			dev_err(dev, "missing mgmt-sticky rst property in node\n");
+			dev_err(dev, "missing mgmt-sticky reset property in node\n");
 		return PTR_ERR(port->mgmt_sticky_rst);
 	}
 
 	port->pipe_rst = devm_reset_control_get(dev, "pipe");
 	if (IS_ERR(port->pipe_rst)) {
 		if (PTR_ERR(port->pipe_rst) != -EPROBE_DEFER)
-			dev_err(dev, "missing pipe rst property in node\n");
+			dev_err(dev, "missing pipe reset property in node\n");
 		return PTR_ERR(port->pipe_rst);
 	}
 
@@ -991,7 +967,7 @@ static int rockchip_pcie_prog_ob_atu(struct rockchip_pcie_port *pp,
 
 	if (region_no >= MAX_AXI_WRAPPER_REGION_NUM)
 		return -EINVAL;
-	if ((num_pass_bits + 1) < 8)
+	if (num_pass_bits + 1 < 8)
 		return -EINVAL;
 	if (num_pass_bits > 63)
 		return -EINVAL;
@@ -1030,7 +1006,7 @@ static int rockchip_pcie_prog_ib_atu(struct rockchip_pcie_port *pp,
 
 	if (region_no > MAX_AXI_IB_ROOTPORT_REGION_NUM)
 		return -EINVAL;
-	if ((num_pass_bits + 1) < MIN_AXI_ADDR_BITS_PASSED)
+	if (num_pass_bits + 1 < MIN_AXI_ADDR_BITS_PASSED)
 		return -EINVAL;
 	if (num_pass_bits > 63)
 		return -EINVAL;
@@ -1055,7 +1031,6 @@ static int rockchip_pcie_probe(struct platform_device *pdev)
 	struct pci_bus *bus, *child;
 	struct resource_entry *win;
 	resource_size_t io_base;
-	struct resource	*busn = NULL;
 	struct resource	*mem;
 	struct resource	*io;
 	phys_addr_t io_bus_addr = 0;
@@ -1154,14 +1129,14 @@ static int rockchip_pcie_probe(struct platform_device *pdev)
 			mem_bus_addr = mem->start - win->offset;
 			break;
 		case IORESOURCE_BUS:
-			busn = win->res;
+			port->root_bus_nr = win->res->start;
 			break;
 		default:
 			continue;
 		}
 	}
 
-	if (mem_size)
+	if (mem_size) {
 		for (reg_no = 0; reg_no < (mem_size >> 20); reg_no++) {
 			err = rockchip_pcie_prog_ob_atu(port, reg_no + 1,
 							AXI_WRAPPER_MEM_WRITE,
@@ -1174,6 +1149,7 @@ static int rockchip_pcie_probe(struct platform_device *pdev)
 				goto err_vpcie;
 			}
 		}
+	}
 
 	err = rockchip_pcie_prog_ib_atu(port, 2, 32 - 1, 0x0, 0);
 	if (err) {
@@ -1183,7 +1159,7 @@ static int rockchip_pcie_probe(struct platform_device *pdev)
 
 	offset = mem_size >> 20;
 
-	if (io_size)
+	if (io_size) {
 		for (reg_no = 0; reg_no < (io_size >> 20); reg_no++) {
 			err = rockchip_pcie_prog_ob_atu(port,
 							reg_no + 1 + offset,
@@ -1197,12 +1173,9 @@ static int rockchip_pcie_probe(struct platform_device *pdev)
 				goto err_vpcie;
 			}
 		}
-
-	if (busn)
-		port->root_bus_nr = busn->start;
+	}
 
 	bus = pci_scan_root_bus(&pdev->dev, 0, &rockchip_pcie_ops, port, &res);
-
 	if (!bus) {
 		err = -ENOMEM;
 		goto err_vpcie;

[PATCH 2/9] Rename pcie_read() and pcie_write() to rockchip_pcie_read() and

[Bjorn Helgaas]

rockchip_pcie_write().
---
 drivers/pci/host/pcie-rockchip.c |   66 +++++++++++++++++++-------------------
 1 file changed, 33 insertions(+), 33 deletions(-)

diff --git a/drivers/pci/host/pcie-rockchip.c b/drivers/pci/host/pcie-rockchip.c
index a7006be..c9d0799 100644
--- a/drivers/pci/host/pcie-rockchip.c
+++ b/drivers/pci/host/pcie-rockchip.c
@@ -200,12 +200,12 @@ struct rockchip_pcie_port {
 	struct	irq_domain *irq_domain;
 };
 
-static inline u32 pcie_read(struct rockchip_pcie_port *port, u32 reg)
+static u32 rockchip_pcie_read(struct rockchip_pcie_port *port, u32 reg)
 {
 	return readl(port->apb_base + reg);
 }
 
-static inline void pcie_write(struct rockchip_pcie_port *port, u32 val, u32 reg)
+static void rockchip_pcie_write(struct rockchip_pcie_port *port, u32 val, u32 reg)
 {
 	writel(val, port->apb_base + reg);
 }
@@ -214,18 +214,18 @@ static void rockchip_pcie_enable_bw_int(struct rockchip_pcie_port *port)
 {
 	u32 status;
 
-	status = pcie_read(port, PCIE_RC_CONFIG_BASE + PCIE_RC_CONFIG_LCSR);
+	status = rockchip_pcie_read(port, PCIE_RC_CONFIG_BASE + PCIE_RC_CONFIG_LCSR);
 	status |= (PCIE_RC_CONFIG_LCSR_LBMIE | PCIE_RC_CONFIG_LCSR_LABIE);
-	pcie_write(port, status, PCIE_RC_CONFIG_BASE + PCIE_RC_CONFIG_LCSR);
+	rockchip_pcie_write(port, status, PCIE_RC_CONFIG_BASE + PCIE_RC_CONFIG_LCSR);
 }
 
 static void rockchip_pcie_clr_bw_int(struct rockchip_pcie_port *port)
 {
 	u32 status;
 
-	status = pcie_read(port, PCIE_RC_CONFIG_BASE + PCIE_RC_CONFIG_LCSR);
+	status = rockchip_pcie_read(port, PCIE_RC_CONFIG_BASE + PCIE_RC_CONFIG_LCSR);
 	status |= (PCIE_RC_CONFIG_LCSR_LBMS | PCIE_RC_CONFIG_LCSR_LAMS);
-	pcie_write(port, status, PCIE_RC_CONFIG_BASE + PCIE_RC_CONFIG_LCSR);
+	rockchip_pcie_write(port, status, PCIE_RC_CONFIG_BASE + PCIE_RC_CONFIG_LCSR);
 }
 
 static int rockchip_pcie_valid_device(struct rockchip_pcie_port *pp,
@@ -417,7 +417,7 @@ static int rockchip_pcie_init_port(struct rockchip_pcie_port *port)
 		return err;
 	}
 
-	pcie_write(port,
+	rockchip_pcie_write(port,
 		   HIWORD_UPDATE(PCIE_CLIENT_CONF_ENABLE,
 				 PCIE_CLIENT_CONF_ENABLE_MASK,
 				 PCIE_CLIENT_CONF_ENABLE_SHIFT) |
@@ -471,13 +471,13 @@ static int rockchip_pcie_init_port(struct rockchip_pcie_port *port)
 	 * reliable and enabling ASPM doesn't work.  This is a controller
 	 * bug we need to work around.
 	 */
-	status = pcie_read(port, PCIE_RC_CONFIG_BASE +
+	status = rockchip_pcie_read(port, PCIE_RC_CONFIG_BASE +
 				 PCIE_RC_CONFIG_L1_SUBSTATE_CTRL2);
-	pcie_write(port, status, PCIE_RC_CONFIG_BASE +
+	rockchip_pcie_write(port, status, PCIE_RC_CONFIG_BASE +
 				 PCIE_RC_CONFIG_L1_SUBSTATE_CTRL2);
 
 	/* Enable Gen1 training */
-	pcie_write(port,
+	rockchip_pcie_write(port,
 		   HIWORD_UPDATE(PCIE_CLIENT_LINK_TRAIN_ENABLE,
 				 PCIE_CLIENT_LINK_TRAIN_MASK,
 				 PCIE_CLIENT_LINK_TRAIN_SHIFT),
@@ -489,7 +489,7 @@ static int rockchip_pcie_init_port(struct rockchip_pcie_port *port)
 	timeout = jiffies + msecs_to_jiffies(500);
 
 	for (;;) {
-		status = pcie_read(port, PCIE_CLIENT_BASIC_STATUS1);
+		status = rockchip_pcie_read(port, PCIE_CLIENT_BASIC_STATUS1);
 		if (((status >> PCIE_CLIENT_LINK_STATUS_SHIFT) &
 		      PCIE_CLIENT_LINK_STATUS_MASK) ==
 		      PCIE_CLIENT_LINK_STATUS_UP) {
@@ -507,7 +507,7 @@ static int rockchip_pcie_init_port(struct rockchip_pcie_port *port)
 
 	/* Double check gen1 training */
 	if (err) {
-		status = pcie_read(port, PCIE_CLIENT_BASIC_STATUS1);
+		status = rockchip_pcie_read(port, PCIE_CLIENT_BASIC_STATUS1);
 		err = (((status >> PCIE_CLIENT_LINK_STATUS_SHIFT) &
 			PCIE_CLIENT_LINK_STATUS_MASK) ==
 			PCIE_CLIENT_LINK_STATUS_UP) ? 0 : -ETIMEDOUT;
@@ -521,15 +521,15 @@ static int rockchip_pcie_init_port(struct rockchip_pcie_port *port)
 	 * Enable retrain for gen2. This should be configured only after
 	 * gen1 finished.
 	 */
-	status = pcie_read(port,
+	status = rockchip_pcie_read(port,
 			   PCIE_RC_CONFIG_LCS + PCIE_RC_CONFIG_BASE);
 	status |= PCIE_CORE_LCSR_RETRAIN_LINK;
-	pcie_write(port, status,
+	rockchip_pcie_write(port, status,
 		   PCIE_RC_CONFIG_LCS + PCIE_RC_CONFIG_BASE);
 
 	timeout = jiffies + msecs_to_jiffies(500);
 	for (;;) {
-		status = pcie_read(port, PCIE_CORE_CTRL_MGMT_BASE);
+		status = rockchip_pcie_read(port, PCIE_CORE_CTRL_MGMT_BASE);
 		if (((status >> PCIE_CORE_PL_CONF_SPEED_SHIFT) &
 		     PCIE_CORE_PL_CONF_SPEED_MASK) ==
 		     PCIE_CORE_PL_CONF_SPEED_5G) {
@@ -547,7 +547,7 @@ static int rockchip_pcie_init_port(struct rockchip_pcie_port *port)
 
 	/* Double check gen2 training */
 	if (err) {
-		status = pcie_read(port, PCIE_CORE_CTRL_MGMT_BASE);
+		status = rockchip_pcie_read(port, PCIE_CORE_CTRL_MGMT_BASE);
 		err = (((status >> PCIE_CORE_PL_CONF_SPEED_SHIFT) &
 			PCIE_CORE_PL_CONF_SPEED_MASK) ==
 			PCIE_CORE_PL_CONF_SPEED_5G) ? 0 : -ETIMEDOUT;
@@ -556,23 +556,23 @@ static int rockchip_pcie_init_port(struct rockchip_pcie_port *port)
 	}
 
 	/* Check the final link width from negotiated lane counter from MGMT */
-	status = pcie_read(port, PCIE_CORE_CTRL_MGMT_BASE);
+	status = rockchip_pcie_read(port, PCIE_CORE_CTRL_MGMT_BASE);
 	status =  0x1 << ((status >> PCIE_CORE_PL_CONF_LANE_SHIFT) &
 			   PCIE_CORE_PL_CONF_LANE_MASK);
 	dev_dbg(port->dev, "current link width is x%d\n", status);
 
-	pcie_write(port, ROCKCHIP_VENDOR_ID, PCIE_RC_CONFIG_BASE);
-	pcie_write(port, PCI_CLASS_BRIDGE_PCI << PCIE_CORE_RC_CONF_SCC_SHIFT,
+	rockchip_pcie_write(port, ROCKCHIP_VENDOR_ID, PCIE_RC_CONFIG_BASE);
+	rockchip_pcie_write(port, PCI_CLASS_BRIDGE_PCI << PCIE_CORE_RC_CONF_SCC_SHIFT,
 		   PCIE_RC_CONFIG_BASE + PCIE_RC_CONFIG_RID_CCR);
-	pcie_write(port, 0x0, PCIE_CORE_CTRL_MGMT_BASE + PCIE_RC_BAR_CONF);
+	rockchip_pcie_write(port, 0x0, PCIE_CORE_CTRL_MGMT_BASE + PCIE_RC_BAR_CONF);
 
-	pcie_write(port, (RC_REGION_0_ADDR_TRANS_L + RC_REGION_0_PASS_BITS),
+	rockchip_pcie_write(port, (RC_REGION_0_ADDR_TRANS_L + RC_REGION_0_PASS_BITS),
 		   PCIE_CORE_AXI_CONF_BASE);
-	pcie_write(port, RC_REGION_0_ADDR_TRANS_H,
+	rockchip_pcie_write(port, RC_REGION_0_ADDR_TRANS_H,
 		   PCIE_CORE_AXI_CONF_BASE + PCIE_CORE_OB_REGION_ADDR1);
-	pcie_write(port, 0x0080000a,
+	rockchip_pcie_write(port, 0x0080000a,
 		   PCIE_CORE_AXI_CONF_BASE + PCIE_CORE_OB_REGION_DESC0);
-	pcie_write(port, 0x0,
+	rockchip_pcie_write(port, 0x0,
 		   PCIE_CORE_AXI_CONF_BASE + PCIE_CORE_OB_REGION_DESC1);
 
 	return 0;
@@ -584,10 +584,10 @@ static irqreturn_t rockchip_pcie_subsys_irq_handler(int irq, void *arg)
 	u32 reg;
 	u32 sub_reg;
 
-	reg = pcie_read(pp, PCIE_CLIENT_INT_STATUS);
+	reg = rockchip_pcie_read(pp, PCIE_CLIENT_INT_STATUS);
 	if (reg & PCIE_CLIENT_INT_LOCAL) {
 		dev_dbg(pp->dev, "local interrupt received\n");
-		sub_reg = pcie_read(pp, PCIE_CORE_INT_STATUS);
+		sub_reg = rockchip_pcie_read(pp, PCIE_CORE_INT_STATUS);
 		if (sub_reg & PCIE_CORE_INT_PRFPE)
 			dev_dbg(pp->dev, "parity error detected while reading from the PNP receive FIFO RAM\n");
 
@@ -630,13 +630,13 @@ static irqreturn_t rockchip_pcie_subsys_irq_handler(int irq, void *arg)
 		if (sub_reg & PCIE_CORE_INT_MMVC)
 			dev_dbg(pp->dev, "MSI mask register changes\n");
 
-		pcie_write(pp, sub_reg, PCIE_CORE_INT_STATUS);
+		rockchip_pcie_write(pp, sub_reg, PCIE_CORE_INT_STATUS);
 	} else if (reg & PCIE_CLIENT_INT_PHY) {
 		dev_dbg(pp->dev, "phy link changes\n");
 		rockchip_pcie_clr_bw_int(pp);
 	}
 
-	pcie_write(pp, reg & PCIE_CLIENT_INT_LOCAL, PCIE_CLIENT_INT_STATUS);
+	rockchip_pcie_write(pp, reg & PCIE_CLIENT_INT_LOCAL, PCIE_CLIENT_INT_STATUS);
 
 	return IRQ_HANDLED;
 }
@@ -646,7 +646,7 @@ static irqreturn_t rockchip_pcie_client_irq_handler(int irq, void *arg)
 	struct rockchip_pcie_port *pp = arg;
 	u32 reg;
 
-	reg = pcie_read(pp, PCIE_CLIENT_INT_STATUS);
+	reg = rockchip_pcie_read(pp, PCIE_CLIENT_INT_STATUS);
 	if (reg & PCIE_CLIENT_INT_LEGACY_DONE)
 		dev_dbg(pp->dev, "legacy done interrupt received\n");
 
@@ -671,7 +671,7 @@ static irqreturn_t rockchip_pcie_client_irq_handler(int irq, void *arg)
 	if (reg & PCIE_CLIENT_INT_PHY)
 		dev_dbg(pp->dev, "phy interrupt received\n");
 
-	pcie_write(pp, reg & (PCIE_CLIENT_INT_LEGACY_DONE |
+	rockchip_pcie_write(pp, reg & (PCIE_CLIENT_INT_LEGACY_DONE |
 			      PCIE_CLIENT_INT_MSG | PCIE_CLIENT_INT_HOT_RST |
 			      PCIE_CLIENT_INT_DPA | PCIE_CLIENT_INT_FATAL_ERR |
 			      PCIE_CLIENT_INT_NFATAL_ERR |
@@ -693,7 +693,7 @@ static void rockchip_pcie_legacy_int_handler(struct irq_desc *desc)
 	chained_irq_enter(chip, desc);
 	port = irq_desc_get_handler_data(desc);
 
-	reg = pcie_read(port, PCIE_CLIENT_INT_STATUS);
+	reg = rockchip_pcie_read(port, PCIE_CLIENT_INT_STATUS);
 	reg = (reg & ROCKCHIP_PCIE_RPIFR1_INTR_MASK) >>
 	       ROCKCHIP_PCIE_RPIFR1_INTR_SHIFT;
 
@@ -917,9 +917,9 @@ err_out:
 
 static void rockchip_pcie_enable_interrupts(struct rockchip_pcie_port *port)
 {
-	pcie_write(port, (PCIE_CLIENT_INT_CLI << 16) &
+	rockchip_pcie_write(port, (PCIE_CLIENT_INT_CLI << 16) &
 		   (~PCIE_CLIENT_INT_CLI), PCIE_CLIENT_INT_MASK);
-	pcie_write(port, (u32)(~PCIE_CORE_INT), PCIE_CORE_INT_MASK);
+	rockchip_pcie_write(port, (u32)(~PCIE_CORE_INT), PCIE_CORE_INT_MASK);
 
 	rockchip_pcie_enable_bw_int(port);
 }

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[PATCH 3/9] Always use "rockchip" as the pointer to per-device struct.

[Bjorn Helgaas]

---
 drivers/pci/host/pcie-rockchip.c |  488 +++++++++++++++++++-------------------
 1 file changed, 244 insertions(+), 244 deletions(-)

diff --git a/drivers/pci/host/pcie-rockchip.c b/drivers/pci/host/pcie-rockchip.c
index c9d0799..3cfb47a 100644
--- a/drivers/pci/host/pcie-rockchip.c
+++ b/drivers/pci/host/pcie-rockchip.c
@@ -200,56 +200,55 @@ struct rockchip_pcie_port {
 	struct	irq_domain *irq_domain;
 };
 
-static u32 rockchip_pcie_read(struct rockchip_pcie_port *port, u32 reg)
+static u32 rockchip_pcie_read(struct rockchip_pcie_port *rockchip, u32 reg)
 {
-	return readl(port->apb_base + reg);
+	return readl(rockchip->apb_base + reg);
 }
 
-static void rockchip_pcie_write(struct rockchip_pcie_port *port, u32 val, u32 reg)
+static void rockchip_pcie_write(struct rockchip_pcie_port *rockchip, u32 val, u32 reg)
 {
-	writel(val, port->apb_base + reg);
+	writel(val, rockchip->apb_base + reg);
 }
 
-static void rockchip_pcie_enable_bw_int(struct rockchip_pcie_port *port)
+static void rockchip_pcie_enable_bw_int(struct rockchip_pcie_port *rockchip)
 {
 	u32 status;
 
-	status = rockchip_pcie_read(port, PCIE_RC_CONFIG_BASE + PCIE_RC_CONFIG_LCSR);
+	status = rockchip_pcie_read(rockchip, PCIE_RC_CONFIG_BASE + PCIE_RC_CONFIG_LCSR);
 	status |= (PCIE_RC_CONFIG_LCSR_LBMIE | PCIE_RC_CONFIG_LCSR_LABIE);
-	rockchip_pcie_write(port, status, PCIE_RC_CONFIG_BASE + PCIE_RC_CONFIG_LCSR);
+	rockchip_pcie_write(rockchip, status, PCIE_RC_CONFIG_BASE + PCIE_RC_CONFIG_LCSR);
 }
 
-static void rockchip_pcie_clr_bw_int(struct rockchip_pcie_port *port)
+static void rockchip_pcie_clr_bw_int(struct rockchip_pcie_port *rockchip)
 {
 	u32 status;
 
-	status = rockchip_pcie_read(port, PCIE_RC_CONFIG_BASE + PCIE_RC_CONFIG_LCSR);
+	status = rockchip_pcie_read(rockchip, PCIE_RC_CONFIG_BASE + PCIE_RC_CONFIG_LCSR);
 	status |= (PCIE_RC_CONFIG_LCSR_LBMS | PCIE_RC_CONFIG_LCSR_LAMS);
-	rockchip_pcie_write(port, status, PCIE_RC_CONFIG_BASE + PCIE_RC_CONFIG_LCSR);
+	rockchip_pcie_write(rockchip, status, PCIE_RC_CONFIG_BASE + PCIE_RC_CONFIG_LCSR);
 }
 
-static int rockchip_pcie_valid_device(struct rockchip_pcie_port *pp,
+static int rockchip_pcie_valid_device(struct rockchip_pcie_port *rockchip,
 				      struct pci_bus *bus, int dev)
 {
 	/* access only one slot on each root port */
-	if (bus->number == pp->root_bus_nr && dev > 0)
+	if (bus->number == rockchip->root_bus_nr && dev > 0)
 		return 0;
 
 	/*
 	 * do not read more than one device on the bus directly attached
 	 * to RC's downstream side.
 	 */
-	if (bus->primary == pp->root_bus_nr && dev > 0)
+	if (bus->primary == rockchip->root_bus_nr && dev > 0)
 		return 0;
 
 	return 1;
 }
 
-static int rockchip_pcie_rd_own_conf(struct rockchip_pcie_port *pp,
-				     int where, int size,
-				     u32 *val)
+static int rockchip_pcie_rd_own_conf(struct rockchip_pcie_port *rockchip,
+				     int where, int size, u32 *val)
 {
-	void __iomem *addr = pp->apb_base + PCIE_RC_CONFIG_BASE + where;
+	void __iomem *addr = rockchip->apb_base + PCIE_RC_CONFIG_BASE + where;
 
 	if (!IS_ALIGNED((uintptr_t)addr, size)) {
 		*val = 0;
@@ -269,7 +268,7 @@ static int rockchip_pcie_rd_own_conf(struct rockchip_pcie_port *pp,
 	return PCIBIOS_SUCCESSFUL;
 }
 
-static int rockchip_pcie_wr_own_conf(struct rockchip_pcie_port *pp,
+static int rockchip_pcie_wr_own_conf(struct rockchip_pcie_port *rockchip,
 				     int where, int size, u32 val)
 {
 	u32 mask, tmp, offset;
@@ -277,20 +276,20 @@ static int rockchip_pcie_wr_own_conf(struct rockchip_pcie_port *pp,
 	offset = where & ~0x3;
 
 	if (size == 4) {
-		writel(val, pp->apb_base + PCIE_RC_CONFIG_BASE + offset);
+		writel(val, rockchip->apb_base + PCIE_RC_CONFIG_BASE + offset);
 		return PCIBIOS_SUCCESSFUL;
 	}
 
 	mask = ~(((1 << (size * 8)) - 1) << ((where & 0x3) * 8));
 
-	tmp = readl(pp->apb_base + PCIE_RC_CONFIG_BASE + offset) & mask;
+	tmp = readl(rockchip->apb_base + PCIE_RC_CONFIG_BASE + offset) & mask;
 	tmp |= val << ((where & 0x3) * 8);
-	writel(tmp, pp->apb_base + PCIE_RC_CONFIG_BASE + offset);
+	writel(tmp, rockchip->apb_base + PCIE_RC_CONFIG_BASE + offset);
 
 	return PCIBIOS_SUCCESSFUL;
 }
 
-static int rockchip_pcie_rd_other_conf(struct rockchip_pcie_port *pp,
+static int rockchip_pcie_rd_other_conf(struct rockchip_pcie_port *rockchip,
 				       struct pci_bus *bus, u32 devfn,
 				       int where, int size, u32 *val)
 {
@@ -305,11 +304,11 @@ static int rockchip_pcie_rd_other_conf(struct rockchip_pcie_port *pp,
 	}
 
 	if (size == 4) {
-		*val = readl(pp->reg_base + busdev);
+		*val = readl(rockchip->reg_base + busdev);
 	} else if (size == 2) {
-		*val = readw(pp->reg_base + busdev);
+		*val = readw(rockchip->reg_base + busdev);
 	} else if (size == 1) {
-		*val = readb(pp->reg_base + busdev);
+		*val = readb(rockchip->reg_base + busdev);
 	} else {
 		*val = 0;
 		return PCIBIOS_BAD_REGISTER_NUMBER;
@@ -317,7 +316,7 @@ static int rockchip_pcie_rd_other_conf(struct rockchip_pcie_port *pp,
 	return PCIBIOS_SUCCESSFUL;
 }
 
-static int rockchip_pcie_wr_other_conf(struct rockchip_pcie_port *pp,
+static int rockchip_pcie_wr_other_conf(struct rockchip_pcie_port *rockchip,
 				       struct pci_bus *bus, u32 devfn,
 				       int where, int size, u32 val)
 {
@@ -329,11 +328,11 @@ static int rockchip_pcie_wr_other_conf(struct rockchip_pcie_port *pp,
 		return PCIBIOS_BAD_REGISTER_NUMBER;
 
 	if (size == 4)
-		writel(val, pp->reg_base + busdev);
+		writel(val, rockchip->reg_base + busdev);
 	else if (size == 2)
-		writew(val, pp->reg_base + busdev);
+		writew(val, rockchip->reg_base + busdev);
 	else if (size == 1)
-		writeb(val, pp->reg_base + busdev);
+		writeb(val, rockchip->reg_base + busdev);
 	else
 		return PCIBIOS_BAD_REGISTER_NUMBER;
 
@@ -343,31 +342,31 @@ static int rockchip_pcie_wr_other_conf(struct rockchip_pcie_port *pp,
 static int rockchip_pcie_rd_conf(struct pci_bus *bus, u32 devfn, int where,
 				 int size, u32 *val)
 {
-	struct rockchip_pcie_port *pp = bus->sysdata;
+	struct rockchip_pcie_port *rockchip = bus->sysdata;
 
-	if (!rockchip_pcie_valid_device(pp, bus, PCI_SLOT(devfn))) {
+	if (!rockchip_pcie_valid_device(rockchip, bus, PCI_SLOT(devfn))) {
 		*val = 0xffffffff;
 		return PCIBIOS_DEVICE_NOT_FOUND;
 	}
 
-	if (bus->number == pp->root_bus_nr)
-		return rockchip_pcie_rd_own_conf(pp, where, size, val);
+	if (bus->number == rockchip->root_bus_nr)
+		return rockchip_pcie_rd_own_conf(rockchip, where, size, val);
 
-	return rockchip_pcie_rd_other_conf(pp, bus, devfn, where, size, val);
+	return rockchip_pcie_rd_other_conf(rockchip, bus, devfn, where, size, val);
 }
 
 static int rockchip_pcie_wr_conf(struct pci_bus *bus, u32 devfn,
 				 int where, int size, u32 val)
 {
-	struct rockchip_pcie_port *pp = bus->sysdata;
+	struct rockchip_pcie_port *rockchip = bus->sysdata;
 
-	if (!rockchip_pcie_valid_device(pp, bus, PCI_SLOT(devfn)))
+	if (!rockchip_pcie_valid_device(rockchip, bus, PCI_SLOT(devfn)))
 		return PCIBIOS_DEVICE_NOT_FOUND;
 
-	if (bus->number == pp->root_bus_nr)
-		return rockchip_pcie_wr_own_conf(pp, where, size, val);
+	if (bus->number == rockchip->root_bus_nr)
+		return rockchip_pcie_wr_own_conf(rockchip, where, size, val);
 
-	return rockchip_pcie_wr_other_conf(pp, bus, devfn, where, size, val);
+	return rockchip_pcie_wr_other_conf(rockchip, bus, devfn, where, size, val);
 }
 
 static struct pci_ops rockchip_pcie_ops = {
@@ -377,51 +376,51 @@ static struct pci_ops rockchip_pcie_ops = {
 
 /**
  * rockchip_pcie_init_port - Initialize hardware
- * @port: PCIe port information
+ * @rockchip: PCIe port information
  */
-static int rockchip_pcie_init_port(struct rockchip_pcie_port *port)
+static int rockchip_pcie_init_port(struct rockchip_pcie_port *rockchip)
 {
 	int err;
 	u32 status;
 	unsigned long timeout;
 
-	gpiod_set_value(port->ep_gpio, 0);
+	gpiod_set_value(rockchip->ep_gpio, 0);
 
-	err = phy_init(port->phy);
+	err = phy_init(rockchip->phy);
 	if (err < 0) {
-		dev_err(port->dev, "fail to init phy, err %d\n", err);
+		dev_err(rockchip->dev, "fail to init phy, err %d\n", err);
 		return err;
 	}
 
-	err = reset_control_assert(port->core_rst);
+	err = reset_control_assert(rockchip->core_rst);
 	if (err) {
-		dev_err(port->dev, "assert core_rst err %d\n", err);
+		dev_err(rockchip->dev, "assert core_rst err %d\n", err);
 		return err;
 	}
 
-	err = reset_control_assert(port->mgmt_rst);
+	err = reset_control_assert(rockchip->mgmt_rst);
 	if (err) {
-		dev_err(port->dev, "assert mgmt_rst err %d\n", err);
+		dev_err(rockchip->dev, "assert mgmt_rst err %d\n", err);
 		return err;
 	}
 
-	err = reset_control_assert(port->mgmt_sticky_rst);
+	err = reset_control_assert(rockchip->mgmt_sticky_rst);
 	if (err) {
-		dev_err(port->dev, "assert mgmt_sticky_rst err %d\n", err);
+		dev_err(rockchip->dev, "assert mgmt_sticky_rst err %d\n", err);
 		return err;
 	}
 
-	err = reset_control_assert(port->pipe_rst);
+	err = reset_control_assert(rockchip->pipe_rst);
 	if (err) {
-		dev_err(port->dev, "assert pipe_rst err %d\n", err);
+		dev_err(rockchip->dev, "assert pipe_rst err %d\n", err);
 		return err;
 	}
 
-	rockchip_pcie_write(port,
+	rockchip_pcie_write(rockchip,
 		   HIWORD_UPDATE(PCIE_CLIENT_CONF_ENABLE,
 				 PCIE_CLIENT_CONF_ENABLE_MASK,
 				 PCIE_CLIENT_CONF_ENABLE_SHIFT) |
-		   HIWORD_UPDATE(PCIE_CLIENT_CONF_LANE_NUM(port->lanes),
+		   HIWORD_UPDATE(PCIE_CLIENT_CONF_LANE_NUM(rockchip->lanes),
 				 PCIE_CLIENT_CONF_LANE_NUM_MASK,
 				 PCIE_CLIENT_CONF_LANE_NUM_SHIFT) |
 		   HIWORD_UPDATE(PCIE_CLIENT_MODE_RC,
@@ -435,33 +434,33 @@ static int rockchip_pcie_init_port(struct rockchip_pcie_port *port)
 				 PCIE_CLIENT_GEN_SEL_SHIFT),
 		   PCIE_CLIENT_BASE);
 
-	err = phy_power_on(port->phy);
+	err = phy_power_on(rockchip->phy);
 	if (err) {
-		dev_err(port->dev, "fail to power on phy, err %d\n", err);
+		dev_err(rockchip->dev, "fail to power on phy, err %d\n", err);
 		return err;
 	}
 
-	err = reset_control_deassert(port->core_rst);
+	err = reset_control_deassert(rockchip->core_rst);
 	if (err) {
-		dev_err(port->dev, "deassert core_rst err %d\n", err);
+		dev_err(rockchip->dev, "deassert core_rst err %d\n", err);
 		return err;
 	}
 
-	err = reset_control_deassert(port->mgmt_rst);
+	err = reset_control_deassert(rockchip->mgmt_rst);
 	if (err) {
-		dev_err(port->dev, "deassert mgmt_rst err %d\n", err);
+		dev_err(rockchip->dev, "deassert mgmt_rst err %d\n", err);
 		return err;
 	}
 
-	err = reset_control_deassert(port->mgmt_sticky_rst);
+	err = reset_control_deassert(rockchip->mgmt_sticky_rst);
 	if (err) {
-		dev_err(port->dev, "deassert mgmt_sticky_rst err %d\n", err);
+		dev_err(rockchip->dev, "deassert mgmt_sticky_rst err %d\n", err);
 		return err;
 	}
 
-	err = reset_control_deassert(port->pipe_rst);
+	err = reset_control_deassert(rockchip->pipe_rst);
 	if (err) {
-		dev_err(port->dev, "deassert pipe_rst err %d\n", err);
+		dev_err(rockchip->dev, "deassert pipe_rst err %d\n", err);
 		return err;
 	}
 
@@ -471,29 +470,29 @@ static int rockchip_pcie_init_port(struct rockchip_pcie_port *port)
 	 * reliable and enabling ASPM doesn't work.  This is a controller
 	 * bug we need to work around.
 	 */
-	status = rockchip_pcie_read(port, PCIE_RC_CONFIG_BASE +
+	status = rockchip_pcie_read(rockchip, PCIE_RC_CONFIG_BASE +
 				 PCIE_RC_CONFIG_L1_SUBSTATE_CTRL2);
-	rockchip_pcie_write(port, status, PCIE_RC_CONFIG_BASE +
+	rockchip_pcie_write(rockchip, status, PCIE_RC_CONFIG_BASE +
 				 PCIE_RC_CONFIG_L1_SUBSTATE_CTRL2);
 
 	/* Enable Gen1 training */
-	rockchip_pcie_write(port,
+	rockchip_pcie_write(rockchip,
 		   HIWORD_UPDATE(PCIE_CLIENT_LINK_TRAIN_ENABLE,
 				 PCIE_CLIENT_LINK_TRAIN_MASK,
 				 PCIE_CLIENT_LINK_TRAIN_SHIFT),
 		   PCIE_CLIENT_BASE);
 
-	gpiod_set_value(port->ep_gpio, 1);
+	gpiod_set_value(rockchip->ep_gpio, 1);
 
 	/* 500ms timeout value should be enough for Gen1/2 training */
 	timeout = jiffies + msecs_to_jiffies(500);
 
 	for (;;) {
-		status = rockchip_pcie_read(port, PCIE_CLIENT_BASIC_STATUS1);
+		status = rockchip_pcie_read(rockchip, PCIE_CLIENT_BASIC_STATUS1);
 		if (((status >> PCIE_CLIENT_LINK_STATUS_SHIFT) &
 		      PCIE_CLIENT_LINK_STATUS_MASK) ==
 		      PCIE_CLIENT_LINK_STATUS_UP) {
-			dev_dbg(port->dev, "PCIe link training gen1 pass!\n");
+			dev_dbg(rockchip->dev, "PCIe link training gen1 pass!\n");
 			break;
 		}
 
@@ -507,12 +506,12 @@ static int rockchip_pcie_init_port(struct rockchip_pcie_port *port)
 
 	/* Double check gen1 training */
 	if (err) {
-		status = rockchip_pcie_read(port, PCIE_CLIENT_BASIC_STATUS1);
+		status = rockchip_pcie_read(rockchip, PCIE_CLIENT_BASIC_STATUS1);
 		err = (((status >> PCIE_CLIENT_LINK_STATUS_SHIFT) &
 			PCIE_CLIENT_LINK_STATUS_MASK) ==
 			PCIE_CLIENT_LINK_STATUS_UP) ? 0 : -ETIMEDOUT;
 		if (err) {
-			dev_err(port->dev, "PCIe link training gen1 timeout!\n");
+			dev_err(rockchip->dev, "PCIe link training gen1 timeout!\n");
 			return err;
 		}
 	}
@@ -521,19 +520,19 @@ static int rockchip_pcie_init_port(struct rockchip_pcie_port *port)
 	 * Enable retrain for gen2. This should be configured only after
 	 * gen1 finished.
 	 */
-	status = rockchip_pcie_read(port,
+	status = rockchip_pcie_read(rockchip,
 			   PCIE_RC_CONFIG_LCS + PCIE_RC_CONFIG_BASE);
 	status |= PCIE_CORE_LCSR_RETRAIN_LINK;
-	rockchip_pcie_write(port, status,
+	rockchip_pcie_write(rockchip, status,
 		   PCIE_RC_CONFIG_LCS + PCIE_RC_CONFIG_BASE);
 
 	timeout = jiffies + msecs_to_jiffies(500);
 	for (;;) {
-		status = rockchip_pcie_read(port, PCIE_CORE_CTRL_MGMT_BASE);
+		status = rockchip_pcie_read(rockchip, PCIE_CORE_CTRL_MGMT_BASE);
 		if (((status >> PCIE_CORE_PL_CONF_SPEED_SHIFT) &
 		     PCIE_CORE_PL_CONF_SPEED_MASK) ==
 		     PCIE_CORE_PL_CONF_SPEED_5G) {
-			dev_dbg(port->dev, "PCIe link training gen2 pass!\n");
+			dev_dbg(rockchip->dev, "PCIe link training gen2 pass!\n");
 			break;
 		}
 
@@ -547,32 +546,32 @@ static int rockchip_pcie_init_port(struct rockchip_pcie_port *port)
 
 	/* Double check gen2 training */
 	if (err) {
-		status = rockchip_pcie_read(port, PCIE_CORE_CTRL_MGMT_BASE);
+		status = rockchip_pcie_read(rockchip, PCIE_CORE_CTRL_MGMT_BASE);
 		err = (((status >> PCIE_CORE_PL_CONF_SPEED_SHIFT) &
 			PCIE_CORE_PL_CONF_SPEED_MASK) ==
 			PCIE_CORE_PL_CONF_SPEED_5G) ? 0 : -ETIMEDOUT;
 		if (err)
-			dev_dbg(port->dev, "PCIe link training gen2 timeout, fall back to gen1!\n");
+			dev_dbg(rockchip->dev, "PCIe link training gen2 timeout, fall back to gen1!\n");
 	}
 
 	/* Check the final link width from negotiated lane counter from MGMT */
-	status = rockchip_pcie_read(port, PCIE_CORE_CTRL_MGMT_BASE);
+	status = rockchip_pcie_read(rockchip, PCIE_CORE_CTRL_MGMT_BASE);
 	status =  0x1 << ((status >> PCIE_CORE_PL_CONF_LANE_SHIFT) &
 			   PCIE_CORE_PL_CONF_LANE_MASK);
-	dev_dbg(port->dev, "current link width is x%d\n", status);
+	dev_dbg(rockchip->dev, "current link width is x%d\n", status);
 
-	rockchip_pcie_write(port, ROCKCHIP_VENDOR_ID, PCIE_RC_CONFIG_BASE);
-	rockchip_pcie_write(port, PCI_CLASS_BRIDGE_PCI << PCIE_CORE_RC_CONF_SCC_SHIFT,
+	rockchip_pcie_write(rockchip, ROCKCHIP_VENDOR_ID, PCIE_RC_CONFIG_BASE);
+	rockchip_pcie_write(rockchip, PCI_CLASS_BRIDGE_PCI << PCIE_CORE_RC_CONF_SCC_SHIFT,
 		   PCIE_RC_CONFIG_BASE + PCIE_RC_CONFIG_RID_CCR);
-	rockchip_pcie_write(port, 0x0, PCIE_CORE_CTRL_MGMT_BASE + PCIE_RC_BAR_CONF);
+	rockchip_pcie_write(rockchip, 0x0, PCIE_CORE_CTRL_MGMT_BASE + PCIE_RC_BAR_CONF);
 
-	rockchip_pcie_write(port, (RC_REGION_0_ADDR_TRANS_L + RC_REGION_0_PASS_BITS),
+	rockchip_pcie_write(rockchip, (RC_REGION_0_ADDR_TRANS_L + RC_REGION_0_PASS_BITS),
 		   PCIE_CORE_AXI_CONF_BASE);
-	rockchip_pcie_write(port, RC_REGION_0_ADDR_TRANS_H,
+	rockchip_pcie_write(rockchip, RC_REGION_0_ADDR_TRANS_H,
 		   PCIE_CORE_AXI_CONF_BASE + PCIE_CORE_OB_REGION_ADDR1);
-	rockchip_pcie_write(port, 0x0080000a,
+	rockchip_pcie_write(rockchip, 0x0080000a,
 		   PCIE_CORE_AXI_CONF_BASE + PCIE_CORE_OB_REGION_DESC0);
-	rockchip_pcie_write(port, 0x0,
+	rockchip_pcie_write(rockchip, 0x0,
 		   PCIE_CORE_AXI_CONF_BASE + PCIE_CORE_OB_REGION_DESC1);
 
 	return 0;
@@ -580,98 +579,98 @@ static int rockchip_pcie_init_port(struct rockchip_pcie_port *port)
 
 static irqreturn_t rockchip_pcie_subsys_irq_handler(int irq, void *arg)
 {
-	struct rockchip_pcie_port *pp = arg;
+	struct rockchip_pcie_port *rockchip = arg;
 	u32 reg;
 	u32 sub_reg;
 
-	reg = rockchip_pcie_read(pp, PCIE_CLIENT_INT_STATUS);
+	reg = rockchip_pcie_read(rockchip, PCIE_CLIENT_INT_STATUS);
 	if (reg & PCIE_CLIENT_INT_LOCAL) {
-		dev_dbg(pp->dev, "local interrupt received\n");
-		sub_reg = rockchip_pcie_read(pp, PCIE_CORE_INT_STATUS);
+		dev_dbg(rockchip->dev, "local interrupt received\n");
+		sub_reg = rockchip_pcie_read(rockchip, PCIE_CORE_INT_STATUS);
 		if (sub_reg & PCIE_CORE_INT_PRFPE)
-			dev_dbg(pp->dev, "parity error detected while reading from the PNP receive FIFO RAM\n");
+			dev_dbg(rockchip->dev, "parity error detected while reading from the PNP receive FIFO RAM\n");
 
 		if (sub_reg & PCIE_CORE_INT_CRFPE)
-			dev_dbg(pp->dev, "parity error detected while reading from the Completion Receive FIFO RAM\n");
+			dev_dbg(rockchip->dev, "parity error detected while reading from the Completion Receive FIFO RAM\n");
 
 		if (sub_reg & PCIE_CORE_INT_RRPE)
-			dev_dbg(pp->dev, "parity error detected while reading from replay buffer RAM\n");
+			dev_dbg(rockchip->dev, "parity error detected while reading from replay buffer RAM\n");
 
 		if (sub_reg & PCIE_CORE_INT_PRFO)
-			dev_dbg(pp->dev, "overflow occurred in the PNP receive FIFO\n");
+			dev_dbg(rockchip->dev, "overflow occurred in the PNP receive FIFO\n");
 
 		if (sub_reg & PCIE_CORE_INT_CRFO)
-			dev_dbg(pp->dev, "overflow occurred in the completion receive FIFO\n");
+			dev_dbg(rockchip->dev, "overflow occurred in the completion receive FIFO\n");
 
 		if (sub_reg & PCIE_CORE_INT_RT)
-			dev_dbg(pp->dev, "replay timer timed out\n");
+			dev_dbg(rockchip->dev, "replay timer timed out\n");
 
 		if (sub_reg & PCIE_CORE_INT_RTR)
-			dev_dbg(pp->dev, "replay timer rolled over after 4 transmissions of the same TLP\n");
+			dev_dbg(rockchip->dev, "replay timer rolled over after 4 transmissions of the same TLP\n");
 
 		if (sub_reg & PCIE_CORE_INT_PE)
-			dev_dbg(pp->dev, "phy error detected on receive side\n");
+			dev_dbg(rockchip->dev, "phy error detected on receive side\n");
 
 		if (sub_reg & PCIE_CORE_INT_MTR)
-			dev_dbg(pp->dev, "malformed TLP received from the link\n");
+			dev_dbg(rockchip->dev, "malformed TLP received from the link\n");
 
 		if (sub_reg & PCIE_CORE_INT_UCR)
-			dev_dbg(pp->dev, "malformed TLP received from the link\n");
+			dev_dbg(rockchip->dev, "malformed TLP received from the link\n");
 
 		if (sub_reg & PCIE_CORE_INT_FCE)
-			dev_dbg(pp->dev, "an error was observed in the flow control advertisements from the other side\n");
+			dev_dbg(rockchip->dev, "an error was observed in the flow control advertisements from the other side\n");
 
 		if (sub_reg & PCIE_CORE_INT_CT)
-			dev_dbg(pp->dev, "a request timed out waiting for completion\n");
+			dev_dbg(rockchip->dev, "a request timed out waiting for completion\n");
 
 		if (sub_reg & PCIE_CORE_INT_UTC)
-			dev_dbg(pp->dev, "unmapped TC error\n");
+			dev_dbg(rockchip->dev, "unmapped TC error\n");
 
 		if (sub_reg & PCIE_CORE_INT_MMVC)
-			dev_dbg(pp->dev, "MSI mask register changes\n");
+			dev_dbg(rockchip->dev, "MSI mask register changes\n");
 
-		rockchip_pcie_write(pp, sub_reg, PCIE_CORE_INT_STATUS);
+		rockchip_pcie_write(rockchip, sub_reg, PCIE_CORE_INT_STATUS);
 	} else if (reg & PCIE_CLIENT_INT_PHY) {
-		dev_dbg(pp->dev, "phy link changes\n");
-		rockchip_pcie_clr_bw_int(pp);
+		dev_dbg(rockchip->dev, "phy link changes\n");
+		rockchip_pcie_clr_bw_int(rockchip);
 	}
 
-	rockchip_pcie_write(pp, reg & PCIE_CLIENT_INT_LOCAL, PCIE_CLIENT_INT_STATUS);
+	rockchip_pcie_write(rockchip, reg & PCIE_CLIENT_INT_LOCAL, PCIE_CLIENT_INT_STATUS);
 
 	return IRQ_HANDLED;
 }
 
 static irqreturn_t rockchip_pcie_client_irq_handler(int irq, void *arg)
 {
-	struct rockchip_pcie_port *pp = arg;
+	struct rockchip_pcie_port *rockchip = arg;
 	u32 reg;
 
-	reg = rockchip_pcie_read(pp, PCIE_CLIENT_INT_STATUS);
+	reg = rockchip_pcie_read(rockchip, PCIE_CLIENT_INT_STATUS);
 	if (reg & PCIE_CLIENT_INT_LEGACY_DONE)
-		dev_dbg(pp->dev, "legacy done interrupt received\n");
+		dev_dbg(rockchip->dev, "legacy done interrupt received\n");
 
 	if (reg & PCIE_CLIENT_INT_MSG)
-		dev_dbg(pp->dev, "message done interrupt received\n");
+		dev_dbg(rockchip->dev, "message done interrupt received\n");
 
 	if (reg & PCIE_CLIENT_INT_HOT_RST)
-		dev_dbg(pp->dev, "hot reset interrupt received\n");
+		dev_dbg(rockchip->dev, "hot reset interrupt received\n");
 
 	if (reg & PCIE_CLIENT_INT_DPA)
-		dev_dbg(pp->dev, "dpa interrupt received\n");
+		dev_dbg(rockchip->dev, "dpa interrupt received\n");
 
 	if (reg & PCIE_CLIENT_INT_FATAL_ERR)
-		dev_dbg(pp->dev, "fatal error interrupt received\n");
+		dev_dbg(rockchip->dev, "fatal error interrupt received\n");
 
 	if (reg & PCIE_CLIENT_INT_NFATAL_ERR)
-		dev_dbg(pp->dev, "no fatal error interrupt received\n");
+		dev_dbg(rockchip->dev, "no fatal error interrupt received\n");
 
 	if (reg & PCIE_CLIENT_INT_CORR_ERR)
-		dev_dbg(pp->dev, "correctable error interrupt received\n");
+		dev_dbg(rockchip->dev, "correctable error interrupt received\n");
 
 	if (reg & PCIE_CLIENT_INT_PHY)
-		dev_dbg(pp->dev, "phy interrupt received\n");
+		dev_dbg(rockchip->dev, "phy interrupt received\n");
 
-	rockchip_pcie_write(pp, reg & (PCIE_CLIENT_INT_LEGACY_DONE |
+	rockchip_pcie_write(rockchip, reg & (PCIE_CLIENT_INT_LEGACY_DONE |
 			      PCIE_CLIENT_INT_MSG | PCIE_CLIENT_INT_HOT_RST |
 			      PCIE_CLIENT_INT_DPA | PCIE_CLIENT_INT_FATAL_ERR |
 			      PCIE_CLIENT_INT_NFATAL_ERR |
@@ -685,15 +684,15 @@ static irqreturn_t rockchip_pcie_client_irq_handler(int irq, void *arg)
 static void rockchip_pcie_legacy_int_handler(struct irq_desc *desc)
 {
 	struct irq_chip *chip = irq_desc_get_chip(desc);
-	struct rockchip_pcie_port *port;
+	struct rockchip_pcie_port *rockchip;
 	u32 reg;
 	u32 hwirq;
 	u32 virq;
 
 	chained_irq_enter(chip, desc);
-	port = irq_desc_get_handler_data(desc);
+	rockchip = irq_desc_get_handler_data(desc);
 
-	reg = rockchip_pcie_read(port, PCIE_CLIENT_INT_STATUS);
+	reg = rockchip_pcie_read(rockchip, PCIE_CLIENT_INT_STATUS);
 	reg = (reg & ROCKCHIP_PCIE_RPIFR1_INTR_MASK) >>
 	       ROCKCHIP_PCIE_RPIFR1_INTR_SHIFT;
 
@@ -701,11 +700,11 @@ static void rockchip_pcie_legacy_int_handler(struct irq_desc *desc)
 		hwirq = ffs(reg) - 1;
 		reg &= ~BIT(hwirq);
 
-		virq = irq_find_mapping(port->irq_domain, hwirq);
+		virq = irq_find_mapping(rockchip->irq_domain, hwirq);
 		if (virq)
 			generic_handle_irq(virq);
 		else
-			dev_err(port->dev, "unexpected IRQ, INT%d\n", hwirq);
+			dev_err(rockchip->dev, "unexpected IRQ, INT%d\n", hwirq);
 	}
 
 	chained_irq_exit(chip, desc);
@@ -714,13 +713,13 @@ static void rockchip_pcie_legacy_int_handler(struct irq_desc *desc)
 
 /**
  * rockchip_pcie_parse_dt - Parse Device Tree
- * @port: PCIe port information
+ * @rockchip: PCIe port information
  *
  * Return: '0' on success and error value on failure
  */
-static int rockchip_pcie_parse_dt(struct rockchip_pcie_port *port)
+static int rockchip_pcie_parse_dt(struct rockchip_pcie_port *rockchip)
 {
-	struct device *dev = port->dev;
+	struct device *dev = rockchip->dev;
 	struct platform_device *pdev = to_platform_device(dev);
 	struct device_node *node = dev->of_node;
 	struct resource *regs;
@@ -730,89 +729,89 @@ static int rockchip_pcie_parse_dt(struct rockchip_pcie_port *port)
 	regs = platform_get_resource_byname(pdev,
 					    IORESOURCE_MEM,
 					    "axi-base");
-	port->reg_base = devm_ioremap_resource(dev, regs);
-	if (IS_ERR(port->reg_base))
-		return PTR_ERR(port->reg_base);
+	rockchip->reg_base = devm_ioremap_resource(dev, regs);
+	if (IS_ERR(rockchip->reg_base))
+		return PTR_ERR(rockchip->reg_base);
 
 	regs = platform_get_resource_byname(pdev,
 					    IORESOURCE_MEM,
 					    "apb-base");
-	port->apb_base = devm_ioremap_resource(dev, regs);
-	if (IS_ERR(port->apb_base))
-		return PTR_ERR(port->apb_base);
+	rockchip->apb_base = devm_ioremap_resource(dev, regs);
+	if (IS_ERR(rockchip->apb_base))
+		return PTR_ERR(rockchip->apb_base);
 
-	port->phy = devm_phy_get(dev, "pcie-phy");
-	if (IS_ERR(port->phy)) {
-		if (PTR_ERR(port->phy) != -EPROBE_DEFER)
+	rockchip->phy = devm_phy_get(dev, "pcie-phy");
+	if (IS_ERR(rockchip->phy)) {
+		if (PTR_ERR(rockchip->phy) != -EPROBE_DEFER)
 			dev_err(dev, "missing phy\n");
-		return PTR_ERR(port->phy);
+		return PTR_ERR(rockchip->phy);
 	}
 
-	port->lanes = 1;
-	err = of_property_read_u32(node, "num-lanes", &port->lanes);
-	if (!err && (port->lanes == 0 ||
-		     port->lanes == 3 ||
-		     port->lanes > 4)) {
+	rockchip->lanes = 1;
+	err = of_property_read_u32(node, "num-lanes", &rockchip->lanes);
+	if (!err && (rockchip->lanes == 0 ||
+		     rockchip->lanes == 3 ||
+		     rockchip->lanes > 4)) {
 		dev_warn(dev, "invalid num-lanes, default to use one lane\n");
-		port->lanes = 1;
+		rockchip->lanes = 1;
 	}
 
-	port->core_rst = devm_reset_control_get(dev, "core");
-	if (IS_ERR(port->core_rst)) {
-		if (PTR_ERR(port->core_rst) != -EPROBE_DEFER)
+	rockchip->core_rst = devm_reset_control_get(dev, "core");
+	if (IS_ERR(rockchip->core_rst)) {
+		if (PTR_ERR(rockchip->core_rst) != -EPROBE_DEFER)
 			dev_err(dev, "missing core reset property in node\n");
-		return PTR_ERR(port->core_rst);
+		return PTR_ERR(rockchip->core_rst);
 	}
 
-	port->mgmt_rst = devm_reset_control_get(dev, "mgmt");
-	if (IS_ERR(port->mgmt_rst)) {
-		if (PTR_ERR(port->mgmt_rst) != -EPROBE_DEFER)
+	rockchip->mgmt_rst = devm_reset_control_get(dev, "mgmt");
+	if (IS_ERR(rockchip->mgmt_rst)) {
+		if (PTR_ERR(rockchip->mgmt_rst) != -EPROBE_DEFER)
 			dev_err(dev, "missing mgmt reset property in node\n");
-		return PTR_ERR(port->mgmt_rst);
+		return PTR_ERR(rockchip->mgmt_rst);
 	}
 
-	port->mgmt_sticky_rst = devm_reset_control_get(dev, "mgmt-sticky");
-	if (IS_ERR(port->mgmt_sticky_rst)) {
-		if (PTR_ERR(port->mgmt_sticky_rst) != -EPROBE_DEFER)
+	rockchip->mgmt_sticky_rst = devm_reset_control_get(dev, "mgmt-sticky");
+	if (IS_ERR(rockchip->mgmt_sticky_rst)) {
+		if (PTR_ERR(rockchip->mgmt_sticky_rst) != -EPROBE_DEFER)
 			dev_err(dev, "missing mgmt-sticky reset property in node\n");
-		return PTR_ERR(port->mgmt_sticky_rst);
+		return PTR_ERR(rockchip->mgmt_sticky_rst);
 	}
 
-	port->pipe_rst = devm_reset_control_get(dev, "pipe");
-	if (IS_ERR(port->pipe_rst)) {
-		if (PTR_ERR(port->pipe_rst) != -EPROBE_DEFER)
+	rockchip->pipe_rst = devm_reset_control_get(dev, "pipe");
+	if (IS_ERR(rockchip->pipe_rst)) {
+		if (PTR_ERR(rockchip->pipe_rst) != -EPROBE_DEFER)
 			dev_err(dev, "missing pipe reset property in node\n");
-		return PTR_ERR(port->pipe_rst);
+		return PTR_ERR(rockchip->pipe_rst);
 	}
 
-	port->ep_gpio = devm_gpiod_get(dev, "ep", GPIOD_OUT_HIGH);
-	if (IS_ERR(port->ep_gpio)) {
+	rockchip->ep_gpio = devm_gpiod_get(dev, "ep", GPIOD_OUT_HIGH);
+	if (IS_ERR(rockchip->ep_gpio)) {
 		dev_err(dev, "missing ep-gpios property in node\n");
-		return PTR_ERR(port->ep_gpio);
+		return PTR_ERR(rockchip->ep_gpio);
 	}
 
-	port->aclk_pcie = devm_clk_get(dev, "aclk");
-	if (IS_ERR(port->aclk_pcie)) {
+	rockchip->aclk_pcie = devm_clk_get(dev, "aclk");
+	if (IS_ERR(rockchip->aclk_pcie)) {
 		dev_err(dev, "aclk clock not found\n");
-		return PTR_ERR(port->aclk_pcie);
+		return PTR_ERR(rockchip->aclk_pcie);
 	}
 
-	port->aclk_perf_pcie = devm_clk_get(dev, "aclk-perf");
-	if (IS_ERR(port->aclk_perf_pcie)) {
+	rockchip->aclk_perf_pcie = devm_clk_get(dev, "aclk-perf");
+	if (IS_ERR(rockchip->aclk_perf_pcie)) {
 		dev_err(dev, "aclk_perf clock not found\n");
-		return PTR_ERR(port->aclk_perf_pcie);
+		return PTR_ERR(rockchip->aclk_perf_pcie);
 	}
 
-	port->hclk_pcie = devm_clk_get(dev, "hclk");
-	if (IS_ERR(port->hclk_pcie)) {
+	rockchip->hclk_pcie = devm_clk_get(dev, "hclk");
+	if (IS_ERR(rockchip->hclk_pcie)) {
 		dev_err(dev, "hclk clock not found\n");
-		return PTR_ERR(port->hclk_pcie);
+		return PTR_ERR(rockchip->hclk_pcie);
 	}
 
-	port->clk_pcie_pm = devm_clk_get(dev, "pm");
-	if (IS_ERR(port->clk_pcie_pm)) {
+	rockchip->clk_pcie_pm = devm_clk_get(dev, "pm");
+	if (IS_ERR(rockchip->clk_pcie_pm)) {
 		dev_err(dev, "pm clock not found\n");
-		return PTR_ERR(port->clk_pcie_pm);
+		return PTR_ERR(rockchip->clk_pcie_pm);
 	}
 
 	irq = platform_get_irq_byname(pdev, "sys");
@@ -822,7 +821,7 @@ static int rockchip_pcie_parse_dt(struct rockchip_pcie_port *port)
 	}
 
 	err = devm_request_irq(dev, irq, rockchip_pcie_subsys_irq_handler,
-			       IRQF_SHARED, "pcie-sys", port);
+			       IRQF_SHARED, "pcie-sys", rockchip);
 	if (err) {
 		dev_err(dev, "failed to request PCIe subsystem IRQ\n");
 		return err;
@@ -836,7 +835,7 @@ static int rockchip_pcie_parse_dt(struct rockchip_pcie_port *port)
 
 	irq_set_chained_handler_and_data(irq,
 					 rockchip_pcie_legacy_int_handler,
-					 port);
+					 rockchip);
 
 	irq = platform_get_irq_byname(pdev, "client");
 	if (irq < 0) {
@@ -845,29 +844,29 @@ static int rockchip_pcie_parse_dt(struct rockchip_pcie_port *port)
 	}
 
 	err = devm_request_irq(dev, irq, rockchip_pcie_client_irq_handler,
-			       IRQF_SHARED, "pcie-client", port);
+			       IRQF_SHARED, "pcie-client", rockchip);
 	if (err) {
 		dev_err(dev, "failed to request PCIe client IRQ\n");
 		return err;
 	}
 
-	port->vpcie3v3 = devm_regulator_get_optional(dev, "vpcie3v3");
-	if (IS_ERR(port->vpcie3v3)) {
-		if (PTR_ERR(port->vpcie3v3) == -EPROBE_DEFER)
+	rockchip->vpcie3v3 = devm_regulator_get_optional(dev, "vpcie3v3");
+	if (IS_ERR(rockchip->vpcie3v3)) {
+		if (PTR_ERR(rockchip->vpcie3v3) == -EPROBE_DEFER)
 			return -EPROBE_DEFER;
 		dev_info(dev, "no vpcie3v3 regulator found\n");
 	}
 
-	port->vpcie1v8 = devm_regulator_get_optional(dev, "vpcie1v8");
-	if (IS_ERR(port->vpcie1v8)) {
-		if (PTR_ERR(port->vpcie1v8) == -EPROBE_DEFER)
+	rockchip->vpcie1v8 = devm_regulator_get_optional(dev, "vpcie1v8");
+	if (IS_ERR(rockchip->vpcie1v8)) {
+		if (PTR_ERR(rockchip->vpcie1v8) == -EPROBE_DEFER)
 			return -EPROBE_DEFER;
 		dev_info(dev, "no vpcie1v8 regulator found\n");
 	}
 
-	port->vpcie0v9 = devm_regulator_get_optional(dev, "vpcie0v9");
-	if (IS_ERR(port->vpcie0v9)) {
-		if (PTR_ERR(port->vpcie0v9) == -EPROBE_DEFER)
+	rockchip->vpcie0v9 = devm_regulator_get_optional(dev, "vpcie0v9");
+	if (IS_ERR(rockchip->vpcie0v9)) {
+		if (PTR_ERR(rockchip->vpcie0v9) == -EPROBE_DEFER)
 			return -EPROBE_DEFER;
 		dev_info(dev, "no vpcie0v9 regulator found\n");
 	}
@@ -875,30 +874,30 @@ static int rockchip_pcie_parse_dt(struct rockchip_pcie_port *port)
 	return 0;
 }
 
-static int rockchip_pcie_set_vpcie(struct rockchip_pcie_port *port)
+static int rockchip_pcie_set_vpcie(struct rockchip_pcie_port *rockchip)
 {
 	int err;
 
-	if (!IS_ERR(port->vpcie3v3)) {
-		err = regulator_enable(port->vpcie3v3);
+	if (!IS_ERR(rockchip->vpcie3v3)) {
+		err = regulator_enable(rockchip->vpcie3v3);
 		if (err) {
-			dev_err(port->dev, "fail to enable vpcie3v3 regulator\n");
+			dev_err(rockchip->dev, "fail to enable vpcie3v3 regulator\n");
 			goto err_out;
 		}
 	}
 
-	if (!IS_ERR(port->vpcie1v8)) {
-		err = regulator_enable(port->vpcie1v8);
+	if (!IS_ERR(rockchip->vpcie1v8)) {
+		err = regulator_enable(rockchip->vpcie1v8);
 		if (err) {
-			dev_err(port->dev, "fail to enable vpcie1v8 regulator\n");
+			dev_err(rockchip->dev, "fail to enable vpcie1v8 regulator\n");
 			goto err_disable_3v3;
 		}
 	}
 
-	if (!IS_ERR(port->vpcie0v9)) {
-		err = regulator_enable(port->vpcie0v9);
+	if (!IS_ERR(rockchip->vpcie0v9)) {
+		err = regulator_enable(rockchip->vpcie0v9);
 		if (err) {
-			dev_err(port->dev, "fail to enable vpcie0v9 regulator\n");
+			dev_err(rockchip->dev, "fail to enable vpcie0v9 regulator\n");
 			goto err_disable_1v8;
 		}
 	}
@@ -906,22 +905,22 @@ static int rockchip_pcie_set_vpcie(struct rockchip_pcie_port *port)
 	return 0;
 
 err_disable_1v8:
-	if (!IS_ERR(port->vpcie1v8))
-		regulator_disable(port->vpcie1v8);
+	if (!IS_ERR(rockchip->vpcie1v8))
+		regulator_disable(rockchip->vpcie1v8);
 err_disable_3v3:
-	if (!IS_ERR(port->vpcie3v3))
-		regulator_disable(port->vpcie3v3);
+	if (!IS_ERR(rockchip->vpcie3v3))
+		regulator_disable(rockchip->vpcie3v3);
 err_out:
 	return err;
 }
 
-static void rockchip_pcie_enable_interrupts(struct rockchip_pcie_port *port)
+static void rockchip_pcie_enable_interrupts(struct rockchip_pcie_port *rockchip)
 {
-	rockchip_pcie_write(port, (PCIE_CLIENT_INT_CLI << 16) &
+	rockchip_pcie_write(rockchip, (PCIE_CLIENT_INT_CLI << 16) &
 		   (~PCIE_CLIENT_INT_CLI), PCIE_CLIENT_INT_MASK);
-	rockchip_pcie_write(port, (u32)(~PCIE_CORE_INT), PCIE_CORE_INT_MASK);
+	rockchip_pcie_write(rockchip, (u32)(~PCIE_CORE_INT), PCIE_CORE_INT_MASK);
 
-	rockchip_pcie_enable_bw_int(port);
+	rockchip_pcie_enable_bw_int(rockchip);
 }
 
 static int rockchip_pcie_intx_map(struct irq_domain *domain, unsigned int irq,
@@ -937,9 +936,9 @@ static const struct irq_domain_ops intx_domain_ops = {
 	.map = rockchip_pcie_intx_map,
 };
 
-static int rockchip_pcie_init_irq_domain(struct rockchip_pcie_port *pp)
+static int rockchip_pcie_init_irq_domain(struct rockchip_pcie_port *rockchip)
 {
-	struct device *dev = pp->dev;
+	struct device *dev = rockchip->dev;
 	struct device_node *intc = of_get_next_child(dev->of_node, NULL);
 
 	if (!intc) {
@@ -947,8 +946,9 @@ static int rockchip_pcie_init_irq_domain(struct rockchip_pcie_port *pp)
 		return -EINVAL;
 	}
 
-	pp->irq_domain = irq_domain_add_linear(intc, 4, &intx_domain_ops, pp);
-	if (!pp->irq_domain) {
+	rockchip->irq_domain = irq_domain_add_linear(intc, 4,
+						    &intx_domain_ops, rockchip);
+	if (!rockchip->irq_domain) {
 		dev_err(dev, "failed to get a INTx IRQ domain\n");
 		return -EINVAL;
 	}
@@ -956,7 +956,7 @@ static int rockchip_pcie_init_irq_domain(struct rockchip_pcie_port *pp)
 	return 0;
 }
 
-static int rockchip_pcie_prog_ob_atu(struct rockchip_pcie_port *pp,
+static int rockchip_pcie_prog_ob_atu(struct rockchip_pcie_port *rockchip,
 				     int region_no, int type, u8 num_pass_bits,
 				     u32 lower_addr, u32 upper_addr)
 {
@@ -980,7 +980,7 @@ static int rockchip_pcie_prog_ob_atu(struct rockchip_pcie_port *pp,
 			return -EINVAL;
 	}
 
-	aw_base = pp->apb_base + PCIE_CORE_AXI_CONF_BASE;
+	aw_base = rockchip->apb_base + PCIE_CORE_AXI_CONF_BASE;
 	aw_base += (region_no << OB_REG_SIZE_SHIFT);
 
 	ob_addr_0 = num_pass_bits & PCIE_CORE_OB_REGION_ADDR0_NUM_BITS;
@@ -996,7 +996,7 @@ static int rockchip_pcie_prog_ob_atu(struct rockchip_pcie_port *pp,
 	return 0;
 }
 
-static int rockchip_pcie_prog_ib_atu(struct rockchip_pcie_port *pp,
+static int rockchip_pcie_prog_ib_atu(struct rockchip_pcie_port *rockchip,
 				     int region_no, u8 num_pass_bits,
 				     u32 lower_addr, u32 upper_addr)
 {
@@ -1011,7 +1011,7 @@ static int rockchip_pcie_prog_ib_atu(struct rockchip_pcie_port *pp,
 	if (num_pass_bits > 63)
 		return -EINVAL;
 
-	aw_base = pp->apb_base + PCIE_CORE_AXI_INBOUND_BASE;
+	aw_base = rockchip->apb_base + PCIE_CORE_AXI_INBOUND_BASE;
 	aw_base += (region_no << IB_ROOT_PORT_REG_SIZE_SHIFT);
 
 	ib_addr_0 = num_pass_bits & PCIE_CORE_IB_REGION_ADDR0_NUM_BITS;
@@ -1026,7 +1026,7 @@ static int rockchip_pcie_prog_ib_atu(struct rockchip_pcie_port *pp,
 
 static int rockchip_pcie_probe(struct platform_device *pdev)
 {
-	struct rockchip_pcie_port *port;
+	struct rockchip_pcie_port *rockchip;
 	struct device *dev = &pdev->dev;
 	struct pci_bus *bus, *child;
 	struct resource_entry *win;
@@ -1046,55 +1046,55 @@ static int rockchip_pcie_probe(struct platform_device *pdev)
 	if (!dev->of_node)
 		return -ENODEV;
 
-	port = devm_kzalloc(dev, sizeof(*port), GFP_KERNEL);
-	if (!port)
+	rockchip = devm_kzalloc(dev, sizeof(*rockchip), GFP_KERNEL);
+	if (!rockchip)
 		return -ENOMEM;
 
-	port->dev = dev;
+	rockchip->dev = dev;
 
-	err = rockchip_pcie_parse_dt(port);
+	err = rockchip_pcie_parse_dt(rockchip);
 	if (err)
 		return err;
 
-	err = clk_prepare_enable(port->aclk_pcie);
+	err = clk_prepare_enable(rockchip->aclk_pcie);
 	if (err) {
 		dev_err(dev, "unable to enable aclk_pcie clock\n");
 		goto err_aclk_pcie;
 	}
 
-	err = clk_prepare_enable(port->aclk_perf_pcie);
+	err = clk_prepare_enable(rockchip->aclk_perf_pcie);
 	if (err) {
 		dev_err(dev, "unable to enable aclk_perf_pcie clock\n");
 		goto err_aclk_perf_pcie;
 	}
 
-	err = clk_prepare_enable(port->hclk_pcie);
+	err = clk_prepare_enable(rockchip->hclk_pcie);
 	if (err) {
 		dev_err(dev, "unable to enable hclk_pcie clock\n");
 		goto err_hclk_pcie;
 	}
 
-	err = clk_prepare_enable(port->clk_pcie_pm);
+	err = clk_prepare_enable(rockchip->clk_pcie_pm);
 	if (err) {
 		dev_err(dev, "unable to enable hclk_pcie clock\n");
 		goto err_pcie_pm;
 	}
 
-	err = rockchip_pcie_set_vpcie(port);
+	err = rockchip_pcie_set_vpcie(rockchip);
 	if (err) {
-		dev_err(port->dev, "failed to set vpcie regulator\n");
+		dev_err(rockchip->dev, "failed to set vpcie regulator\n");
 		goto err_set_vpcie;
 	}
 
-	err = rockchip_pcie_init_port(port);
+	err = rockchip_pcie_init_port(rockchip);
 	if (err)
 		goto err_vpcie;
 
-	platform_set_drvdata(pdev, port);
+	platform_set_drvdata(pdev, rockchip);
 
-	rockchip_pcie_enable_interrupts(port);
+	rockchip_pcie_enable_interrupts(rockchip);
 
-	err = rockchip_pcie_init_irq_domain(port);
+	err = rockchip_pcie_init_irq_domain(rockchip);
 	if (err < 0)
 		goto err_vpcie;
 
@@ -1117,7 +1117,7 @@ static int rockchip_pcie_probe(struct platform_device *pdev)
 			io_bus_addr = io->start - win->offset;
 			err = pci_remap_iospace(io, io_base);
 			if (err) {
-				dev_warn(port->dev, "error %d: failed to map resource %pR\n",
+				dev_warn(rockchip->dev, "error %d: failed to map resource %pR\n",
 					 err, io);
 				continue;
 			}
@@ -1129,7 +1129,7 @@ static int rockchip_pcie_probe(struct platform_device *pdev)
 			mem_bus_addr = mem->start - win->offset;
 			break;
 		case IORESOURCE_BUS:
-			port->root_bus_nr = win->res->start;
+			rockchip->root_bus_nr = win->res->start;
 			break;
 		default:
 			continue;
@@ -1138,7 +1138,7 @@ static int rockchip_pcie_probe(struct platform_device *pdev)
 
 	if (mem_size) {
 		for (reg_no = 0; reg_no < (mem_size >> 20); reg_no++) {
-			err = rockchip_pcie_prog_ob_atu(port, reg_no + 1,
+			err = rockchip_pcie_prog_ob_atu(rockchip, reg_no + 1,
 							AXI_WRAPPER_MEM_WRITE,
 							20 - 1,
 							mem_bus_addr +
@@ -1151,7 +1151,7 @@ static int rockchip_pcie_probe(struct platform_device *pdev)
 		}
 	}
 
-	err = rockchip_pcie_prog_ib_atu(port, 2, 32 - 1, 0x0, 0);
+	err = rockchip_pcie_prog_ib_atu(rockchip, 2, 32 - 1, 0x0, 0);
 	if (err) {
 		dev_err(dev, "program RC mem inbound ATU failed\n");
 		goto err_vpcie;
@@ -1161,7 +1161,7 @@ static int rockchip_pcie_probe(struct platform_device *pdev)
 
 	if (io_size) {
 		for (reg_no = 0; reg_no < (io_size >> 20); reg_no++) {
-			err = rockchip_pcie_prog_ob_atu(port,
+			err = rockchip_pcie_prog_ob_atu(rockchip,
 							reg_no + 1 + offset,
 							AXI_WRAPPER_IO_WRITE,
 							20 - 1,
@@ -1175,7 +1175,7 @@ static int rockchip_pcie_probe(struct platform_device *pdev)
 		}
 	}
 
-	bus = pci_scan_root_bus(&pdev->dev, 0, &rockchip_pcie_ops, port, &res);
+	bus = pci_scan_root_bus(&pdev->dev, 0, &rockchip_pcie_ops, rockchip, &res);
 	if (!bus) {
 		err = -ENOMEM;
 		goto err_vpcie;
@@ -1193,20 +1193,20 @@ static int rockchip_pcie_probe(struct platform_device *pdev)
 	return err;
 
 err_vpcie:
-	if (!IS_ERR(port->vpcie3v3))
-		regulator_disable(port->vpcie3v3);
-	if (!IS_ERR(port->vpcie1v8))
-		regulator_disable(port->vpcie1v8);
-	if (!IS_ERR(port->vpcie0v9))
-		regulator_disable(port->vpcie0v9);
+	if (!IS_ERR(rockchip->vpcie3v3))
+		regulator_disable(rockchip->vpcie3v3);
+	if (!IS_ERR(rockchip->vpcie1v8))
+		regulator_disable(rockchip->vpcie1v8);
+	if (!IS_ERR(rockchip->vpcie0v9))
+		regulator_disable(rockchip->vpcie0v9);
 err_set_vpcie:
-	clk_disable_unprepare(port->clk_pcie_pm);
+	clk_disable_unprepare(rockchip->clk_pcie_pm);
 err_pcie_pm:
-	clk_disable_unprepare(port->hclk_pcie);
+	clk_disable_unprepare(rockchip->hclk_pcie);
 err_hclk_pcie:
-	clk_disable_unprepare(port->aclk_perf_pcie);
+	clk_disable_unprepare(rockchip->aclk_perf_pcie);
 err_aclk_perf_pcie:
-	clk_disable_unprepare(port->aclk_pcie);
+	clk_disable_unprepare(rockchip->aclk_pcie);
 err_aclk_pcie:
 	return err;
 }

[PATCH 4/9] Rename struct rockchip_pcie_port to struct rockchip_pcie.

[Bjorn Helgaas]

---
 drivers/pci/host/pcie-rockchip.c |   46 +++++++++++++++++++-------------------
 1 file changed, 23 insertions(+), 23 deletions(-)

diff --git a/drivers/pci/host/pcie-rockchip.c b/drivers/pci/host/pcie-rockchip.c
index 3cfb47a..63fb0ebc 100644
--- a/drivers/pci/host/pcie-rockchip.c
+++ b/drivers/pci/host/pcie-rockchip.c
@@ -178,7 +178,7 @@
 	PCIE_CLIENT_INT_LEGACY_DONE | PCIE_CLIENT_INT_LEGACY | \
 	PCIE_CLIENT_INT_PHY)
 
-struct rockchip_pcie_port {
+struct rockchip_pcie {
 	void	__iomem *reg_base;		/* DT axi-base */
 	void	__iomem *apb_base;		/* DT apb-base */
 	struct	phy *phy;
@@ -200,17 +200,17 @@ struct rockchip_pcie_port {
 	struct	irq_domain *irq_domain;
 };
 
-static u32 rockchip_pcie_read(struct rockchip_pcie_port *rockchip, u32 reg)
+static u32 rockchip_pcie_read(struct rockchip_pcie *rockchip, u32 reg)
 {
 	return readl(rockchip->apb_base + reg);
 }
 
-static void rockchip_pcie_write(struct rockchip_pcie_port *rockchip, u32 val, u32 reg)
+static void rockchip_pcie_write(struct rockchip_pcie *rockchip, u32 val, u32 reg)
 {
 	writel(val, rockchip->apb_base + reg);
 }
 
-static void rockchip_pcie_enable_bw_int(struct rockchip_pcie_port *rockchip)
+static void rockchip_pcie_enable_bw_int(struct rockchip_pcie *rockchip)
 {
 	u32 status;
 
@@ -219,7 +219,7 @@ static void rockchip_pcie_enable_bw_int(struct rockchip_pcie_port *rockchip)
 	rockchip_pcie_write(rockchip, status, PCIE_RC_CONFIG_BASE + PCIE_RC_CONFIG_LCSR);
 }
 
-static void rockchip_pcie_clr_bw_int(struct rockchip_pcie_port *rockchip)
+static void rockchip_pcie_clr_bw_int(struct rockchip_pcie *rockchip)
 {
 	u32 status;
 
@@ -228,7 +228,7 @@ static void rockchip_pcie_clr_bw_int(struct rockchip_pcie_port *rockchip)
 	rockchip_pcie_write(rockchip, status, PCIE_RC_CONFIG_BASE + PCIE_RC_CONFIG_LCSR);
 }
 
-static int rockchip_pcie_valid_device(struct rockchip_pcie_port *rockchip,
+static int rockchip_pcie_valid_device(struct rockchip_pcie *rockchip,
 				      struct pci_bus *bus, int dev)
 {
 	/* access only one slot on each root port */
@@ -245,7 +245,7 @@ static int rockchip_pcie_valid_device(struct rockchip_pcie_port *rockchip,
 	return 1;
 }
 
-static int rockchip_pcie_rd_own_conf(struct rockchip_pcie_port *rockchip,
+static int rockchip_pcie_rd_own_conf(struct rockchip_pcie *rockchip,
 				     int where, int size, u32 *val)
 {
 	void __iomem *addr = rockchip->apb_base + PCIE_RC_CONFIG_BASE + where;
@@ -268,7 +268,7 @@ static int rockchip_pcie_rd_own_conf(struct rockchip_pcie_port *rockchip,
 	return PCIBIOS_SUCCESSFUL;
 }
 
-static int rockchip_pcie_wr_own_conf(struct rockchip_pcie_port *rockchip,
+static int rockchip_pcie_wr_own_conf(struct rockchip_pcie *rockchip,
 				     int where, int size, u32 val)
 {
 	u32 mask, tmp, offset;
@@ -289,7 +289,7 @@ static int rockchip_pcie_wr_own_conf(struct rockchip_pcie_port *rockchip,
 	return PCIBIOS_SUCCESSFUL;
 }
 
-static int rockchip_pcie_rd_other_conf(struct rockchip_pcie_port *rockchip,
+static int rockchip_pcie_rd_other_conf(struct rockchip_pcie *rockchip,
 				       struct pci_bus *bus, u32 devfn,
 				       int where, int size, u32 *val)
 {
@@ -316,7 +316,7 @@ static int rockchip_pcie_rd_other_conf(struct rockchip_pcie_port *rockchip,
 	return PCIBIOS_SUCCESSFUL;
 }
 
-static int rockchip_pcie_wr_other_conf(struct rockchip_pcie_port *rockchip,
+static int rockchip_pcie_wr_other_conf(struct rockchip_pcie *rockchip,
 				       struct pci_bus *bus, u32 devfn,
 				       int where, int size, u32 val)
 {
@@ -342,7 +342,7 @@ static int rockchip_pcie_wr_other_conf(struct rockchip_pcie_port *rockchip,
 static int rockchip_pcie_rd_conf(struct pci_bus *bus, u32 devfn, int where,
 				 int size, u32 *val)
 {
-	struct rockchip_pcie_port *rockchip = bus->sysdata;
+	struct rockchip_pcie *rockchip = bus->sysdata;
 
 	if (!rockchip_pcie_valid_device(rockchip, bus, PCI_SLOT(devfn))) {
 		*val = 0xffffffff;
@@ -358,7 +358,7 @@ static int rockchip_pcie_rd_conf(struct pci_bus *bus, u32 devfn, int where,
 static int rockchip_pcie_wr_conf(struct pci_bus *bus, u32 devfn,
 				 int where, int size, u32 val)
 {
-	struct rockchip_pcie_port *rockchip = bus->sysdata;
+	struct rockchip_pcie *rockchip = bus->sysdata;
 
 	if (!rockchip_pcie_valid_device(rockchip, bus, PCI_SLOT(devfn)))
 		return PCIBIOS_DEVICE_NOT_FOUND;
@@ -378,7 +378,7 @@ static struct pci_ops rockchip_pcie_ops = {
  * rockchip_pcie_init_port - Initialize hardware
  * @rockchip: PCIe port information
  */
-static int rockchip_pcie_init_port(struct rockchip_pcie_port *rockchip)
+static int rockchip_pcie_init_port(struct rockchip_pcie *rockchip)
 {
 	int err;
 	u32 status;
@@ -579,7 +579,7 @@ static int rockchip_pcie_init_port(struct rockchip_pcie_port *rockchip)
 
 static irqreturn_t rockchip_pcie_subsys_irq_handler(int irq, void *arg)
 {
-	struct rockchip_pcie_port *rockchip = arg;
+	struct rockchip_pcie *rockchip = arg;
 	u32 reg;
 	u32 sub_reg;
 
@@ -642,7 +642,7 @@ static irqreturn_t rockchip_pcie_subsys_irq_handler(int irq, void *arg)
 
 static irqreturn_t rockchip_pcie_client_irq_handler(int irq, void *arg)
 {
-	struct rockchip_pcie_port *rockchip = arg;
+	struct rockchip_pcie *rockchip = arg;
 	u32 reg;
 
 	reg = rockchip_pcie_read(rockchip, PCIE_CLIENT_INT_STATUS);
@@ -684,7 +684,7 @@ static irqreturn_t rockchip_pcie_client_irq_handler(int irq, void *arg)
 static void rockchip_pcie_legacy_int_handler(struct irq_desc *desc)
 {
 	struct irq_chip *chip = irq_desc_get_chip(desc);
-	struct rockchip_pcie_port *rockchip;
+	struct rockchip_pcie *rockchip;
 	u32 reg;
 	u32 hwirq;
 	u32 virq;
@@ -717,7 +717,7 @@ static void rockchip_pcie_legacy_int_handler(struct irq_desc *desc)
  *
  * Return: '0' on success and error value on failure
  */
-static int rockchip_pcie_parse_dt(struct rockchip_pcie_port *rockchip)
+static int rockchip_pcie_parse_dt(struct rockchip_pcie *rockchip)
 {
 	struct device *dev = rockchip->dev;
 	struct platform_device *pdev = to_platform_device(dev);
@@ -874,7 +874,7 @@ static int rockchip_pcie_parse_dt(struct rockchip_pcie_port *rockchip)
 	return 0;
 }
 
-static int rockchip_pcie_set_vpcie(struct rockchip_pcie_port *rockchip)
+static int rockchip_pcie_set_vpcie(struct rockchip_pcie *rockchip)
 {
 	int err;
 
@@ -914,7 +914,7 @@ err_out:
 	return err;
 }
 
-static void rockchip_pcie_enable_interrupts(struct rockchip_pcie_port *rockchip)
+static void rockchip_pcie_enable_interrupts(struct rockchip_pcie *rockchip)
 {
 	rockchip_pcie_write(rockchip, (PCIE_CLIENT_INT_CLI << 16) &
 		   (~PCIE_CLIENT_INT_CLI), PCIE_CLIENT_INT_MASK);
@@ -936,7 +936,7 @@ static const struct irq_domain_ops intx_domain_ops = {
 	.map = rockchip_pcie_intx_map,
 };
 
-static int rockchip_pcie_init_irq_domain(struct rockchip_pcie_port *rockchip)
+static int rockchip_pcie_init_irq_domain(struct rockchip_pcie *rockchip)
 {
 	struct device *dev = rockchip->dev;
 	struct device_node *intc = of_get_next_child(dev->of_node, NULL);
@@ -956,7 +956,7 @@ static int rockchip_pcie_init_irq_domain(struct rockchip_pcie_port *rockchip)
 	return 0;
 }
 
-static int rockchip_pcie_prog_ob_atu(struct rockchip_pcie_port *rockchip,
+static int rockchip_pcie_prog_ob_atu(struct rockchip_pcie *rockchip,
 				     int region_no, int type, u8 num_pass_bits,
 				     u32 lower_addr, u32 upper_addr)
 {
@@ -996,7 +996,7 @@ static int rockchip_pcie_prog_ob_atu(struct rockchip_pcie_port *rockchip,
 	return 0;
 }
 
-static int rockchip_pcie_prog_ib_atu(struct rockchip_pcie_port *rockchip,
+static int rockchip_pcie_prog_ib_atu(struct rockchip_pcie *rockchip,
 				     int region_no, u8 num_pass_bits,
 				     u32 lower_addr, u32 upper_addr)
 {
@@ -1026,7 +1026,7 @@ static int rockchip_pcie_prog_ib_atu(struct rockchip_pcie_port *rockchip,
 
 static int rockchip_pcie_probe(struct platform_device *pdev)
 {
-	struct rockchip_pcie_port *rockchip;
+	struct rockchip_pcie *rockchip;
 	struct device *dev = &pdev->dev;
 	struct pci_bus *bus, *child;
 	struct resource_entry *win;

[PATCH 5/9] Use a local "dev" to avoid repetition of "rockchip->dev".

[Bjorn Helgaas]

---
 drivers/pci/host/pcie-rockchip.c |   95 ++++++++++++++++++++------------------
 1 file changed, 50 insertions(+), 45 deletions(-)

diff --git a/drivers/pci/host/pcie-rockchip.c b/drivers/pci/host/pcie-rockchip.c
index 63fb0ebc..17612e5 100644
--- a/drivers/pci/host/pcie-rockchip.c
+++ b/drivers/pci/host/pcie-rockchip.c
@@ -380,6 +380,7 @@ static struct pci_ops rockchip_pcie_ops = {
  */
 static int rockchip_pcie_init_port(struct rockchip_pcie *rockchip)
 {
+	struct device *dev = rockchip->dev;
 	int err;
 	u32 status;
 	unsigned long timeout;
@@ -388,31 +389,31 @@ static int rockchip_pcie_init_port(struct rockchip_pcie *rockchip)
 
 	err = phy_init(rockchip->phy);
 	if (err < 0) {
-		dev_err(rockchip->dev, "fail to init phy, err %d\n", err);
+		dev_err(dev, "fail to init phy, err %d\n", err);
 		return err;
 	}
 
 	err = reset_control_assert(rockchip->core_rst);
 	if (err) {
-		dev_err(rockchip->dev, "assert core_rst err %d\n", err);
+		dev_err(dev, "assert core_rst err %d\n", err);
 		return err;
 	}
 
 	err = reset_control_assert(rockchip->mgmt_rst);
 	if (err) {
-		dev_err(rockchip->dev, "assert mgmt_rst err %d\n", err);
+		dev_err(dev, "assert mgmt_rst err %d\n", err);
 		return err;
 	}
 
 	err = reset_control_assert(rockchip->mgmt_sticky_rst);
 	if (err) {
-		dev_err(rockchip->dev, "assert mgmt_sticky_rst err %d\n", err);
+		dev_err(dev, "assert mgmt_sticky_rst err %d\n", err);
 		return err;
 	}
 
 	err = reset_control_assert(rockchip->pipe_rst);
 	if (err) {
-		dev_err(rockchip->dev, "assert pipe_rst err %d\n", err);
+		dev_err(dev, "assert pipe_rst err %d\n", err);
 		return err;
 	}
 
@@ -436,31 +437,31 @@ static int rockchip_pcie_init_port(struct rockchip_pcie *rockchip)
 
 	err = phy_power_on(rockchip->phy);
 	if (err) {
-		dev_err(rockchip->dev, "fail to power on phy, err %d\n", err);
+		dev_err(dev, "fail to power on phy, err %d\n", err);
 		return err;
 	}
 
 	err = reset_control_deassert(rockchip->core_rst);
 	if (err) {
-		dev_err(rockchip->dev, "deassert core_rst err %d\n", err);
+		dev_err(dev, "deassert core_rst err %d\n", err);
 		return err;
 	}
 
 	err = reset_control_deassert(rockchip->mgmt_rst);
 	if (err) {
-		dev_err(rockchip->dev, "deassert mgmt_rst err %d\n", err);
+		dev_err(dev, "deassert mgmt_rst err %d\n", err);
 		return err;
 	}
 
 	err = reset_control_deassert(rockchip->mgmt_sticky_rst);
 	if (err) {
-		dev_err(rockchip->dev, "deassert mgmt_sticky_rst err %d\n", err);
+		dev_err(dev, "deassert mgmt_sticky_rst err %d\n", err);
 		return err;
 	}
 
 	err = reset_control_deassert(rockchip->pipe_rst);
 	if (err) {
-		dev_err(rockchip->dev, "deassert pipe_rst err %d\n", err);
+		dev_err(dev, "deassert pipe_rst err %d\n", err);
 		return err;
 	}
 
@@ -492,7 +493,7 @@ static int rockchip_pcie_init_port(struct rockchip_pcie *rockchip)
 		if (((status >> PCIE_CLIENT_LINK_STATUS_SHIFT) &
 		      PCIE_CLIENT_LINK_STATUS_MASK) ==
 		      PCIE_CLIENT_LINK_STATUS_UP) {
-			dev_dbg(rockchip->dev, "PCIe link training gen1 pass!\n");
+			dev_dbg(dev, "PCIe link training gen1 pass!\n");
 			break;
 		}
 
@@ -511,7 +512,7 @@ static int rockchip_pcie_init_port(struct rockchip_pcie *rockchip)
 			PCIE_CLIENT_LINK_STATUS_MASK) ==
 			PCIE_CLIENT_LINK_STATUS_UP) ? 0 : -ETIMEDOUT;
 		if (err) {
-			dev_err(rockchip->dev, "PCIe link training gen1 timeout!\n");
+			dev_err(dev, "PCIe link training gen1 timeout!\n");
 			return err;
 		}
 	}
@@ -532,7 +533,7 @@ static int rockchip_pcie_init_port(struct rockchip_pcie *rockchip)
 		if (((status >> PCIE_CORE_PL_CONF_SPEED_SHIFT) &
 		     PCIE_CORE_PL_CONF_SPEED_MASK) ==
 		     PCIE_CORE_PL_CONF_SPEED_5G) {
-			dev_dbg(rockchip->dev, "PCIe link training gen2 pass!\n");
+			dev_dbg(dev, "PCIe link training gen2 pass!\n");
 			break;
 		}
 
@@ -551,14 +552,14 @@ static int rockchip_pcie_init_port(struct rockchip_pcie *rockchip)
 			PCIE_CORE_PL_CONF_SPEED_MASK) ==
 			PCIE_CORE_PL_CONF_SPEED_5G) ? 0 : -ETIMEDOUT;
 		if (err)
-			dev_dbg(rockchip->dev, "PCIe link training gen2 timeout, fall back to gen1!\n");
+			dev_dbg(dev, "PCIe link training gen2 timeout, fall back to gen1!\n");
 	}
 
 	/* Check the final link width from negotiated lane counter from MGMT */
 	status = rockchip_pcie_read(rockchip, PCIE_CORE_CTRL_MGMT_BASE);
 	status =  0x1 << ((status >> PCIE_CORE_PL_CONF_LANE_SHIFT) &
 			   PCIE_CORE_PL_CONF_LANE_MASK);
-	dev_dbg(rockchip->dev, "current link width is x%d\n", status);
+	dev_dbg(dev, "current link width is x%d\n", status);
 
 	rockchip_pcie_write(rockchip, ROCKCHIP_VENDOR_ID, PCIE_RC_CONFIG_BASE);
 	rockchip_pcie_write(rockchip, PCI_CLASS_BRIDGE_PCI << PCIE_CORE_RC_CONF_SCC_SHIFT,
@@ -580,58 +581,59 @@ static int rockchip_pcie_init_port(struct rockchip_pcie *rockchip)
 static irqreturn_t rockchip_pcie_subsys_irq_handler(int irq, void *arg)
 {
 	struct rockchip_pcie *rockchip = arg;
+	struct device *dev = rockchip->dev;
 	u32 reg;
 	u32 sub_reg;
 
 	reg = rockchip_pcie_read(rockchip, PCIE_CLIENT_INT_STATUS);
 	if (reg & PCIE_CLIENT_INT_LOCAL) {
-		dev_dbg(rockchip->dev, "local interrupt received\n");
+		dev_dbg(dev, "local interrupt received\n");
 		sub_reg = rockchip_pcie_read(rockchip, PCIE_CORE_INT_STATUS);
 		if (sub_reg & PCIE_CORE_INT_PRFPE)
-			dev_dbg(rockchip->dev, "parity error detected while reading from the PNP receive FIFO RAM\n");
+			dev_dbg(dev, "parity error detected while reading from the PNP receive FIFO RAM\n");
 
 		if (sub_reg & PCIE_CORE_INT_CRFPE)
-			dev_dbg(rockchip->dev, "parity error detected while reading from the Completion Receive FIFO RAM\n");
+			dev_dbg(dev, "parity error detected while reading from the Completion Receive FIFO RAM\n");
 
 		if (sub_reg & PCIE_CORE_INT_RRPE)
-			dev_dbg(rockchip->dev, "parity error detected while reading from replay buffer RAM\n");
+			dev_dbg(dev, "parity error detected while reading from replay buffer RAM\n");
 
 		if (sub_reg & PCIE_CORE_INT_PRFO)
-			dev_dbg(rockchip->dev, "overflow occurred in the PNP receive FIFO\n");
+			dev_dbg(dev, "overflow occurred in the PNP receive FIFO\n");
 
 		if (sub_reg & PCIE_CORE_INT_CRFO)
-			dev_dbg(rockchip->dev, "overflow occurred in the completion receive FIFO\n");
+			dev_dbg(dev, "overflow occurred in the completion receive FIFO\n");
 
 		if (sub_reg & PCIE_CORE_INT_RT)
-			dev_dbg(rockchip->dev, "replay timer timed out\n");
+			dev_dbg(dev, "replay timer timed out\n");
 
 		if (sub_reg & PCIE_CORE_INT_RTR)
-			dev_dbg(rockchip->dev, "replay timer rolled over after 4 transmissions of the same TLP\n");
+			dev_dbg(dev, "replay timer rolled over after 4 transmissions of the same TLP\n");
 
 		if (sub_reg & PCIE_CORE_INT_PE)
-			dev_dbg(rockchip->dev, "phy error detected on receive side\n");
+			dev_dbg(dev, "phy error detected on receive side\n");
 
 		if (sub_reg & PCIE_CORE_INT_MTR)
-			dev_dbg(rockchip->dev, "malformed TLP received from the link\n");
+			dev_dbg(dev, "malformed TLP received from the link\n");
 
 		if (sub_reg & PCIE_CORE_INT_UCR)
-			dev_dbg(rockchip->dev, "malformed TLP received from the link\n");
+			dev_dbg(dev, "malformed TLP received from the link\n");
 
 		if (sub_reg & PCIE_CORE_INT_FCE)
-			dev_dbg(rockchip->dev, "an error was observed in the flow control advertisements from the other side\n");
+			dev_dbg(dev, "an error was observed in the flow control advertisements from the other side\n");
 
 		if (sub_reg & PCIE_CORE_INT_CT)
-			dev_dbg(rockchip->dev, "a request timed out waiting for completion\n");
+			dev_dbg(dev, "a request timed out waiting for completion\n");
 
 		if (sub_reg & PCIE_CORE_INT_UTC)
-			dev_dbg(rockchip->dev, "unmapped TC error\n");
+			dev_dbg(dev, "unmapped TC error\n");
 
 		if (sub_reg & PCIE_CORE_INT_MMVC)
-			dev_dbg(rockchip->dev, "MSI mask register changes\n");
+			dev_dbg(dev, "MSI mask register changes\n");
 
 		rockchip_pcie_write(rockchip, sub_reg, PCIE_CORE_INT_STATUS);
 	} else if (reg & PCIE_CLIENT_INT_PHY) {
-		dev_dbg(rockchip->dev, "phy link changes\n");
+		dev_dbg(dev, "phy link changes\n");
 		rockchip_pcie_clr_bw_int(rockchip);
 	}
 
@@ -643,32 +645,33 @@ static irqreturn_t rockchip_pcie_subsys_irq_handler(int irq, void *arg)
 static irqreturn_t rockchip_pcie_client_irq_handler(int irq, void *arg)
 {
 	struct rockchip_pcie *rockchip = arg;
+	struct device *dev = rockchip->dev;
 	u32 reg;
 
 	reg = rockchip_pcie_read(rockchip, PCIE_CLIENT_INT_STATUS);
 	if (reg & PCIE_CLIENT_INT_LEGACY_DONE)
-		dev_dbg(rockchip->dev, "legacy done interrupt received\n");
+		dev_dbg(dev, "legacy done interrupt received\n");
 
 	if (reg & PCIE_CLIENT_INT_MSG)
-		dev_dbg(rockchip->dev, "message done interrupt received\n");
+		dev_dbg(dev, "message done interrupt received\n");
 
 	if (reg & PCIE_CLIENT_INT_HOT_RST)
-		dev_dbg(rockchip->dev, "hot reset interrupt received\n");
+		dev_dbg(dev, "hot reset interrupt received\n");
 
 	if (reg & PCIE_CLIENT_INT_DPA)
-		dev_dbg(rockchip->dev, "dpa interrupt received\n");
+		dev_dbg(dev, "dpa interrupt received\n");
 
 	if (reg & PCIE_CLIENT_INT_FATAL_ERR)
-		dev_dbg(rockchip->dev, "fatal error interrupt received\n");
+		dev_dbg(dev, "fatal error interrupt received\n");
 
 	if (reg & PCIE_CLIENT_INT_NFATAL_ERR)
-		dev_dbg(rockchip->dev, "no fatal error interrupt received\n");
+		dev_dbg(dev, "no fatal error interrupt received\n");
 
 	if (reg & PCIE_CLIENT_INT_CORR_ERR)
-		dev_dbg(rockchip->dev, "correctable error interrupt received\n");
+		dev_dbg(dev, "correctable error interrupt received\n");
 
 	if (reg & PCIE_CLIENT_INT_PHY)
-		dev_dbg(rockchip->dev, "phy interrupt received\n");
+		dev_dbg(dev, "phy interrupt received\n");
 
 	rockchip_pcie_write(rockchip, reg & (PCIE_CLIENT_INT_LEGACY_DONE |
 			      PCIE_CLIENT_INT_MSG | PCIE_CLIENT_INT_HOT_RST |
@@ -685,6 +688,7 @@ static void rockchip_pcie_legacy_int_handler(struct irq_desc *desc)
 {
 	struct irq_chip *chip = irq_desc_get_chip(desc);
 	struct rockchip_pcie *rockchip;
+	struct device *dev = rockchip->dev;
 	u32 reg;
 	u32 hwirq;
 	u32 virq;
@@ -704,7 +708,7 @@ static void rockchip_pcie_legacy_int_handler(struct irq_desc *desc)
 		if (virq)
 			generic_handle_irq(virq);
 		else
-			dev_err(rockchip->dev, "unexpected IRQ, INT%d\n", hwirq);
+			dev_err(dev, "unexpected IRQ, INT%d\n", hwirq);
 	}
 
 	chained_irq_exit(chip, desc);
@@ -876,12 +880,13 @@ static int rockchip_pcie_parse_dt(struct rockchip_pcie *rockchip)
 
 static int rockchip_pcie_set_vpcie(struct rockchip_pcie *rockchip)
 {
+	struct device *dev = rockchip->dev;
 	int err;
 
 	if (!IS_ERR(rockchip->vpcie3v3)) {
 		err = regulator_enable(rockchip->vpcie3v3);
 		if (err) {
-			dev_err(rockchip->dev, "fail to enable vpcie3v3 regulator\n");
+			dev_err(dev, "fail to enable vpcie3v3 regulator\n");
 			goto err_out;
 		}
 	}
@@ -889,7 +894,7 @@ static int rockchip_pcie_set_vpcie(struct rockchip_pcie *rockchip)
 	if (!IS_ERR(rockchip->vpcie1v8)) {
 		err = regulator_enable(rockchip->vpcie1v8);
 		if (err) {
-			dev_err(rockchip->dev, "fail to enable vpcie1v8 regulator\n");
+			dev_err(dev, "fail to enable vpcie1v8 regulator\n");
 			goto err_disable_3v3;
 		}
 	}
@@ -897,7 +902,7 @@ static int rockchip_pcie_set_vpcie(struct rockchip_pcie *rockchip)
 	if (!IS_ERR(rockchip->vpcie0v9)) {
 		err = regulator_enable(rockchip->vpcie0v9);
 		if (err) {
-			dev_err(rockchip->dev, "fail to enable vpcie0v9 regulator\n");
+			dev_err(dev, "fail to enable vpcie0v9 regulator\n");
 			goto err_disable_1v8;
 		}
 	}
@@ -1082,7 +1087,7 @@ static int rockchip_pcie_probe(struct platform_device *pdev)
 
 	err = rockchip_pcie_set_vpcie(rockchip);
 	if (err) {
-		dev_err(rockchip->dev, "failed to set vpcie regulator\n");
+		dev_err(dev, "failed to set vpcie regulator\n");
 		goto err_set_vpcie;
 	}
 
@@ -1117,7 +1122,7 @@ static int rockchip_pcie_probe(struct platform_device *pdev)
 			io_bus_addr = io->start - win->offset;
 			err = pci_remap_iospace(io, io_base);
 			if (err) {
-				dev_warn(rockchip->dev, "error %d: failed to map resource %pR\n",
+				dev_warn(dev, "error %d: failed to map resource %pR\n",
 					 err, io);
 				continue;
 			}

[PATCH 6/9] Add comment about why 32-bit read/modify/write isn't safe.

[Bjorn Helgaas]

---
 drivers/pci/host/pcie-rockchip.c |    5 +++++
 1 file changed, 5 insertions(+)

diff --git a/drivers/pci/host/pcie-rockchip.c b/drivers/pci/host/pcie-rockchip.c
index 17612e5..33bf2e1 100644
--- a/drivers/pci/host/pcie-rockchip.c
+++ b/drivers/pci/host/pcie-rockchip.c
@@ -282,6 +282,11 @@ static int rockchip_pcie_wr_own_conf(struct rockchip_pcie *rockchip,
 
 	mask = ~(((1 << (size * 8)) - 1) << ((where & 0x3) * 8));
 
+	/*
+	 * N.B. This read/modify/write isn't safe in general because it can
+	 * corrupt RW1C bits in adjacent registers.  But the hardware
+	 * doesn't support smaller writes.
+	 */
 	tmp = readl(rockchip->apb_base + PCIE_RC_CONFIG_BASE + offset) & mask;
 	tmp |= val << ((where & 0x3) * 8);
 	writel(tmp, rockchip->apb_base + PCIE_RC_CONFIG_BASE + offset);

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[PATCH 7/9] Simplify the confusing HIWORD_UPDATE scheme.

[Bjorn Helgaas]

---
 drivers/pci/host/pcie-rockchip.c |   69 +++++++++++++-------------------------
 1 file changed, 23 insertions(+), 46 deletions(-)

diff --git a/drivers/pci/host/pcie-rockchip.c b/drivers/pci/host/pcie-rockchip.c
index 33bf2e1..7f6fe7d 100644
--- a/drivers/pci/host/pcie-rockchip.c
+++ b/drivers/pci/host/pcie-rockchip.c
@@ -115,36 +115,25 @@
 	  (PCIE_ECAM_BUS(bus) | PCIE_ECAM_DEV(dev) | \
 	   PCIE_ECAM_FUNC(func) | PCIE_ECAM_REG(reg))
 
-/*
-  * The higher 16-bit of this register is used for write protection
-  * only if BIT(x + 16) set to 1 the BIT(x) can be written.
-  */
-#define HIWORD_UPDATE(val, mask, shift) \
-	((val) << (shift) | (mask) << ((shift) + 16))
-
 #define RC_REGION_0_ADDR_TRANS_H		0x00000000
 #define RC_REGION_0_ADDR_TRANS_L		0x00000000
 #define RC_REGION_0_PASS_BITS			(25 - 1)
 #define MAX_AXI_WRAPPER_REGION_NUM		33
 #define PCIE_CORE_LCSR_RETRAIN_LINK		BIT(5)
-#define PCIE_CLIENT_CONF_ENABLE			BIT(0)
-#define PCIE_CLIENT_CONF_ENABLE_SHIFT		0
-#define PCIE_CLIENT_CONF_ENABLE_MASK		0x1
-#define PCIE_CLIENT_LINK_TRAIN_ENABLE		1
-#define PCIE_CLIENT_LINK_TRAIN_SHIFT		1
-#define PCIE_CLIENT_LINK_TRAIN_MASK		0x1
-#define PCIE_CLIENT_ARI_ENABLE			BIT(0)
-#define PCIE_CLIENT_ARI_ENABLE_SHIFT		3
-#define PCIE_CLIENT_ARI_ENABLE_MASK		0x1
-#define PCIE_CLIENT_CONF_LANE_NUM(x)		(x / 2)
-#define PCIE_CLIENT_CONF_LANE_NUM_SHIFT		4
-#define PCIE_CLIENT_CONF_LANE_NUM_MASK		0x3
-#define PCIE_CLIENT_MODE_RC			BIT(0)
-#define PCIE_CLIENT_MODE_SHIFT			6
-#define PCIE_CLIENT_MODE_MASK			0x1
-#define PCIE_CLIENT_GEN_SEL_2			1
-#define PCIE_CLIENT_GEN_SEL_SHIFT		7
-#define PCIE_CLIENT_GEN_SEL_MASK		0x1
+
+/*
+ * The higher 16-bit of this register is used for write protection
+ * only if BIT(x + 16) set to 1 the BIT(x) can be written.
+ */
+#define PCIE_CLIENT_CONF_ENABLE		(0x00010000 | 0x0001)
+#define PCIE_CLIENT_LINK_TRAIN_ENABLE	(0x00020000 | 0x0002)
+#define PCIE_CLIENT_ARI_ENABLE		(0x00080000 | 0x0008)
+#define PCIE_CLIENT_CONF_LANE_NUM(x)	(0x00300000 | (((x >> 1) & 3) << 4)
+#define PCIE_CLIENT_MODE_RC		(0x00400000 | 0x0040)
+#define PCIE_CLIENT_GEN_SEL(x)		(0x00800000 | ((x & 1) << 7)
+#define  PCIE_CLIENT_GEN_SEL_0			0
+#define  PCIE_CLIENT_GEN_SEL_2			1
+
 #define PCIE_CLIENT_LINK_STATUS_UP		0x3
 #define PCIE_CLIENT_LINK_STATUS_SHIFT		20
 #define PCIE_CLIENT_LINK_STATUS_MASK		0x3
@@ -423,22 +412,13 @@ static int rockchip_pcie_init_port(struct rockchip_pcie *rockchip)
 	}
 
 	rockchip_pcie_write(rockchip,
-		   HIWORD_UPDATE(PCIE_CLIENT_CONF_ENABLE,
-				 PCIE_CLIENT_CONF_ENABLE_MASK,
-				 PCIE_CLIENT_CONF_ENABLE_SHIFT) |
-		   HIWORD_UPDATE(PCIE_CLIENT_CONF_LANE_NUM(rockchip->lanes),
-				 PCIE_CLIENT_CONF_LANE_NUM_MASK,
-				 PCIE_CLIENT_CONF_LANE_NUM_SHIFT) |
-		   HIWORD_UPDATE(PCIE_CLIENT_MODE_RC,
-				 PCIE_CLIENT_MODE_MASK,
-				 PCIE_CLIENT_MODE_SHIFT) |
-		   HIWORD_UPDATE(PCIE_CLIENT_ARI_ENABLE,
-				 PCIE_CLIENT_ARI_ENABLE_MASK,
-				 PCIE_CLIENT_ARI_ENABLE_SHIFT) |
-		   HIWORD_UPDATE(PCIE_CLIENT_GEN_SEL_2,
-				 PCIE_CLIENT_GEN_SEL_MASK,
-				 PCIE_CLIENT_GEN_SEL_SHIFT),
-		   PCIE_CLIENT_BASE);
+			    PCIE_CLIENT_CONF_ENABLE |
+			    PCIE_CLIENT_LINK_TRAIN_ENABLE |
+			    PCIE_CLIENT_ARI_ENABLE |
+			    PCIE_CLIENT_CONF_LANE_NUM(rockchip->lanes) |
+			    PCIE_CLIENT_MODE_RC |
+			    PCIE_CLIENT_GEN_SEL(PCIE_CLIENT_GEN_SEL_2),
+			    PCIE_CLIENT_BASE);
 
 	err = phy_power_on(rockchip->phy);
 	if (err) {
@@ -482,11 +462,8 @@ static int rockchip_pcie_init_port(struct rockchip_pcie *rockchip)
 				 PCIE_RC_CONFIG_L1_SUBSTATE_CTRL2);
 
 	/* Enable Gen1 training */
-	rockchip_pcie_write(rockchip,
-		   HIWORD_UPDATE(PCIE_CLIENT_LINK_TRAIN_ENABLE,
-				 PCIE_CLIENT_LINK_TRAIN_MASK,
-				 PCIE_CLIENT_LINK_TRAIN_SHIFT),
-		   PCIE_CLIENT_BASE);
+	rockchip_pcie_write(rockchip, PCIE_CLIENT_LINK_TRAIN_ENABLE,
+			    PCIE_CLIENT_BASE);
 
 	gpiod_set_value(rockchip->ep_gpio, 1);

[PATCH 8/9] Simplify testing of link status and speed testing.

[Bjorn Helgaas]

---
 drivers/pci/host/pcie-rockchip.c |   46 +++++++++++++++++---------------------
 1 file changed, 20 insertions(+), 26 deletions(-)

diff --git a/drivers/pci/host/pcie-rockchip.c b/drivers/pci/host/pcie-rockchip.c
index 7f6fe7d..61b0630 100644
--- a/drivers/pci/host/pcie-rockchip.c
+++ b/drivers/pci/host/pcie-rockchip.c
@@ -131,18 +131,16 @@
 #define PCIE_CLIENT_CONF_LANE_NUM(x)	(0x00300000 | (((x >> 1) & 3) << 4)
 #define PCIE_CLIENT_MODE_RC		(0x00400000 | 0x0040)
 #define PCIE_CLIENT_GEN_SEL(x)		(0x00800000 | ((x & 1) << 7)
-#define  PCIE_CLIENT_GEN_SEL_0			0
-#define  PCIE_CLIENT_GEN_SEL_2			1
-
-#define PCIE_CLIENT_LINK_STATUS_UP		0x3
-#define PCIE_CLIENT_LINK_STATUS_SHIFT		20
-#define PCIE_CLIENT_LINK_STATUS_MASK		0x3
-#define PCIE_CORE_PL_CONF_SPEED_5G		0x1
-#define PCIE_CORE_PL_CONF_SPEED_SHIFT		3
-#define PCIE_CORE_PL_CONF_SPEED_MASK		0x3
-#define PCIE_CORE_PL_CONF_LANE_SHIFT		1
-#define PCIE_CORE_PL_CONF_LANE_MASK		0x3
-#define PCIE_CORE_RC_CONF_SCC_SHIFT		16
+#define  PCIE_CLIENT_GEN_SEL_0		0
+#define  PCIE_CLIENT_GEN_SEL_2		1
+
+#define PCIE_CLIENT_LINK_STATUS_UP	0x00300000
+#define PCIE_CLIENT_LINK_STATUS_MASK	0x00300000
+#define PCIE_CORE_PL_CONF_SPEED_5G	0x00000008
+#define PCIE_CORE_PL_CONF_SPEED_MASK	0x00000018
+#define PCIE_CORE_PL_CONF_LANE_MASK	0x00000006
+#define PCIE_CORE_PL_CONF_LANE_SHIFT	1
+#define PCIE_CORE_RC_CONF_SCC_SHIFT	16
 
 #define ROCKCHIP_PCIE_RPIFR1_INTR_MASK		GENMASK(8, 5)
 #define ROCKCHIP_PCIE_RPIFR1_INTR_SHIFT		5
@@ -472,9 +470,8 @@ static int rockchip_pcie_init_port(struct rockchip_pcie *rockchip)
 
 	for (;;) {
 		status = rockchip_pcie_read(rockchip, PCIE_CLIENT_BASIC_STATUS1);
-		if (((status >> PCIE_CLIENT_LINK_STATUS_SHIFT) &
-		      PCIE_CLIENT_LINK_STATUS_MASK) ==
-		      PCIE_CLIENT_LINK_STATUS_UP) {
+		if ((status & PCIE_CLIENT_LINK_STATUS_MASK) ==
+		    PCIE_CLIENT_LINK_STATUS_UP) {
 			dev_dbg(dev, "PCIe link training gen1 pass!\n");
 			break;
 		}
@@ -490,9 +487,8 @@ static int rockchip_pcie_init_port(struct rockchip_pcie *rockchip)
 	/* Double check gen1 training */
 	if (err) {
 		status = rockchip_pcie_read(rockchip, PCIE_CLIENT_BASIC_STATUS1);
-		err = (((status >> PCIE_CLIENT_LINK_STATUS_SHIFT) &
-			PCIE_CLIENT_LINK_STATUS_MASK) ==
-			PCIE_CLIENT_LINK_STATUS_UP) ? 0 : -ETIMEDOUT;
+		err = ((status & PCIE_CLIENT_LINK_STATUS_MASK) ==
+		       PCIE_CLIENT_LINK_STATUS_UP) ? 0 : -ETIMEDOUT;
 		if (err) {
 			dev_err(dev, "PCIe link training gen1 timeout!\n");
 			return err;
@@ -512,9 +508,8 @@ static int rockchip_pcie_init_port(struct rockchip_pcie *rockchip)
 	timeout = jiffies + msecs_to_jiffies(500);
 	for (;;) {
 		status = rockchip_pcie_read(rockchip, PCIE_CORE_CTRL_MGMT_BASE);
-		if (((status >> PCIE_CORE_PL_CONF_SPEED_SHIFT) &
-		     PCIE_CORE_PL_CONF_SPEED_MASK) ==
-		     PCIE_CORE_PL_CONF_SPEED_5G) {
+		if ((status & PCIE_CORE_PL_CONF_SPEED_MASK) ==
+		    PCIE_CORE_PL_CONF_SPEED_5G) {
 			dev_dbg(dev, "PCIe link training gen2 pass!\n");
 			break;
 		}
@@ -530,17 +525,16 @@ static int rockchip_pcie_init_port(struct rockchip_pcie *rockchip)
 	/* Double check gen2 training */
 	if (err) {
 		status = rockchip_pcie_read(rockchip, PCIE_CORE_CTRL_MGMT_BASE);
-		err = (((status >> PCIE_CORE_PL_CONF_SPEED_SHIFT) &
-			PCIE_CORE_PL_CONF_SPEED_MASK) ==
-			PCIE_CORE_PL_CONF_SPEED_5G) ? 0 : -ETIMEDOUT;
+		err = ((status & PCIE_CORE_PL_CONF_SPEED_MASK) ==
+		       PCIE_CORE_PL_CONF_SPEED_5G) ? 0 : -ETIMEDOUT;
 		if (err)
 			dev_dbg(dev, "PCIe link training gen2 timeout, fall back to gen1!\n");
 	}
 
 	/* Check the final link width from negotiated lane counter from MGMT */
 	status = rockchip_pcie_read(rockchip, PCIE_CORE_CTRL_MGMT_BASE);
-	status =  0x1 << ((status >> PCIE_CORE_PL_CONF_LANE_SHIFT) &
-			   PCIE_CORE_PL_CONF_LANE_MASK);
+	status =  0x1 << ((status & PCIE_CORE_PL_CONF_LANE_MASK) >>
+			  PCIE_CORE_PL_CONF_LANE_MASK);
 	dev_dbg(dev, "current link width is x%d\n", status);
 
 	rockchip_pcie_write(rockchip, ROCKCHIP_VENDOR_ID, PCIE_RC_CONFIG_BASE);

[PATCH 9/9] Move msleeps to address Guenter's comments.

[Bjorn Helgaas]

---
 drivers/pci/host/pcie-rockchip.c |   34 +++++++---------------------------
 1 file changed, 7 insertions(+), 27 deletions(-)

diff --git a/drivers/pci/host/pcie-rockchip.c b/drivers/pci/host/pcie-rockchip.c
index 61b0630..6623598 100644
--- a/drivers/pci/host/pcie-rockchip.c
+++ b/drivers/pci/host/pcie-rockchip.c
@@ -476,23 +476,12 @@ static int rockchip_pcie_init_port(struct rockchip_pcie *rockchip)
 			break;
 		}
 
-		msleep(20);
-
-		if (!time_before(jiffies, timeout)) {
-			err = -ETIMEDOUT;
-			break;
-		}
-	}
-
-	/* Double check gen1 training */
-	if (err) {
-		status = rockchip_pcie_read(rockchip, PCIE_CLIENT_BASIC_STATUS1);
-		err = ((status & PCIE_CLIENT_LINK_STATUS_MASK) ==
-		       PCIE_CLIENT_LINK_STATUS_UP) ? 0 : -ETIMEDOUT;
-		if (err) {
+		if (time_after(jiffies, timeout)) {
 			dev_err(dev, "PCIe link training gen1 timeout!\n");
-			return err;
+			return -ETIMEDOUT;
 		}
+
+		msleep(20);
 	}
 
 	/*
@@ -514,21 +503,12 @@ static int rockchip_pcie_init_port(struct rockchip_pcie *rockchip)
 			break;
 		}
 
-		msleep(20);
-
-		if (!time_before(jiffies, timeout)) {
-			err = -ETIMEDOUT;
+		if (time_after(jiffies, timeout)) {
+			dev_dbg(dev, "PCIe link training gen2 timeout, fall back to gen1!\n");
 			break;
 		}
-	}
 
-	/* Double check gen2 training */
-	if (err) {
-		status = rockchip_pcie_read(rockchip, PCIE_CORE_CTRL_MGMT_BASE);
-		err = ((status & PCIE_CORE_PL_CONF_SPEED_MASK) ==
-		       PCIE_CORE_PL_CONF_SPEED_5G) ? 0 : -ETIMEDOUT;
-		if (err)
-			dev_dbg(dev, "PCIe link training gen2 timeout, fall back to gen1!\n");
+		msleep(20);
 	}
 
 	/* Check the final link width from negotiated lane counter from MGMT */

Re: [PATCH 0/9] PCI: rockchip: Cleanups against v10

[Arnd Bergmann]

On Thursday, September 1, 2016 11:43:52 AM CEST Bjorn Helgaas wrote:
> These are cleanups against 2098142ae87d, the current pci/host-rockchip
> head in my tree.  This is basically the v10 driver posting (it's not
> identical because I had already tweaked a few things and squashed in
> Brian's bug fix).

I looked over the series and everything looks good, I particularly
like the way that 	patches 7 and 8 make the code so much more readable.

	Arnd