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[82.192.45.213]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-47be27b749esm205928155e9.14.2025.12.21.11.12.19 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 21 Dec 2025 11:12:19 -0800 (PST) From: Jernej =?UTF-8?B?xaBrcmFiZWM=?= To: Uwe =?UTF-8?B?S2xlaW5lLUvDtm5pZw==?= , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Chen-Yu Tsai , Samuel Holland , Philipp Zabel , Richard Genoud Cc: Thomas Petazzoni , linux-pwm@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-sunxi@lists.linux.dev, linux-kernel@vger.kernel.org, Richard Genoud Subject: Re: [PATCH v2 0/4] Introduce Allwinner H616 PWM controller Date: Sun, 21 Dec 2025 20:12:18 +0100 Message-ID: <6113404.MhkbZ0Pkbq@jernej-laptop> In-Reply-To: <20251217082504.80226-1-richard.genoud@bootlin.com> References: <20251217082504.80226-1-richard.genoud@bootlin.com> Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Dne sreda, 17. december 2025 ob 09:25:00 Srednjeevropski standardni =C4=8Da= s je Richard Genoud napisal(a): > Allwinner H616 PWM controller is quite different from the A10 one. >=20 > It can drive 6 PWM channels, and like for the A10, each channel has a > bypass that permits to output a clock, bypassing the PWM logic, when > enabled. >=20 > But, the channels are paired 2 by 2, sharing a first set of > MUX/prescaler/gate. > Then, for each channel, there's another prescaler (that will be bypassed > if the bypass is enabled for this channel). >=20 > It looks like that: > _____ ______ ________ > OSC24M --->| | | | | | > APB1 ----->| Mux |--->| Gate |--->| /div_m |-----> PWM_clock_src_xy > |_____| |______| |________| > ________ > | | > +->| /div_k |---> PWM_clock_x > | |________| > | ______ > | | | > +-->| Gate |----> PWM_bypass_clock_x > | |______| > PWM_clock_src_xy -----+ ________ > | | | > +->| /div_k |---> PWM_clock_y > | |________| > | ______ > | | | > +-->| Gate |----> PWM_bypass_clock_y > |______| >=20 > Where xy can be 0/1, 2/3, 4/5 >=20 > PWM_clock_x/y serve for the PWM purpose. > PWM_bypass_clock_x/y serve for the clock-provider purpose. > The common clock framework has been used to manage those clocks. >=20 > This PWM driver serves as a clock-provider for PWM_bypass_clocks. > This is needed for example by the embedded AC300 PHY which clock comes > from PMW5 pin (PB12). No. Drop all clocks related code and make this pure PWM driver, like pwm-su= n4i is. For AC300, AC200 or whatever other device may need clock produced by PW= M, pwm-clock can be used like this: ac300_pwm_clk: ac300-clk { compatible =3D "pwm-clock"; #clock-cells =3D <0>; clock-frequency =3D <24000000>; pinctrl-names =3D "default"; pinctrl-0 =3D <&pwm1_pin>; pwms =3D <&pwm 1 42 0>; }; ac300 { ... clocks =3D <&ac300_pwm_clk>; ... }; Best regards, Jernej >=20 > This series is based onto v6.19-rc1 >=20 > Changes since v1: > - rebase onto v6.19-rc1 > - add missing headers > - remove MODULE_ALIAS (suggested by Krzysztof) > - use sun4i-pwm binding instead of creating a new one (suggested by Krzys= ztof) > - retrieve the parent clocks from the devicetree > - switch num_parents to unsigned int >=20 > Richard Genoud (4): > dt-bindings: pwm: allwinner: add h616 pwm compatible > pwm: sun50i: Add H616 PWM support > arm64: dts: allwinner: h616: add PWM controller > MAINTAINERS: Add entry on Allwinner H616 PWM driver >=20 > .../bindings/pwm/allwinner,sun4i-a10-pwm.yaml | 19 +- > MAINTAINERS | 5 + > .../arm64/boot/dts/allwinner/sun50i-h616.dtsi | 47 + > drivers/pwm/Kconfig | 12 + > drivers/pwm/Makefile | 1 + > drivers/pwm/pwm-sun50i-h616.c | 892 ++++++++++++++++++ > 6 files changed, 975 insertions(+), 1 deletion(-) > create mode 100644 drivers/pwm/pwm-sun50i-h616.c >=20 >=20 > base-commit: 8f0b4cce4481fb22653697cced8d0d04027cb1e8 >=20