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Fri, 25 Mar 2022 04:01:12 -0700 (PDT) Received: from [192.168.1.145] ([207.188.167.132]) by smtp.gmail.com with ESMTPSA id v13-20020adfe28d000000b0020375f27a5asm4914906wri.4.2022.03.25.04.01.11 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Fri, 25 Mar 2022 04:01:11 -0700 (PDT) Message-ID: <6117f51e-d43a-40da-f5a0-7b59c09ac29e@gmail.com> Date: Fri, 25 Mar 2022 12:01:10 +0100 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:91.0) Gecko/20100101 Thunderbird/91.5.0 Subject: Re: [PATCH v4 15/22] arm64: dts: mt8192: Add H264 venc device node Content-Language: en-US To: Allen-KH Cheng , Rob Herring , Krzysztof Kozlowski Cc: Project_Global_Chrome_Upstream_Group@mediatek.com, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-mediatek@lists.infradead.org, Chen-Yu Tsai , Ryder Lee , Hui Liu References: <20220318144534.17996-1-allen-kh.cheng@mediatek.com> <20220318144534.17996-16-allen-kh.cheng@mediatek.com> From: Matthias Brugger In-Reply-To: <20220318144534.17996-16-allen-kh.cheng@mediatek.com> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org On 18/03/2022 15:45, Allen-KH Cheng wrote: > Adds H264 venc node for mt8192 SoC. > > Signed-off-by: Allen-KH Cheng > Reviewed-by: AngeloGioacchino Del Regno Applied thanks > --- > arch/arm64/boot/dts/mediatek/mt8192.dtsi | 23 +++++++++++++++++++++++ > 1 file changed, 23 insertions(+) > > diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi b/arch/arm64/boot/dts/mediatek/mt8192.dtsi > index 4addf6ddd86d..63893779b193 100644 > --- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi > +++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi > @@ -1336,6 +1336,29 @@ > power-domains = <&spm MT8192_POWER_DOMAIN_VENC>; > }; > > + vcodec_enc: vcodec@17020000 { > + compatible = "mediatek,mt8192-vcodec-enc"; > + reg = <0 0x17020000 0 0x2000>; > + iommus = <&iommu0 M4U_PORT_L7_VENC_RCPU>, > + <&iommu0 M4U_PORT_L7_VENC_REC>, > + <&iommu0 M4U_PORT_L7_VENC_BSDMA>, > + <&iommu0 M4U_PORT_L7_VENC_SV_COMV>, > + <&iommu0 M4U_PORT_L7_VENC_RD_COMV>, > + <&iommu0 M4U_PORT_L7_VENC_CUR_LUMA>, > + <&iommu0 M4U_PORT_L7_VENC_CUR_CHROMA>, > + <&iommu0 M4U_PORT_L7_VENC_REF_LUMA>, > + <&iommu0 M4U_PORT_L7_VENC_REF_CHROMA>, > + <&iommu0 M4U_PORT_L7_VENC_SUB_R_LUMA>, > + <&iommu0 M4U_PORT_L7_VENC_SUB_W_LUMA>; > + interrupts = ; > + mediatek,scp = <&scp>; > + power-domains = <&spm MT8192_POWER_DOMAIN_VENC>; > + clocks = <&vencsys CLK_VENC_SET1_VENC>; > + clock-names = "venc-set1"; > + assigned-clocks = <&topckgen CLK_TOP_VENC_SEL>; > + assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D4>; > + }; > + > camsys: clock-controller@1a000000 { > compatible = "mediatek,mt8192-camsys"; > reg = <0 0x1a000000 0 0x1000>;