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a=rsa-sha256; c=relaxed/relaxed; d=ew.tq-group.com; s=dkim; t=1742799731; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=jtdsIlvZFuNXS5m+ytZfrbj/VE0WKhdwUACbuDCbmXo=; b=ZPioefSLN+FlFThMWD0H5hkSLzq2+eFOFR5/Nr1DxIkttSAr16drmLBsreSRcMrylHrIJN TtRuu+Ea4B7HK+cGBVFKmRR03kXt7IZ/6limBz2iId/yblXkYZZhkMiHF8+kJANHgEX9bH XVEUrl7EOLukSw6jseg6QCeYM4aZGN68IlYSrdx3sJF2ZQbW9WbvY0GIZ7puYCCEb6dCIO Kzp3PEoHSNBdRZwFkhtV+fwvWH8LWZWyiIMqh/8MLxM/NFUgJXG5aRwyrZPRjY/lq3L4Ep alMs13rW53+XkfDpLEYMCCF4Wf6ZRAA0tqrMfLFleLulmUWb77oEmPg4Lw2wFw== From: Alexander Stein To: linux-arm-kernel@lists.infradead.org, dri-devel@lists.freedesktop.org Cc: Marek Vasut , Boris Brezillon , Conor Dooley , David Airlie , Fabio Estevam , Krzysztof Kozlowski , Liviu Dudau , Maarten Lankhorst , Maxime Ripard , Pengutronix Kernel Team , Philipp Zabel , Rob Herring , Sascha Hauer , Sebastian Reichel , Shawn Guo , Simona Vetter , Steven Price , Thomas Zimmermann , devicetree@vger.kernel.org, dri-devel@lists.freedesktop.org, imx@lists.linux.dev, Marek Vasut Subject: Re: [PATCH v2 9/9] arm64: dts: imx95: Describe Mali G310 GPU Date: Mon, 24 Mar 2025 08:02:06 +0100 Message-ID: <6144881.lOV4Wx5bFT@steina-w> Organization: TQ-Systems GmbH In-Reply-To: <20250321200625.132494-10-marex@denx.de> References: <20250321200625.132494-1-marex@denx.de> <20250321200625.132494-10-marex@denx.de> Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="iso-8859-1" X-Last-TLS-Session-Version: TLSv1.3 Am Freitag, 21. M=E4rz 2025, 21:05:59 CET schrieb Marek Vasut: > The instance of the GPU populated in i.MX95 is the G310, > describe this GPU in the DT. Include description of the > GPUMIX block controller, which can be operated as a simple > reset. Include dummy GPU voltage regulator and OPP tables. >=20 > Signed-off-by: Marek Vasut > --- > Cc: Boris Brezillon > Cc: Conor Dooley > Cc: David Airlie > Cc: Fabio Estevam > Cc: Krzysztof Kozlowski > Cc: Liviu Dudau > Cc: Maarten Lankhorst > Cc: Maxime Ripard > Cc: Pengutronix Kernel Team > Cc: Philipp Zabel > Cc: Rob Herring > Cc: Sascha Hauer > Cc: Sebastian Reichel > Cc: Shawn Guo > Cc: Simona Vetter > Cc: Steven Price > Cc: Thomas Zimmermann > Cc: devicetree@vger.kernel.org > Cc: dri-devel@lists.freedesktop.org > Cc: imx@lists.linux.dev > Cc: linux-arm-kernel@lists.infradead.org > --- > V2: - Drop regulator-{always,boot}-on from fixed-gpu-reg regulator > - Keep the GPU and GPUMIX always enabled > - Switch from fsl, to nxp, vendor prefix > - Fix opp_table to opp-table > - Describe IMX95_CLK_GPUAPB as coregroup clock > - Sort interrupts by their names to match bindings > --- > arch/arm64/boot/dts/freescale/imx95.dtsi | 58 ++++++++++++++++++++++++ > 1 file changed, 58 insertions(+) >=20 > diff --git a/arch/arm64/boot/dts/freescale/imx95.dtsi b/arch/arm64/boot/d= ts/freescale/imx95.dtsi > index 9bb26b466a061..3acdbd7fd4eee 100644 > --- a/arch/arm64/boot/dts/freescale/imx95.dtsi > +++ b/arch/arm64/boot/dts/freescale/imx95.dtsi > @@ -249,6 +249,35 @@ dummy: clock-dummy { > clock-output-names =3D "dummy"; > }; > =20 > + gpu_fixed_reg: fixed-gpu-reg { > + compatible =3D "regulator-fixed"; > + regulator-min-microvolt =3D <920000>; > + regulator-max-microvolt =3D <920000>; > + regulator-name =3D "vdd_gpu"; > + }; > + > + gpu_opp_table: opp-table { > + compatible =3D "operating-points-v2"; > + > + opp-500000000 { > + opp-hz =3D /bits/ 64 <500000000>; > + opp-hz-real =3D /bits/ 64 <500000000>; > + opp-microvolt =3D <920000>; > + }; > + > + opp-800000000 { > + opp-hz =3D /bits/ 64 <800000000>; > + opp-hz-real =3D /bits/ 64 <800000000>; > + opp-microvolt =3D <920000>; > + }; > + > + opp-1000000000 { > + opp-hz =3D /bits/ 64 <1000000000>; > + opp-hz-real =3D /bits/ 64 <1000000000>; > + opp-microvolt =3D <920000>; > + }; > + }; > + > clk_ext1: clock-ext1 { > compatible =3D "fixed-clock"; > #clock-cells =3D <0>; > @@ -1890,6 +1919,35 @@ netc_emdio: mdio@0,0 { > }; > }; > =20 > + gpu_blk_ctrl: reset-controller@4d810000 { > + compatible =3D "nxp,imx95-gpu-blk-ctrl"; > + reg =3D <0x0 0x4d810000 0x0 0xc>; > + #reset-cells =3D <1>; > + clocks =3D <&scmi_clk IMX95_CLK_GPUAPB>; > + assigned-clocks =3D <&scmi_clk IMX95_CLK_GPUAPB>; > + assigned-clock-parents =3D <&scmi_clk IMX95_CLK_SYSPLL1_PFD1_DIV2>; > + assigned-clock-rates =3D <133333333>; > + power-domains =3D <&scmi_devpd IMX95_PD_GPU>; > + }; With the SM release lf-6.12.3-1.0.0 AP does not have any access to this BLK_CTRL anymore. See [1] Best regards, Alexander [1] https://github.com/nxp-imx/imx-sm/blob/master/sm/doc/rn_cl.md#sm-184-de= assert-the-gpu-reset-when-the-gpumix-is-powered-up-rn_detail_sm_184 > + > + gpu: gpu@4d900000 { > + compatible =3D "nxp,imx95-mali", "arm,mali-valhall-csf"; > + reg =3D <0 0x4d900000 0 0x480000>; > + clocks =3D <&scmi_clk IMX95_CLK_GPU>, <&scmi_clk IMX95_CLK_GPUAPB>; > + clock-names =3D "core", "coregroup"; > + interrupts =3D , > + , > + ; > + interrupt-names =3D "job", "mmu", "gpu"; > + mali-supply =3D <&gpu_fixed_reg>; > + operating-points-v2 =3D <&gpu_opp_table>; > + power-domains =3D <&scmi_devpd IMX95_PD_GPU>, <&scmi_perf IMX95_PERF_= GPU>; > + power-domain-names =3D "mix", "perf"; > + resets =3D <&gpu_blk_ctrl 0>; > + #cooling-cells =3D <2>; > + dynamic-power-coefficient =3D <1013>; > + }; > + > ddr-pmu@4e090dc0 { > compatible =3D "fsl,imx95-ddr-pmu", "fsl,imx93-ddr-pmu"; > reg =3D <0x0 0x4e090dc0 0x0 0x200>; >=20 =2D-=20 TQ-Systems GmbH | M=FChlstra=DFe 2, Gut Delling | 82229 Seefeld, Germany Amtsgericht M=FCnchen, HRB 105018 Gesch=E4ftsf=FChrer: Detlef Schneider, R=FCdiger Stahl, Stefan Schneider http://www.tq-group.com/