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[98.183.112.25]) by smtp.gmail.com with ESMTPSA id 586e51a60fabf-28c7925cf54sm3075640fac.18.2024.10.24.07.43.02 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Thu, 24 Oct 2024 07:43:04 -0700 (PDT) Message-ID: <6162ea7d-40d6-4a21-96e5-7f851bc587dc@baylibre.com> Date: Thu, 24 Oct 2024 09:43:02 -0500 Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v7 2/8] dt-bindings: iio: dac: adi-axi-dac: add ad3552r axi variant To: =?UTF-8?Q?Nuno_S=C3=A1?= , Angelo Dureghello , Conor Dooley Cc: =?UTF-8?Q?Nuno_S=C3=A1?= , Lars-Peter Clausen , Michael Hennerich , Jonathan Cameron , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Olivier Moysan , linux-iio@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Mark Brown References: <20241021-wip-bl-ad3552r-axi-v0-iio-testing-v7-0-969694f53c5d@baylibre.com> <20241021-wip-bl-ad3552r-axi-v0-iio-testing-v7-2-969694f53c5d@baylibre.com> <20241022-flagpole-subject-51e68e81e948@spud> <6c2f188fc04ea957c842fe595951039244c43b7e.camel@gmail.com> Content-Language: en-US From: David Lechner In-Reply-To: <6c2f188fc04ea957c842fe595951039244c43b7e.camel@gmail.com> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit On 10/24/24 7:37 AM, Nuno Sá wrote: > On Thu, 2024-10-24 at 11:28 +0200, Angelo Dureghello wrote: >> Hi Conor, >> >> On 22.10.2024 18:22, Conor Dooley wrote: >>> On Mon, Oct 21, 2024 at 02:40:12PM +0200, Angelo Dureghello wrote: >>>> From: Angelo Dureghello >>>> >>>> Add a new compatible and related bindigns for the fpga-based >>>> "ad3552r" AXI IP core, a variant of the generic AXI DAC IP. >>>> >>>> The AXI "ad3552r" IP is a very similar HDL (fpga) variant of the >>>> generic AXI "DAC" IP, intended to control ad3552r and similar chips, >>>> mainly to reach high speed transfer rates using a QSPI DDR >>>> (dobule-data-rate) interface. >>>> >>>> The ad3552r device is defined as a child of the AXI DAC, that in >>>> this case is acting as an SPI controller. >>>> >>>> Note, #io-backend is present because it is possible (in theory anyway) >>>> to use a separate controller for the control path than that used >>>> for the datapath. >>>> >>>> Signed-off-by: Angelo Dureghello >>>> --- >>>>  .../devicetree/bindings/iio/dac/adi,axi-dac.yaml   | 69 +++++++++++++++++++++- >>>>  1 file changed, 66 insertions(+), 3 deletions(-) >>>> >>>> diff --git a/Documentation/devicetree/bindings/iio/dac/adi,axi-dac.yaml >>>> b/Documentation/devicetree/bindings/iio/dac/adi,axi-dac.yaml >>>> index a55e9bfc66d7..0aabb210f26d 100644 >>>> --- a/Documentation/devicetree/bindings/iio/dac/adi,axi-dac.yaml >>>> +++ b/Documentation/devicetree/bindings/iio/dac/adi,axi-dac.yaml >>>> @@ -19,11 +19,13 @@ description: | >>>>    memory via DMA into the DAC. >>>>   >>>>    https://wiki.analog.com/resources/fpga/docs/axi_dac_ip >>>> +  https://analogdevicesinc.github.io/hdl/library/axi_ad3552r/index.html >>>>   >>>>  properties: >>>>    compatible: >>>>      enum: >>>>        - adi,axi-dac-9.1.b >>>> +      - adi,axi-ad3552r >>>>   >>>>    reg: >>>>      maxItems: 1 >>>> @@ -36,7 +38,12 @@ properties: >>>>        - const: tx >>>>   >>>>    clocks: >>>> -    maxItems: 1 >>>> +    minItems: 1 >>>> +    maxItems: 2 >>>> + >>>> +  clock-names: >>>> +    minItems: 1 >>>> +    maxItems: 2 >>>>   >>>>    '#io-backend-cells': >>>>      const: 0 >>>> @@ -47,7 +54,31 @@ required: >>>>    - reg >>>>    - clocks >>>>   >>>> -additionalProperties: false >>>> +allOf: >>>> +  - if: >>>> +      properties: >>>> +        compatible: >>>> +          contains: >>>> +            const: adi,axi-ad3552r >>>> +    then: >>>> +      $ref: /schemas/spi/spi-controller.yaml# >>>> +      properties: >>>> +        clocks: >>>> +          minItems: 2 >>>> +          maxItems: 2 >>> >>> Is this maxItems required? It matches the outer maximum. >>> >>>> +        clock-names: >>>> +          items: >>>> +            - const: s_axi_aclk >>>> +            - const: dac_clk >>> >>> The names are the same in both cases, you can move the definitions >>> outside of the if/then/else stuff and only constrain it here. >>> >> thanks, could you maybe have a look if it's ok now ? >> (maxItems not needed for a const list) >> >>   clocks: >>     minItems: 1 >>     maxItems: 2 >> >>   clock-names: >>     items: >>       - const: s_axi_aclk >>       - const: dac_clk >>     minItems: 1 >> >>   '#io-backend-cells': >>     const: 0 >> >> required: >>   - compatible >>   - dmas >>   - reg >>   - clocks >> >> allOf: >>   - if: >>       properties: >>         compatible: >>           contains: >>             const: adi,axi-ad3552r >>     then: >>       $ref: /schemas/spi/spi-controller.yaml# >>       properties: >>         clocks: >>           minItems: 2 >>         clock-names: >>           minItems: 2 For this one, I think we also need: required: - clock-names >>     else: >>       properties: >>         clocks: >>           maxItems: 1 >>         clock-names: >>           maxItems: 1 > > I guess in this case it could even be clock-names: false. One does not make much > sense. > > - Nuno Sá > >