[PATCH 00/14] Multiple addition and improvement to ipq8064 gcc

[PATCH 00/14] Multiple addition and improvement to ipq8064 gcc

[Ansuel Smith]

This is an attempt in making the ipq8064 SoC actually usable. Currently
many feature are missing for this SoC and devs user off-the-tree patches
to make it work (example patch for missing clock, patch for cpufreq
driver, patch to add missing node in the dts)

I notice there was some work in modernizing the gcc driver for other
qcom target but this wasn't done for ipq806x. This does exactly this, we
drop any parent_names stuff and we switch to the parent_data way. We
also drop the pxo and cxo source clk from gcc driver and we refer to the
dts for it.

This also add all the missing feature for the nss cores and the
cryptoengine in them. It does also introduce the required flags to make
the RPM actually work and NOT reject any command. There was an attempt
in declaring these clock as core clock in the dts but this ends up in no
serial as the kernel makes these clock not accessible. We just want to
make the kernel NOT disable them if unused nothing more.

At the end we update the ipq8064 dtsi to add the pxo and cxo tag and
declare them in gcc and also fix a problem with tsens probe.

Ansuel Smith (14):
  dt-bindings: clock: Document qcom,gcc-ipq8064 binding
  drivers: clk: qcom: gcc-ipq806x: fix wrong naming for
    gcc_pxo_pll8_pll0
  drivers: clk: qcom: gcc-ipq806x: convert parent_names to parent_data
  drivers: clk: qcom: gcc-ipq806x: use ARRAY_SIZE for num_parents
  drivers: clk: qcom: gcc-ipq806x: drop hardcoded pxo and cxo source clk
  drivers: clk: qcom: gcc-ipq806x: use parent_hws where possible
  drivers: clk: qcom: gcc-ipq806x: add additional freq nss cores
  drivers: clk: qcom: gcc-ipq806x: add unusued flag for critical clock
  drivers: clk: qcom: gcc-ipq806x: add additional freq for sdc table
  dt-bindings: clock: add ipq8064 ce5 clk define
  drivers: clk: qcom: gcc-ipq806x: add CryptoEngine clocks
  dt-bindings: reset: add ipq8064 ce5 resets
  drivers: clk: qcom: gcc-ipq806x: add CryptoEngine resets
  ARM: dts: qcom: Add syscon and cxo/pxo clock to gcc node for ipq8064

 .../bindings/clock/qcom,gcc-ipq8064.yaml      |  67 ++
 arch/arm/boot/dts/qcom-ipq8064.dtsi           |   8 +-
 drivers/clk/qcom/gcc-ipq806x.c                | 652 +++++++++++++-----
 include/dt-bindings/clock/qcom,gcc-ipq806x.h  |   5 +-
 include/dt-bindings/reset/qcom,gcc-ipq806x.h  |   5 +
 5 files changed, 567 insertions(+), 170 deletions(-)
 create mode 100644 Documentation/devicetree/bindings/clock/qcom,gcc-ipq8064.yaml

-- 
2.33.1

[PATCH 01/14] dt-bindings: clock: Document qcom,gcc-ipq8064 binding

[Ansuel Smith]

Document qcom,gcc-ipq8064 binding needed to declare pxo and cxo source
clocks. The gcc node is also used by the tsens driver, already Documented,
to get the calib nvmem cells and the base reg from gcc.

Signed-off-by: Ansuel Smith <ansuelsmth@gmail.com>
---
 .../bindings/clock/qcom,gcc-ipq8064.yaml      | 67 +++++++++++++++++++
 1 file changed, 67 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/clock/qcom,gcc-ipq8064.yaml

diff --git a/Documentation/devicetree/bindings/clock/qcom,gcc-ipq8064.yaml b/Documentation/devicetree/bindings/clock/qcom,gcc-ipq8064.yaml
new file mode 100644
index 000000000000..2dc254fdf161
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/qcom,gcc-ipq8064.yaml
@@ -0,0 +1,67 @@
+# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/clock/qcom,gcc-ipq8064.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Qualcomm Global Clock & Reset Controller Binding for IPQ8064
+
+maintainers:
+  - Ansuel Smith <ansuelsmth@gmail.com>
+
+description: |
+  Qualcomm global clock control module which supports the clocks, resets and
+  power domains on IPQ8064.
+
+properties:
+  compatible:
+    const: qcom,gcc-ipq8064
+
+  '#clock-cells':
+    const: 1
+
+  '#reset-cells':
+    const: 1
+
+  '#power-domain-cells':
+    const: 1
+
+  reg:
+    maxItems: 1
+
+  clocks:
+    items:
+      - description: PXO source
+      - description: CX0 source
+
+  clock-names:
+    items:
+      - const: pxo
+      - const: cxo
+
+required:
+  - compatible
+  - reg
+  - '#clock-cells'
+  - '#reset-cells'
+  - '#power-domain-cells'
+  - clocks
+  - clock-names
+
+additionalProperties: true
+
+examples:
+  - |
+    gcc: clock-controller@900000 {
+      compatible = "qcom,gcc-ipq8064", "syscon";
+      reg = <0x00900000 0x4000>;
+      clocks = <&pxo_board>, <&cxo_board>;
+      clock-names = "pxo", "cxo";
+      #clock-cells = <1>;
+      #reset-cells = <1>;
+      #power-domain-cells = <1>;
+
+      /* Tsens node definition */
+
+    };
+...
-- 
2.33.1

[PATCH 02/14] drivers: clk: qcom: gcc-ipq806x: fix wrong naming for gcc_pxo_pll8_pll0

[Ansuel Smith]

Parent gcc_pxo_pll8_pll0 had the parent definition and parent map
swapped. Fix this naming error.

Signed-off-by: Ansuel Smith <ansuelsmth@gmail.com>
---
 drivers/clk/qcom/gcc-ipq806x.c | 20 ++++++++++----------
 1 file changed, 10 insertions(+), 10 deletions(-)

diff --git a/drivers/clk/qcom/gcc-ipq806x.c b/drivers/clk/qcom/gcc-ipq806x.c
index d6b7adb4be38..34cddf461dba 100644
--- a/drivers/clk/qcom/gcc-ipq806x.c
+++ b/drivers/clk/qcom/gcc-ipq806x.c
@@ -291,13 +291,13 @@ static const char * const gcc_pxo_pll3[] = {
 	"pll3",
 };
 
-static const struct parent_map gcc_pxo_pll8_pll0[] = {
+static const struct parent_map gcc_pxo_pll8_pll0_map[] = {
 	{ P_PXO, 0 },
 	{ P_PLL8, 3 },
 	{ P_PLL0, 2 }
 };
 
-static const char * const gcc_pxo_pll8_pll0_map[] = {
+static const char * const gcc_pxo_pll8_pll0[] = {
 	"pxo",
 	"pll8_vote",
 	"pll0_vote",
@@ -1993,7 +1993,7 @@ static struct clk_rcg usb30_master_clk_src = {
 	},
 	.s = {
 		.src_sel_shift = 0,
-		.parent_map = gcc_pxo_pll8_pll0,
+		.parent_map = gcc_pxo_pll8_pll0_map,
 	},
 	.freq_tbl = clk_tbl_usb30_master,
 	.clkr = {
@@ -2001,7 +2001,7 @@ static struct clk_rcg usb30_master_clk_src = {
 		.enable_mask = BIT(11),
 		.hw.init = &(struct clk_init_data){
 			.name = "usb30_master_ref_src",
-			.parent_names = gcc_pxo_pll8_pll0_map,
+			.parent_names = gcc_pxo_pll8_pll0,
 			.num_parents = 3,
 			.ops = &clk_rcg_ops,
 			.flags = CLK_SET_RATE_GATE,
@@ -2063,7 +2063,7 @@ static struct clk_rcg usb30_utmi_clk = {
 	},
 	.s = {
 		.src_sel_shift = 0,
-		.parent_map = gcc_pxo_pll8_pll0,
+		.parent_map = gcc_pxo_pll8_pll0_map,
 	},
 	.freq_tbl = clk_tbl_usb30_utmi,
 	.clkr = {
@@ -2071,7 +2071,7 @@ static struct clk_rcg usb30_utmi_clk = {
 		.enable_mask = BIT(11),
 		.hw.init = &(struct clk_init_data){
 			.name = "usb30_utmi_clk",
-			.parent_names = gcc_pxo_pll8_pll0_map,
+			.parent_names = gcc_pxo_pll8_pll0,
 			.num_parents = 3,
 			.ops = &clk_rcg_ops,
 			.flags = CLK_SET_RATE_GATE,
@@ -2133,7 +2133,7 @@ static struct clk_rcg usb_hs1_xcvr_clk_src = {
 	},
 	.s = {
 		.src_sel_shift = 0,
-		.parent_map = gcc_pxo_pll8_pll0,
+		.parent_map = gcc_pxo_pll8_pll0_map,
 	},
 	.freq_tbl = clk_tbl_usb,
 	.clkr = {
@@ -2141,7 +2141,7 @@ static struct clk_rcg usb_hs1_xcvr_clk_src = {
 		.enable_mask = BIT(11),
 		.hw.init = &(struct clk_init_data){
 			.name = "usb_hs1_xcvr_src",
-			.parent_names = gcc_pxo_pll8_pll0_map,
+			.parent_names = gcc_pxo_pll8_pll0,
 			.num_parents = 3,
 			.ops = &clk_rcg_ops,
 			.flags = CLK_SET_RATE_GATE,
@@ -2197,7 +2197,7 @@ static struct clk_rcg usb_fs1_xcvr_clk_src = {
 	},
 	.s = {
 		.src_sel_shift = 0,
-		.parent_map = gcc_pxo_pll8_pll0,
+		.parent_map = gcc_pxo_pll8_pll0_map,
 	},
 	.freq_tbl = clk_tbl_usb,
 	.clkr = {
@@ -2205,7 +2205,7 @@ static struct clk_rcg usb_fs1_xcvr_clk_src = {
 		.enable_mask = BIT(11),
 		.hw.init = &(struct clk_init_data){
 			.name = "usb_fs1_xcvr_src",
-			.parent_names = gcc_pxo_pll8_pll0_map,
+			.parent_names = gcc_pxo_pll8_pll0,
 			.num_parents = 3,
 			.ops = &clk_rcg_ops,
 			.flags = CLK_SET_RATE_GATE,
-- 
2.33.1

[PATCH 03/14] drivers: clk: qcom: gcc-ipq806x: convert parent_names to parent_data

[Ansuel Smith]

Convert parent_names to parent_data to modernize the driver.

Signed-off-by: Ansuel Smith <ansuelsmth@gmail.com>
---
 drivers/clk/qcom/gcc-ipq806x.c | 300 ++++++++++++++++++++-------------
 1 file changed, 187 insertions(+), 113 deletions(-)

diff --git a/drivers/clk/qcom/gcc-ipq806x.c b/drivers/clk/qcom/gcc-ipq806x.c
index 34cddf461dba..cbacd56f52d4 100644
--- a/drivers/clk/qcom/gcc-ipq806x.c
+++ b/drivers/clk/qcom/gcc-ipq806x.c
@@ -35,7 +35,9 @@ static struct clk_pll pll0 = {
 	.status_bit = 16,
 	.clkr.hw.init = &(struct clk_init_data){
 		.name = "pll0",
-		.parent_names = (const char *[]){ "pxo" },
+		.parent_data = &(const struct clk_parent_data){
+			.fw_name = "pxo",
+		},
 		.num_parents = 1,
 		.ops = &clk_pll_ops,
 	},
@@ -46,7 +48,9 @@ static struct clk_regmap pll0_vote = {
 	.enable_mask = BIT(0),
 	.hw.init = &(struct clk_init_data){
 		.name = "pll0_vote",
-		.parent_names = (const char *[]){ "pll0" },
+		.parent_data = &(const struct clk_parent_data){
+			.hw = &pll0.clkr.hw,
+		},
 		.num_parents = 1,
 		.ops = &clk_pll_vote_ops,
 	},
@@ -62,7 +66,9 @@ static struct clk_pll pll3 = {
 	.status_bit = 16,
 	.clkr.hw.init = &(struct clk_init_data){
 		.name = "pll3",
-		.parent_names = (const char *[]){ "pxo" },
+		.parent_data = &(const struct clk_parent_data){
+			.fw_name = "pxo",
+		},
 		.num_parents = 1,
 		.ops = &clk_pll_ops,
 	},
@@ -89,7 +95,9 @@ static struct clk_pll pll8 = {
 	.status_bit = 16,
 	.clkr.hw.init = &(struct clk_init_data){
 		.name = "pll8",
-		.parent_names = (const char *[]){ "pxo" },
+		.parent_data = &(const struct clk_parent_data){
+			.fw_name = "pxo",
+		},
 		.num_parents = 1,
 		.ops = &clk_pll_ops,
 	},
@@ -100,7 +108,9 @@ static struct clk_regmap pll8_vote = {
 	.enable_mask = BIT(8),
 	.hw.init = &(struct clk_init_data){
 		.name = "pll8_vote",
-		.parent_names = (const char *[]){ "pll8" },
+		.parent_data = &(const struct clk_parent_data){
+			.hw = &pll8.clkr.hw,
+		},
 		.num_parents = 1,
 		.ops = &clk_pll_vote_ops,
 	},
@@ -123,7 +133,9 @@ static struct hfpll_data hfpll0_data = {
 static struct clk_hfpll hfpll0 = {
 	.d = &hfpll0_data,
 	.clkr.hw.init = &(struct clk_init_data){
-		.parent_names = (const char *[]){ "pxo" },
+		.parent_data = &(const struct clk_parent_data){
+			.fw_name = "pxo",
+		},
 		.num_parents = 1,
 		.name = "hfpll0",
 		.ops = &clk_ops_hfpll,
@@ -149,7 +161,9 @@ static struct hfpll_data hfpll1_data = {
 static struct clk_hfpll hfpll1 = {
 	.d = &hfpll1_data,
 	.clkr.hw.init = &(struct clk_init_data){
-		.parent_names = (const char *[]){ "pxo" },
+		.parent_data = &(const struct clk_parent_data){
+			.fw_name = "pxo",
+		},
 		.num_parents = 1,
 		.name = "hfpll1",
 		.ops = &clk_ops_hfpll,
@@ -175,7 +189,9 @@ static struct hfpll_data hfpll_l2_data = {
 static struct clk_hfpll hfpll_l2 = {
 	.d = &hfpll_l2_data,
 	.clkr.hw.init = &(struct clk_init_data){
-		.parent_names = (const char *[]){ "pxo" },
+		.parent_data = &(const struct clk_parent_data){
+			.fw_name = "pxo",
+		},
 		.num_parents = 1,
 		.name = "hfpll_l2",
 		.ops = &clk_ops_hfpll,
@@ -194,7 +210,9 @@ static struct clk_pll pll14 = {
 	.status_bit = 16,
 	.clkr.hw.init = &(struct clk_init_data){
 		.name = "pll14",
-		.parent_names = (const char *[]){ "pxo" },
+		.parent_data = &(const struct clk_parent_data){
+			.fw_name = "pxo",
+		},
 		.num_parents = 1,
 		.ops = &clk_pll_ops,
 	},
@@ -205,7 +223,9 @@ static struct clk_regmap pll14_vote = {
 	.enable_mask = BIT(14),
 	.hw.init = &(struct clk_init_data){
 		.name = "pll14_vote",
-		.parent_names = (const char *[]){ "pll14" },
+		.parent_data = &(const struct clk_parent_data){
+			.hw = &pll14.clkr.hw,
+		},
 		.num_parents = 1,
 		.ops = &clk_pll_vote_ops,
 	},
@@ -238,7 +258,9 @@ static struct clk_pll pll18 = {
 	.freq_tbl = pll18_freq_tbl,
 	.clkr.hw.init = &(struct clk_init_data){
 		.name = "pll18",
-		.parent_names = (const char *[]){ "pxo" },
+		.parent_data = &(const struct clk_parent_data){
+			.fw_name = "pxo",
+		},
 		.num_parents = 1,
 		.ops = &clk_pll_ops,
 	},
@@ -259,9 +281,9 @@ static const struct parent_map gcc_pxo_pll8_map[] = {
 	{ P_PLL8, 3 }
 };
 
-static const char * const gcc_pxo_pll8[] = {
-	"pxo",
-	"pll8_vote",
+static const struct clk_parent_data gcc_pxo_pll8[] = {
+	{ .fw_name = "pxo" },
+	{ .hw = &pll8_vote.hw },
 };
 
 static const struct parent_map gcc_pxo_pll8_cxo_map[] = {
@@ -270,10 +292,10 @@ static const struct parent_map gcc_pxo_pll8_cxo_map[] = {
 	{ P_CXO, 5 }
 };
 
-static const char * const gcc_pxo_pll8_cxo[] = {
-	"pxo",
-	"pll8_vote",
-	"cxo",
+static const struct clk_parent_data gcc_pxo_pll8_cxo[] = {
+	{ .fw_name = "pxo" },
+	{ .hw = &pll8_vote.hw },
+	{ .fw_name = "cxo" },
 };
 
 static const struct parent_map gcc_pxo_pll3_map[] = {
@@ -286,9 +308,9 @@ static const struct parent_map gcc_pxo_pll3_sata_map[] = {
 	{ P_PLL3, 6 }
 };
 
-static const char * const gcc_pxo_pll3[] = {
-	"pxo",
-	"pll3",
+static const struct clk_parent_data gcc_pxo_pll3[] = {
+	{ .fw_name = "pxo" },
+	{ .hw = &pll3.clkr.hw },
 };
 
 static const struct parent_map gcc_pxo_pll8_pll0_map[] = {
@@ -297,10 +319,10 @@ static const struct parent_map gcc_pxo_pll8_pll0_map[] = {
 	{ P_PLL0, 2 }
 };
 
-static const char * const gcc_pxo_pll8_pll0[] = {
-	"pxo",
-	"pll8_vote",
-	"pll0_vote",
+static const struct clk_parent_data gcc_pxo_pll8_pll0[] = {
+	{ .fw_name = "pxo" },
+	{ .hw = &pll8_vote.hw },
+	{ .hw = &pll0_vote.hw },
 };
 
 static const struct parent_map gcc_pxo_pll8_pll14_pll18_pll0_map[] = {
@@ -311,12 +333,12 @@ static const struct parent_map gcc_pxo_pll8_pll14_pll18_pll0_map[] = {
 	{ P_PLL18, 1 }
 };
 
-static const char * const gcc_pxo_pll8_pll14_pll18_pll0[] = {
-	"pxo",
-	"pll8_vote",
-	"pll0_vote",
-	"pll14",
-	"pll18",
+static const struct clk_parent_data gcc_pxo_pll8_pll14_pll18_pll0[] = {
+	{ .fw_name = "pxo" },
+	{ .hw = &pll8_vote.hw },
+	{ .hw = &pll0_vote.hw },
+	{ .hw = &pll14.clkr.hw },
+	{ .hw = &pll18.clkr.hw },
 };
 
 static struct freq_tbl clk_tbl_gsbi_uart[] = {
@@ -362,7 +384,7 @@ static struct clk_rcg gsbi1_uart_src = {
 		.enable_mask = BIT(11),
 		.hw.init = &(struct clk_init_data){
 			.name = "gsbi1_uart_src",
-			.parent_names = gcc_pxo_pll8,
+			.parent_data = gcc_pxo_pll8,
 			.num_parents = 2,
 			.ops = &clk_rcg_ops,
 			.flags = CLK_SET_PARENT_GATE,
@@ -378,8 +400,8 @@ static struct clk_branch gsbi1_uart_clk = {
 		.enable_mask = BIT(9),
 		.hw.init = &(struct clk_init_data){
 			.name = "gsbi1_uart_clk",
-			.parent_names = (const char *[]){
-				"gsbi1_uart_src",
+			.parent_data = &(const struct clk_parent_data){
+				.hw = &gsbi1_uart_src.clkr.hw,
 			},
 			.num_parents = 1,
 			.ops = &clk_branch_ops,
@@ -413,7 +435,7 @@ static struct clk_rcg gsbi2_uart_src = {
 		.enable_mask = BIT(11),
 		.hw.init = &(struct clk_init_data){
 			.name = "gsbi2_uart_src",
-			.parent_names = gcc_pxo_pll8,
+			.parent_data = gcc_pxo_pll8,
 			.num_parents = 2,
 			.ops = &clk_rcg_ops,
 			.flags = CLK_SET_PARENT_GATE,
@@ -429,8 +451,8 @@ static struct clk_branch gsbi2_uart_clk = {
 		.enable_mask = BIT(9),
 		.hw.init = &(struct clk_init_data){
 			.name = "gsbi2_uart_clk",
-			.parent_names = (const char *[]){
-				"gsbi2_uart_src",
+			.parent_data = &(const struct clk_parent_data){
+				.hw = &gsbi2_uart_src.clkr.hw,
 			},
 			.num_parents = 1,
 			.ops = &clk_branch_ops,
@@ -464,7 +486,7 @@ static struct clk_rcg gsbi4_uart_src = {
 		.enable_mask = BIT(11),
 		.hw.init = &(struct clk_init_data){
 			.name = "gsbi4_uart_src",
-			.parent_names = gcc_pxo_pll8,
+			.parent_data = gcc_pxo_pll8,
 			.num_parents = 2,
 			.ops = &clk_rcg_ops,
 			.flags = CLK_SET_PARENT_GATE,
@@ -480,8 +502,8 @@ static struct clk_branch gsbi4_uart_clk = {
 		.enable_mask = BIT(9),
 		.hw.init = &(struct clk_init_data){
 			.name = "gsbi4_uart_clk",
-			.parent_names = (const char *[]){
-				"gsbi4_uart_src",
+			.parent_data = &(const struct clk_parent_data){
+				.hw = &gsbi4_uart_src.clkr.hw,
 			},
 			.num_parents = 1,
 			.ops = &clk_branch_ops,
@@ -515,7 +537,7 @@ static struct clk_rcg gsbi5_uart_src = {
 		.enable_mask = BIT(11),
 		.hw.init = &(struct clk_init_data){
 			.name = "gsbi5_uart_src",
-			.parent_names = gcc_pxo_pll8,
+			.parent_data = gcc_pxo_pll8,
 			.num_parents = 2,
 			.ops = &clk_rcg_ops,
 			.flags = CLK_SET_PARENT_GATE,
@@ -531,8 +553,8 @@ static struct clk_branch gsbi5_uart_clk = {
 		.enable_mask = BIT(9),
 		.hw.init = &(struct clk_init_data){
 			.name = "gsbi5_uart_clk",
-			.parent_names = (const char *[]){
-				"gsbi5_uart_src",
+			.parent_data = &(const struct clk_parent_data){
+				.hw = &gsbi5_uart_src.clkr.hw,
 			},
 			.num_parents = 1,
 			.ops = &clk_branch_ops,
@@ -566,7 +588,7 @@ static struct clk_rcg gsbi6_uart_src = {
 		.enable_mask = BIT(11),
 		.hw.init = &(struct clk_init_data){
 			.name = "gsbi6_uart_src",
-			.parent_names = gcc_pxo_pll8,
+			.parent_data = gcc_pxo_pll8,
 			.num_parents = 2,
 			.ops = &clk_rcg_ops,
 			.flags = CLK_SET_PARENT_GATE,
@@ -582,8 +604,8 @@ static struct clk_branch gsbi6_uart_clk = {
 		.enable_mask = BIT(9),
 		.hw.init = &(struct clk_init_data){
 			.name = "gsbi6_uart_clk",
-			.parent_names = (const char *[]){
-				"gsbi6_uart_src",
+			.parent_data = &(const struct clk_parent_data){
+				.hw = &gsbi6_uart_src.clkr.hw,
 			},
 			.num_parents = 1,
 			.ops = &clk_branch_ops,
@@ -617,7 +639,7 @@ static struct clk_rcg gsbi7_uart_src = {
 		.enable_mask = BIT(11),
 		.hw.init = &(struct clk_init_data){
 			.name = "gsbi7_uart_src",
-			.parent_names = gcc_pxo_pll8,
+			.parent_data = gcc_pxo_pll8,
 			.num_parents = 2,
 			.ops = &clk_rcg_ops,
 			.flags = CLK_SET_PARENT_GATE,
@@ -633,8 +655,8 @@ static struct clk_branch gsbi7_uart_clk = {
 		.enable_mask = BIT(9),
 		.hw.init = &(struct clk_init_data){
 			.name = "gsbi7_uart_clk",
-			.parent_names = (const char *[]){
-				"gsbi7_uart_src",
+			.parent_data = &(const struct clk_parent_data){
+				.hw = &gsbi7_uart_src.clkr.hw,
 			},
 			.num_parents = 1,
 			.ops = &clk_branch_ops,
@@ -681,7 +703,7 @@ static struct clk_rcg gsbi1_qup_src = {
 		.enable_mask = BIT(11),
 		.hw.init = &(struct clk_init_data){
 			.name = "gsbi1_qup_src",
-			.parent_names = gcc_pxo_pll8,
+			.parent_data = gcc_pxo_pll8,
 			.num_parents = 2,
 			.ops = &clk_rcg_ops,
 			.flags = CLK_SET_PARENT_GATE,
@@ -697,7 +719,9 @@ static struct clk_branch gsbi1_qup_clk = {
 		.enable_mask = BIT(9),
 		.hw.init = &(struct clk_init_data){
 			.name = "gsbi1_qup_clk",
-			.parent_names = (const char *[]){ "gsbi1_qup_src" },
+			.parent_data = &(const struct clk_parent_data){
+				.hw = &gsbi1_qup_src.clkr.hw,
+			},
 			.num_parents = 1,
 			.ops = &clk_branch_ops,
 			.flags = CLK_SET_RATE_PARENT,
@@ -730,7 +754,7 @@ static struct clk_rcg gsbi2_qup_src = {
 		.enable_mask = BIT(11),
 		.hw.init = &(struct clk_init_data){
 			.name = "gsbi2_qup_src",
-			.parent_names = gcc_pxo_pll8,
+			.parent_data = gcc_pxo_pll8,
 			.num_parents = 2,
 			.ops = &clk_rcg_ops,
 			.flags = CLK_SET_PARENT_GATE,
@@ -746,7 +770,9 @@ static struct clk_branch gsbi2_qup_clk = {
 		.enable_mask = BIT(9),
 		.hw.init = &(struct clk_init_data){
 			.name = "gsbi2_qup_clk",
-			.parent_names = (const char *[]){ "gsbi2_qup_src" },
+			.parent_data = &(const struct clk_parent_data){
+				.hw = &gsbi2_qup_src.clkr.hw,
+			},
 			.num_parents = 1,
 			.ops = &clk_branch_ops,
 			.flags = CLK_SET_RATE_PARENT,
@@ -779,7 +805,7 @@ static struct clk_rcg gsbi4_qup_src = {
 		.enable_mask = BIT(11),
 		.hw.init = &(struct clk_init_data){
 			.name = "gsbi4_qup_src",
-			.parent_names = gcc_pxo_pll8,
+			.parent_data = gcc_pxo_pll8,
 			.num_parents = 2,
 			.ops = &clk_rcg_ops,
 			.flags = CLK_SET_PARENT_GATE,
@@ -795,7 +821,9 @@ static struct clk_branch gsbi4_qup_clk = {
 		.enable_mask = BIT(9),
 		.hw.init = &(struct clk_init_data){
 			.name = "gsbi4_qup_clk",
-			.parent_names = (const char *[]){ "gsbi4_qup_src" },
+			.parent_data = &(const struct clk_parent_data){
+				.hw = &gsbi4_qup_src.clkr.hw,
+			},
 			.num_parents = 1,
 			.ops = &clk_branch_ops,
 			.flags = CLK_SET_RATE_PARENT,
@@ -828,7 +856,7 @@ static struct clk_rcg gsbi5_qup_src = {
 		.enable_mask = BIT(11),
 		.hw.init = &(struct clk_init_data){
 			.name = "gsbi5_qup_src",
-			.parent_names = gcc_pxo_pll8,
+			.parent_data = gcc_pxo_pll8,
 			.num_parents = 2,
 			.ops = &clk_rcg_ops,
 			.flags = CLK_SET_PARENT_GATE,
@@ -844,7 +872,9 @@ static struct clk_branch gsbi5_qup_clk = {
 		.enable_mask = BIT(9),
 		.hw.init = &(struct clk_init_data){
 			.name = "gsbi5_qup_clk",
-			.parent_names = (const char *[]){ "gsbi5_qup_src" },
+			.parent_data = &(const struct clk_parent_data){
+				.hw = &gsbi5_qup_src.clkr.hw,
+			},
 			.num_parents = 1,
 			.ops = &clk_branch_ops,
 			.flags = CLK_SET_RATE_PARENT,
@@ -877,7 +907,7 @@ static struct clk_rcg gsbi6_qup_src = {
 		.enable_mask = BIT(11),
 		.hw.init = &(struct clk_init_data){
 			.name = "gsbi6_qup_src",
-			.parent_names = gcc_pxo_pll8,
+			.parent_data = gcc_pxo_pll8,
 			.num_parents = 2,
 			.ops = &clk_rcg_ops,
 			.flags = CLK_SET_PARENT_GATE,
@@ -893,7 +923,9 @@ static struct clk_branch gsbi6_qup_clk = {
 		.enable_mask = BIT(9),
 		.hw.init = &(struct clk_init_data){
 			.name = "gsbi6_qup_clk",
-			.parent_names = (const char *[]){ "gsbi6_qup_src" },
+			.parent_data = &(const struct clk_parent_data){
+				.hw = &gsbi6_qup_src.clkr.hw,
+			},
 			.num_parents = 1,
 			.ops = &clk_branch_ops,
 			.flags = CLK_SET_RATE_PARENT,
@@ -926,7 +958,7 @@ static struct clk_rcg gsbi7_qup_src = {
 		.enable_mask = BIT(11),
 		.hw.init = &(struct clk_init_data){
 			.name = "gsbi7_qup_src",
-			.parent_names = gcc_pxo_pll8,
+			.parent_data = gcc_pxo_pll8,
 			.num_parents = 2,
 			.ops = &clk_rcg_ops,
 			.flags = CLK_SET_PARENT_GATE,
@@ -942,7 +974,9 @@ static struct clk_branch gsbi7_qup_clk = {
 		.enable_mask = BIT(9),
 		.hw.init = &(struct clk_init_data){
 			.name = "gsbi7_qup_clk",
-			.parent_names = (const char *[]){ "gsbi7_qup_src" },
+			.parent_data = &(const struct clk_parent_data){
+				.hw = &gsbi7_qup_src.clkr.hw,
+			},
 			.num_parents = 1,
 			.ops = &clk_branch_ops,
 			.flags = CLK_SET_RATE_PARENT,
@@ -1076,7 +1110,7 @@ static struct clk_rcg gp0_src = {
 		.enable_mask = BIT(11),
 		.hw.init = &(struct clk_init_data){
 			.name = "gp0_src",
-			.parent_names = gcc_pxo_pll8_cxo,
+			.parent_data = gcc_pxo_pll8_cxo,
 			.num_parents = 3,
 			.ops = &clk_rcg_ops,
 			.flags = CLK_SET_PARENT_GATE,
@@ -1092,7 +1126,9 @@ static struct clk_branch gp0_clk = {
 		.enable_mask = BIT(9),
 		.hw.init = &(struct clk_init_data){
 			.name = "gp0_clk",
-			.parent_names = (const char *[]){ "gp0_src" },
+			.parent_data = &(const struct clk_parent_data){
+				.hw = &gp0_src.clkr.hw,
+			},
 			.num_parents = 1,
 			.ops = &clk_branch_ops,
 			.flags = CLK_SET_RATE_PARENT,
@@ -1125,7 +1161,7 @@ static struct clk_rcg gp1_src = {
 		.enable_mask = BIT(11),
 		.hw.init = &(struct clk_init_data){
 			.name = "gp1_src",
-			.parent_names = gcc_pxo_pll8_cxo,
+			.parent_data = gcc_pxo_pll8_cxo,
 			.num_parents = 3,
 			.ops = &clk_rcg_ops,
 			.flags = CLK_SET_RATE_GATE,
@@ -1141,7 +1177,9 @@ static struct clk_branch gp1_clk = {
 		.enable_mask = BIT(9),
 		.hw.init = &(struct clk_init_data){
 			.name = "gp1_clk",
-			.parent_names = (const char *[]){ "gp1_src" },
+			.parent_data = &(const struct clk_parent_data){
+				.hw = &gp1_src.clkr.hw,
+			},
 			.num_parents = 1,
 			.ops = &clk_branch_ops,
 			.flags = CLK_SET_RATE_PARENT,
@@ -1174,7 +1212,7 @@ static struct clk_rcg gp2_src = {
 		.enable_mask = BIT(11),
 		.hw.init = &(struct clk_init_data){
 			.name = "gp2_src",
-			.parent_names = gcc_pxo_pll8_cxo,
+			.parent_data = gcc_pxo_pll8_cxo,
 			.num_parents = 3,
 			.ops = &clk_rcg_ops,
 			.flags = CLK_SET_RATE_GATE,
@@ -1190,7 +1228,9 @@ static struct clk_branch gp2_clk = {
 		.enable_mask = BIT(9),
 		.hw.init = &(struct clk_init_data){
 			.name = "gp2_clk",
-			.parent_names = (const char *[]){ "gp2_src" },
+			.parent_data = &(const struct clk_parent_data){
+				.hw = &gp2_src.clkr.hw,
+			},
 			.num_parents = 1,
 			.ops = &clk_branch_ops,
 			.flags = CLK_SET_RATE_PARENT,
@@ -1228,7 +1268,7 @@ static struct clk_rcg prng_src = {
 		.enable_mask = BIT(11),
 		.hw.init = &(struct clk_init_data){
 			.name = "prng_src",
-			.parent_names = gcc_pxo_pll8,
+			.parent_data = gcc_pxo_pll8,
 			.num_parents = 2,
 			.ops = &clk_rcg_ops,
 		},
@@ -1244,7 +1284,9 @@ static struct clk_branch prng_clk = {
 		.enable_mask = BIT(10),
 		.hw.init = &(struct clk_init_data){
 			.name = "prng_clk",
-			.parent_names = (const char *[]){ "prng_src" },
+			.parent_data = &(const struct clk_parent_data){
+				.hw = &prng_src.clkr.hw,
+			},
 			.num_parents = 1,
 			.ops = &clk_branch_ops,
 		},
@@ -1290,7 +1332,7 @@ static struct clk_rcg sdc1_src = {
 		.enable_mask = BIT(11),
 		.hw.init = &(struct clk_init_data){
 			.name = "sdc1_src",
-			.parent_names = gcc_pxo_pll8,
+			.parent_data = gcc_pxo_pll8,
 			.num_parents = 2,
 			.ops = &clk_rcg_ops,
 		},
@@ -1305,7 +1347,9 @@ static struct clk_branch sdc1_clk = {
 		.enable_mask = BIT(9),
 		.hw.init = &(struct clk_init_data){
 			.name = "sdc1_clk",
-			.parent_names = (const char *[]){ "sdc1_src" },
+			.parent_data = &(const struct clk_parent_data){
+				.hw = &sdc1_src.clkr.hw,
+			},
 			.num_parents = 1,
 			.ops = &clk_branch_ops,
 			.flags = CLK_SET_RATE_PARENT,
@@ -1338,7 +1382,7 @@ static struct clk_rcg sdc3_src = {
 		.enable_mask = BIT(11),
 		.hw.init = &(struct clk_init_data){
 			.name = "sdc3_src",
-			.parent_names = gcc_pxo_pll8,
+			.parent_data = gcc_pxo_pll8,
 			.num_parents = 2,
 			.ops = &clk_rcg_ops,
 		},
@@ -1353,7 +1397,9 @@ static struct clk_branch sdc3_clk = {
 		.enable_mask = BIT(9),
 		.hw.init = &(struct clk_init_data){
 			.name = "sdc3_clk",
-			.parent_names = (const char *[]){ "sdc3_src" },
+			.parent_data = &(const struct clk_parent_data){
+				.hw = &sdc3_src.clkr.hw,
+			},
 			.num_parents = 1,
 			.ops = &clk_branch_ops,
 			.flags = CLK_SET_RATE_PARENT,
@@ -1421,7 +1467,7 @@ static struct clk_rcg tsif_ref_src = {
 		.enable_mask = BIT(11),
 		.hw.init = &(struct clk_init_data){
 			.name = "tsif_ref_src",
-			.parent_names = gcc_pxo_pll8,
+			.parent_data = gcc_pxo_pll8,
 			.num_parents = 2,
 			.ops = &clk_rcg_ops,
 		},
@@ -1436,7 +1482,9 @@ static struct clk_branch tsif_ref_clk = {
 		.enable_mask = BIT(9),
 		.hw.init = &(struct clk_init_data){
 			.name = "tsif_ref_clk",
-			.parent_names = (const char *[]){ "tsif_ref_src" },
+			.parent_data = &(const struct clk_parent_data){
+				.hw = &tsif_ref_src.clkr.hw,
+			},
 			.num_parents = 1,
 			.ops = &clk_branch_ops,
 			.flags = CLK_SET_RATE_PARENT,
@@ -1583,7 +1631,7 @@ static struct clk_rcg pcie_ref_src = {
 		.enable_mask = BIT(11),
 		.hw.init = &(struct clk_init_data){
 			.name = "pcie_ref_src",
-			.parent_names = gcc_pxo_pll3,
+			.parent_data = gcc_pxo_pll3,
 			.num_parents = 2,
 			.ops = &clk_rcg_ops,
 			.flags = CLK_SET_RATE_GATE,
@@ -1599,7 +1647,9 @@ static struct clk_branch pcie_ref_src_clk = {
 		.enable_mask = BIT(9),
 		.hw.init = &(struct clk_init_data){
 			.name = "pcie_ref_src_clk",
-			.parent_names = (const char *[]){ "pcie_ref_src" },
+			.parent_data = &(const struct clk_parent_data){
+				.hw = &pcie_ref_src.clkr.hw,
+			},
 			.num_parents = 1,
 			.ops = &clk_branch_ops,
 			.flags = CLK_SET_RATE_PARENT,
@@ -1675,7 +1725,7 @@ static struct clk_rcg pcie1_ref_src = {
 		.enable_mask = BIT(11),
 		.hw.init = &(struct clk_init_data){
 			.name = "pcie1_ref_src",
-			.parent_names = gcc_pxo_pll3,
+			.parent_data = gcc_pxo_pll3,
 			.num_parents = 2,
 			.ops = &clk_rcg_ops,
 			.flags = CLK_SET_RATE_GATE,
@@ -1691,7 +1741,9 @@ static struct clk_branch pcie1_ref_src_clk = {
 		.enable_mask = BIT(9),
 		.hw.init = &(struct clk_init_data){
 			.name = "pcie1_ref_src_clk",
-			.parent_names = (const char *[]){ "pcie1_ref_src" },
+			.parent_data = &(const struct clk_parent_data){
+				.hw = &pcie1_ref_src.clkr.hw,
+			},
 			.num_parents = 1,
 			.ops = &clk_branch_ops,
 			.flags = CLK_SET_RATE_PARENT,
@@ -1767,7 +1819,7 @@ static struct clk_rcg pcie2_ref_src = {
 		.enable_mask = BIT(11),
 		.hw.init = &(struct clk_init_data){
 			.name = "pcie2_ref_src",
-			.parent_names = gcc_pxo_pll3,
+			.parent_data = gcc_pxo_pll3,
 			.num_parents = 2,
 			.ops = &clk_rcg_ops,
 			.flags = CLK_SET_RATE_GATE,
@@ -1783,7 +1835,9 @@ static struct clk_branch pcie2_ref_src_clk = {
 		.enable_mask = BIT(9),
 		.hw.init = &(struct clk_init_data){
 			.name = "pcie2_ref_src_clk",
-			.parent_names = (const char *[]){ "pcie2_ref_src" },
+			.parent_data = &(const struct clk_parent_data){
+				.hw = &pcie2_ref_src.clkr.hw,
+			},
 			.num_parents = 1,
 			.ops = &clk_branch_ops,
 			.flags = CLK_SET_RATE_PARENT,
@@ -1864,7 +1918,7 @@ static struct clk_rcg sata_ref_src = {
 		.enable_mask = BIT(7),
 		.hw.init = &(struct clk_init_data){
 			.name = "sata_ref_src",
-			.parent_names = gcc_pxo_pll3,
+			.parent_data = gcc_pxo_pll3,
 			.num_parents = 2,
 			.ops = &clk_rcg_ops,
 			.flags = CLK_SET_RATE_GATE,
@@ -1880,7 +1934,9 @@ static struct clk_branch sata_rxoob_clk = {
 		.enable_mask = BIT(4),
 		.hw.init = &(struct clk_init_data){
 			.name = "sata_rxoob_clk",
-			.parent_names = (const char *[]){ "sata_ref_src" },
+			.parent_data = &(const struct clk_parent_data){
+				.hw = &sata_ref_src.clkr.hw,
+			},
 			.num_parents = 1,
 			.ops = &clk_branch_ops,
 			.flags = CLK_SET_RATE_PARENT,
@@ -1896,7 +1952,9 @@ static struct clk_branch sata_pmalive_clk = {
 		.enable_mask = BIT(4),
 		.hw.init = &(struct clk_init_data){
 			.name = "sata_pmalive_clk",
-			.parent_names = (const char *[]){ "sata_ref_src" },
+			.parent_data = &(const struct clk_parent_data){
+				.hw = &sata_ref_src.clkr.hw,
+			},
 			.num_parents = 1,
 			.ops = &clk_branch_ops,
 			.flags = CLK_SET_RATE_PARENT,
@@ -1912,7 +1970,9 @@ static struct clk_branch sata_phy_ref_clk = {
 		.enable_mask = BIT(4),
 		.hw.init = &(struct clk_init_data){
 			.name = "sata_phy_ref_clk",
-			.parent_names = (const char *[]){ "pxo" },
+			.parent_data = &(const struct clk_parent_data){
+				.fw_name = "pxo",
+			},
 			.num_parents = 1,
 			.ops = &clk_branch_ops,
 		},
@@ -2001,7 +2061,7 @@ static struct clk_rcg usb30_master_clk_src = {
 		.enable_mask = BIT(11),
 		.hw.init = &(struct clk_init_data){
 			.name = "usb30_master_ref_src",
-			.parent_names = gcc_pxo_pll8_pll0,
+			.parent_data = gcc_pxo_pll8_pll0,
 			.num_parents = 3,
 			.ops = &clk_rcg_ops,
 			.flags = CLK_SET_RATE_GATE,
@@ -2017,7 +2077,9 @@ static struct clk_branch usb30_0_branch_clk = {
 		.enable_mask = BIT(4),
 		.hw.init = &(struct clk_init_data){
 			.name = "usb30_0_branch_clk",
-			.parent_names = (const char *[]){ "usb30_master_ref_src", },
+			.parent_data = &(const struct clk_parent_data){
+				.hw = &usb30_master_clk_src.clkr.hw,
+			},
 			.num_parents = 1,
 			.ops = &clk_branch_ops,
 			.flags = CLK_SET_RATE_PARENT,
@@ -2033,7 +2095,9 @@ static struct clk_branch usb30_1_branch_clk = {
 		.enable_mask = BIT(4),
 		.hw.init = &(struct clk_init_data){
 			.name = "usb30_1_branch_clk",
-			.parent_names = (const char *[]){ "usb30_master_ref_src", },
+			.parent_data = &(const struct clk_parent_data){
+				.hw = &usb30_master_clk_src.clkr.hw,
+			},
 			.num_parents = 1,
 			.ops = &clk_branch_ops,
 			.flags = CLK_SET_RATE_PARENT,
@@ -2071,7 +2135,7 @@ static struct clk_rcg usb30_utmi_clk = {
 		.enable_mask = BIT(11),
 		.hw.init = &(struct clk_init_data){
 			.name = "usb30_utmi_clk",
-			.parent_names = gcc_pxo_pll8_pll0,
+			.parent_data = gcc_pxo_pll8_pll0,
 			.num_parents = 3,
 			.ops = &clk_rcg_ops,
 			.flags = CLK_SET_RATE_GATE,
@@ -2087,7 +2151,9 @@ static struct clk_branch usb30_0_utmi_clk_ctl = {
 		.enable_mask = BIT(4),
 		.hw.init = &(struct clk_init_data){
 			.name = "usb30_0_utmi_clk_ctl",
-			.parent_names = (const char *[]){ "usb30_utmi_clk", },
+			.parent_data = &(const struct clk_parent_data){
+				.hw = &usb30_utmi_clk.clkr.hw,
+			},
 			.num_parents = 1,
 			.ops = &clk_branch_ops,
 			.flags = CLK_SET_RATE_PARENT,
@@ -2103,7 +2169,9 @@ static struct clk_branch usb30_1_utmi_clk_ctl = {
 		.enable_mask = BIT(4),
 		.hw.init = &(struct clk_init_data){
 			.name = "usb30_1_utmi_clk_ctl",
-			.parent_names = (const char *[]){ "usb30_utmi_clk", },
+			.parent_data = &(const struct clk_parent_data){
+				.hw = &usb30_utmi_clk.clkr.hw,
+			},
 			.num_parents = 1,
 			.ops = &clk_branch_ops,
 			.flags = CLK_SET_RATE_PARENT,
@@ -2141,7 +2209,7 @@ static struct clk_rcg usb_hs1_xcvr_clk_src = {
 		.enable_mask = BIT(11),
 		.hw.init = &(struct clk_init_data){
 			.name = "usb_hs1_xcvr_src",
-			.parent_names = gcc_pxo_pll8_pll0,
+			.parent_data = gcc_pxo_pll8_pll0,
 			.num_parents = 3,
 			.ops = &clk_rcg_ops,
 			.flags = CLK_SET_RATE_GATE,
@@ -2157,7 +2225,9 @@ static struct clk_branch usb_hs1_xcvr_clk = {
 		.enable_mask = BIT(9),
 		.hw.init = &(struct clk_init_data){
 			.name = "usb_hs1_xcvr_clk",
-			.parent_names = (const char *[]){ "usb_hs1_xcvr_src" },
+			.parent_data = &(const struct clk_parent_data){
+				.hw = &usb_hs1_xcvr_clk_src.clkr.hw,
+			},
 			.num_parents = 1,
 			.ops = &clk_branch_ops,
 			.flags = CLK_SET_RATE_PARENT,
@@ -2205,7 +2275,7 @@ static struct clk_rcg usb_fs1_xcvr_clk_src = {
 		.enable_mask = BIT(11),
 		.hw.init = &(struct clk_init_data){
 			.name = "usb_fs1_xcvr_src",
-			.parent_names = gcc_pxo_pll8_pll0,
+			.parent_data = gcc_pxo_pll8_pll0,
 			.num_parents = 3,
 			.ops = &clk_rcg_ops,
 			.flags = CLK_SET_RATE_GATE,
@@ -2221,7 +2291,9 @@ static struct clk_branch usb_fs1_xcvr_clk = {
 		.enable_mask = BIT(9),
 		.hw.init = &(struct clk_init_data){
 			.name = "usb_fs1_xcvr_clk",
-			.parent_names = (const char *[]){ "usb_fs1_xcvr_src", },
+			.parent_data = &(const struct clk_parent_data){
+				.hw = &usb_fs1_xcvr_clk_src.clkr.hw,
+			},
 			.num_parents = 1,
 			.ops = &clk_branch_ops,
 			.flags = CLK_SET_RATE_PARENT,
@@ -2237,7 +2309,9 @@ static struct clk_branch usb_fs1_sys_clk = {
 		.enable_mask = BIT(4),
 		.hw.init = &(struct clk_init_data){
 			.name = "usb_fs1_sys_clk",
-			.parent_names = (const char *[]){ "usb_fs1_xcvr_src", },
+			.parent_data = &(const struct clk_parent_data){
+				.hw = &usb_fs1_xcvr_clk_src.clkr.hw,
+			},
 			.num_parents = 1,
 			.ops = &clk_branch_ops,
 			.flags = CLK_SET_RATE_PARENT,
@@ -2337,7 +2411,7 @@ static struct clk_dyn_rcg gmac_core1_src = {
 		.enable_mask = BIT(1),
 		.hw.init = &(struct clk_init_data){
 			.name = "gmac_core1_src",
-			.parent_names = gcc_pxo_pll8_pll14_pll18_pll0,
+			.parent_data = gcc_pxo_pll8_pll14_pll18_pll0,
 			.num_parents = 5,
 			.ops = &clk_dyn_rcg_ops,
 		},
@@ -2354,8 +2428,8 @@ static struct clk_branch gmac_core1_clk = {
 		.enable_mask = BIT(4),
 		.hw.init = &(struct clk_init_data){
 			.name = "gmac_core1_clk",
-			.parent_names = (const char *[]){
-				"gmac_core1_src",
+			.parent_data = &(const struct clk_parent_data){
+				.hw = &gmac_core1_src.clkr.hw,
 			},
 			.num_parents = 1,
 			.ops = &clk_branch_ops,
@@ -2409,7 +2483,7 @@ static struct clk_dyn_rcg gmac_core2_src = {
 		.enable_mask = BIT(1),
 		.hw.init = &(struct clk_init_data){
 			.name = "gmac_core2_src",
-			.parent_names = gcc_pxo_pll8_pll14_pll18_pll0,
+			.parent_data = gcc_pxo_pll8_pll14_pll18_pll0,
 			.num_parents = 5,
 			.ops = &clk_dyn_rcg_ops,
 		},
@@ -2426,8 +2500,8 @@ static struct clk_branch gmac_core2_clk = {
 		.enable_mask = BIT(4),
 		.hw.init = &(struct clk_init_data){
 			.name = "gmac_core2_clk",
-			.parent_names = (const char *[]){
-				"gmac_core2_src",
+			.parent_data = &(const struct clk_parent_data){
+				.hw = &gmac_core2_src.clkr.hw,
 			},
 			.num_parents = 1,
 			.ops = &clk_branch_ops,
@@ -2481,7 +2555,7 @@ static struct clk_dyn_rcg gmac_core3_src = {
 		.enable_mask = BIT(1),
 		.hw.init = &(struct clk_init_data){
 			.name = "gmac_core3_src",
-			.parent_names = gcc_pxo_pll8_pll14_pll18_pll0,
+			.parent_data = gcc_pxo_pll8_pll14_pll18_pll0,
 			.num_parents = 5,
 			.ops = &clk_dyn_rcg_ops,
 		},
@@ -2498,8 +2572,8 @@ static struct clk_branch gmac_core3_clk = {
 		.enable_mask = BIT(4),
 		.hw.init = &(struct clk_init_data){
 			.name = "gmac_core3_clk",
-			.parent_names = (const char *[]){
-				"gmac_core3_src",
+			.parent_data = &(const struct clk_parent_data){
+				.hw = &gmac_core3_src.clkr.hw,
 			},
 			.num_parents = 1,
 			.ops = &clk_branch_ops,
@@ -2553,7 +2627,7 @@ static struct clk_dyn_rcg gmac_core4_src = {
 		.enable_mask = BIT(1),
 		.hw.init = &(struct clk_init_data){
 			.name = "gmac_core4_src",
-			.parent_names = gcc_pxo_pll8_pll14_pll18_pll0,
+			.parent_data = gcc_pxo_pll8_pll14_pll18_pll0,
 			.num_parents = 5,
 			.ops = &clk_dyn_rcg_ops,
 		},
@@ -2570,8 +2644,8 @@ static struct clk_branch gmac_core4_clk = {
 		.enable_mask = BIT(4),
 		.hw.init = &(struct clk_init_data){
 			.name = "gmac_core4_clk",
-			.parent_names = (const char *[]){
-				"gmac_core4_src",
+			.parent_data = &(const struct clk_parent_data){
+				.hw = &gmac_core4_src.clkr.hw,
 			},
 			.num_parents = 1,
 			.ops = &clk_branch_ops,
@@ -2613,7 +2687,7 @@ static struct clk_dyn_rcg nss_tcm_src = {
 		.enable_mask = BIT(1),
 		.hw.init = &(struct clk_init_data){
 			.name = "nss_tcm_src",
-			.parent_names = gcc_pxo_pll8_pll14_pll18_pll0,
+			.parent_data = gcc_pxo_pll8_pll14_pll18_pll0,
 			.num_parents = 5,
 			.ops = &clk_dyn_rcg_ops,
 		},
@@ -2628,8 +2702,8 @@ static struct clk_branch nss_tcm_clk = {
 		.enable_mask = BIT(6) | BIT(4),
 		.hw.init = &(struct clk_init_data){
 			.name = "nss_tcm_clk",
-			.parent_names = (const char *[]){
-				"nss_tcm_src",
+			.parent_data = &(const struct clk_parent_data){
+				.hw = &nss_tcm_src.clkr.hw,
 			},
 			.num_parents = 1,
 			.ops = &clk_branch_ops,
@@ -2691,7 +2765,7 @@ static struct clk_dyn_rcg ubi32_core1_src_clk = {
 		.enable_mask = BIT(1),
 		.hw.init = &(struct clk_init_data){
 			.name = "ubi32_core1_src_clk",
-			.parent_names = gcc_pxo_pll8_pll14_pll18_pll0,
+			.parent_data = gcc_pxo_pll8_pll14_pll18_pll0,
 			.num_parents = 5,
 			.ops = &clk_dyn_rcg_ops,
 			.flags = CLK_SET_RATE_PARENT | CLK_GET_RATE_NOCACHE,
@@ -2744,7 +2818,7 @@ static struct clk_dyn_rcg ubi32_core2_src_clk = {
 		.enable_mask = BIT(1),
 		.hw.init = &(struct clk_init_data){
 			.name = "ubi32_core2_src_clk",
-			.parent_names = gcc_pxo_pll8_pll14_pll18_pll0,
+			.parent_data = gcc_pxo_pll8_pll14_pll18_pll0,
 			.num_parents = 5,
 			.ops = &clk_dyn_rcg_ops,
 			.flags = CLK_SET_RATE_PARENT | CLK_GET_RATE_NOCACHE,
-- 
2.33.1

[PATCH 04/14] drivers: clk: qcom: gcc-ipq806x: use ARRAY_SIZE for num_parents

[Ansuel Smith]

Use ARRAY_SIZE for num_parents instead of hardcoding the value.

Signed-off-by: Ansuel Smith <ansuelsmth@gmail.com>
---
 drivers/clk/qcom/gcc-ipq806x.c | 68 +++++++++++++++++-----------------
 1 file changed, 34 insertions(+), 34 deletions(-)

diff --git a/drivers/clk/qcom/gcc-ipq806x.c b/drivers/clk/qcom/gcc-ipq806x.c
index cbacd56f52d4..17ce61f36b08 100644
--- a/drivers/clk/qcom/gcc-ipq806x.c
+++ b/drivers/clk/qcom/gcc-ipq806x.c
@@ -385,7 +385,7 @@ static struct clk_rcg gsbi1_uart_src = {
 		.hw.init = &(struct clk_init_data){
 			.name = "gsbi1_uart_src",
 			.parent_data = gcc_pxo_pll8,
-			.num_parents = 2,
+			.num_parents = ARRAY_SIZE(gcc_pxo_pll8),
 			.ops = &clk_rcg_ops,
 			.flags = CLK_SET_PARENT_GATE,
 		},
@@ -436,7 +436,7 @@ static struct clk_rcg gsbi2_uart_src = {
 		.hw.init = &(struct clk_init_data){
 			.name = "gsbi2_uart_src",
 			.parent_data = gcc_pxo_pll8,
-			.num_parents = 2,
+			.num_parents = ARRAY_SIZE(gcc_pxo_pll8),
 			.ops = &clk_rcg_ops,
 			.flags = CLK_SET_PARENT_GATE,
 		},
@@ -487,7 +487,7 @@ static struct clk_rcg gsbi4_uart_src = {
 		.hw.init = &(struct clk_init_data){
 			.name = "gsbi4_uart_src",
 			.parent_data = gcc_pxo_pll8,
-			.num_parents = 2,
+			.num_parents = ARRAY_SIZE(gcc_pxo_pll8),
 			.ops = &clk_rcg_ops,
 			.flags = CLK_SET_PARENT_GATE,
 		},
@@ -538,7 +538,7 @@ static struct clk_rcg gsbi5_uart_src = {
 		.hw.init = &(struct clk_init_data){
 			.name = "gsbi5_uart_src",
 			.parent_data = gcc_pxo_pll8,
-			.num_parents = 2,
+			.num_parents = ARRAY_SIZE(gcc_pxo_pll8),
 			.ops = &clk_rcg_ops,
 			.flags = CLK_SET_PARENT_GATE,
 		},
@@ -589,7 +589,7 @@ static struct clk_rcg gsbi6_uart_src = {
 		.hw.init = &(struct clk_init_data){
 			.name = "gsbi6_uart_src",
 			.parent_data = gcc_pxo_pll8,
-			.num_parents = 2,
+			.num_parents = ARRAY_SIZE(gcc_pxo_pll8),
 			.ops = &clk_rcg_ops,
 			.flags = CLK_SET_PARENT_GATE,
 		},
@@ -640,7 +640,7 @@ static struct clk_rcg gsbi7_uart_src = {
 		.hw.init = &(struct clk_init_data){
 			.name = "gsbi7_uart_src",
 			.parent_data = gcc_pxo_pll8,
-			.num_parents = 2,
+			.num_parents = ARRAY_SIZE(gcc_pxo_pll8),
 			.ops = &clk_rcg_ops,
 			.flags = CLK_SET_PARENT_GATE,
 		},
@@ -704,7 +704,7 @@ static struct clk_rcg gsbi1_qup_src = {
 		.hw.init = &(struct clk_init_data){
 			.name = "gsbi1_qup_src",
 			.parent_data = gcc_pxo_pll8,
-			.num_parents = 2,
+			.num_parents = ARRAY_SIZE(gcc_pxo_pll8),
 			.ops = &clk_rcg_ops,
 			.flags = CLK_SET_PARENT_GATE,
 		},
@@ -755,7 +755,7 @@ static struct clk_rcg gsbi2_qup_src = {
 		.hw.init = &(struct clk_init_data){
 			.name = "gsbi2_qup_src",
 			.parent_data = gcc_pxo_pll8,
-			.num_parents = 2,
+			.num_parents = ARRAY_SIZE(gcc_pxo_pll8),
 			.ops = &clk_rcg_ops,
 			.flags = CLK_SET_PARENT_GATE,
 		},
@@ -806,7 +806,7 @@ static struct clk_rcg gsbi4_qup_src = {
 		.hw.init = &(struct clk_init_data){
 			.name = "gsbi4_qup_src",
 			.parent_data = gcc_pxo_pll8,
-			.num_parents = 2,
+			.num_parents = ARRAY_SIZE(gcc_pxo_pll8),
 			.ops = &clk_rcg_ops,
 			.flags = CLK_SET_PARENT_GATE,
 		},
@@ -857,7 +857,7 @@ static struct clk_rcg gsbi5_qup_src = {
 		.hw.init = &(struct clk_init_data){
 			.name = "gsbi5_qup_src",
 			.parent_data = gcc_pxo_pll8,
-			.num_parents = 2,
+			.num_parents = ARRAY_SIZE(gcc_pxo_pll8),
 			.ops = &clk_rcg_ops,
 			.flags = CLK_SET_PARENT_GATE,
 		},
@@ -908,7 +908,7 @@ static struct clk_rcg gsbi6_qup_src = {
 		.hw.init = &(struct clk_init_data){
 			.name = "gsbi6_qup_src",
 			.parent_data = gcc_pxo_pll8,
-			.num_parents = 2,
+			.num_parents = ARRAY_SIZE(gcc_pxo_pll8),
 			.ops = &clk_rcg_ops,
 			.flags = CLK_SET_PARENT_GATE,
 		},
@@ -959,7 +959,7 @@ static struct clk_rcg gsbi7_qup_src = {
 		.hw.init = &(struct clk_init_data){
 			.name = "gsbi7_qup_src",
 			.parent_data = gcc_pxo_pll8,
-			.num_parents = 2,
+			.num_parents = ARRAY_SIZE(gcc_pxo_pll8),
 			.ops = &clk_rcg_ops,
 			.flags = CLK_SET_PARENT_GATE,
 		},
@@ -1111,7 +1111,7 @@ static struct clk_rcg gp0_src = {
 		.hw.init = &(struct clk_init_data){
 			.name = "gp0_src",
 			.parent_data = gcc_pxo_pll8_cxo,
-			.num_parents = 3,
+			.num_parents = ARRAY_SIZE(gcc_pxo_pll8_cxo),
 			.ops = &clk_rcg_ops,
 			.flags = CLK_SET_PARENT_GATE,
 		},
@@ -1162,7 +1162,7 @@ static struct clk_rcg gp1_src = {
 		.hw.init = &(struct clk_init_data){
 			.name = "gp1_src",
 			.parent_data = gcc_pxo_pll8_cxo,
-			.num_parents = 3,
+			.num_parents = ARRAY_SIZE(gcc_pxo_pll8_cxo),
 			.ops = &clk_rcg_ops,
 			.flags = CLK_SET_RATE_GATE,
 		},
@@ -1213,7 +1213,7 @@ static struct clk_rcg gp2_src = {
 		.hw.init = &(struct clk_init_data){
 			.name = "gp2_src",
 			.parent_data = gcc_pxo_pll8_cxo,
-			.num_parents = 3,
+			.num_parents = ARRAY_SIZE(gcc_pxo_pll8_cxo),
 			.ops = &clk_rcg_ops,
 			.flags = CLK_SET_RATE_GATE,
 		},
@@ -1269,7 +1269,7 @@ static struct clk_rcg prng_src = {
 		.hw.init = &(struct clk_init_data){
 			.name = "prng_src",
 			.parent_data = gcc_pxo_pll8,
-			.num_parents = 2,
+			.num_parents = ARRAY_SIZE(gcc_pxo_pll8),
 			.ops = &clk_rcg_ops,
 		},
 	},
@@ -1333,7 +1333,7 @@ static struct clk_rcg sdc1_src = {
 		.hw.init = &(struct clk_init_data){
 			.name = "sdc1_src",
 			.parent_data = gcc_pxo_pll8,
-			.num_parents = 2,
+			.num_parents = ARRAY_SIZE(gcc_pxo_pll8),
 			.ops = &clk_rcg_ops,
 		},
 	}
@@ -1383,7 +1383,7 @@ static struct clk_rcg sdc3_src = {
 		.hw.init = &(struct clk_init_data){
 			.name = "sdc3_src",
 			.parent_data = gcc_pxo_pll8,
-			.num_parents = 2,
+			.num_parents = ARRAY_SIZE(gcc_pxo_pll8),
 			.ops = &clk_rcg_ops,
 		},
 	}
@@ -1468,7 +1468,7 @@ static struct clk_rcg tsif_ref_src = {
 		.hw.init = &(struct clk_init_data){
 			.name = "tsif_ref_src",
 			.parent_data = gcc_pxo_pll8,
-			.num_parents = 2,
+			.num_parents = ARRAY_SIZE(gcc_pxo_pll8),
 			.ops = &clk_rcg_ops,
 		},
 	}
@@ -1632,7 +1632,7 @@ static struct clk_rcg pcie_ref_src = {
 		.hw.init = &(struct clk_init_data){
 			.name = "pcie_ref_src",
 			.parent_data = gcc_pxo_pll3,
-			.num_parents = 2,
+			.num_parents = ARRAY_SIZE(gcc_pxo_pll3),
 			.ops = &clk_rcg_ops,
 			.flags = CLK_SET_RATE_GATE,
 		},
@@ -1726,7 +1726,7 @@ static struct clk_rcg pcie1_ref_src = {
 		.hw.init = &(struct clk_init_data){
 			.name = "pcie1_ref_src",
 			.parent_data = gcc_pxo_pll3,
-			.num_parents = 2,
+			.num_parents = ARRAY_SIZE(gcc_pxo_pll3),
 			.ops = &clk_rcg_ops,
 			.flags = CLK_SET_RATE_GATE,
 		},
@@ -1820,7 +1820,7 @@ static struct clk_rcg pcie2_ref_src = {
 		.hw.init = &(struct clk_init_data){
 			.name = "pcie2_ref_src",
 			.parent_data = gcc_pxo_pll3,
-			.num_parents = 2,
+			.num_parents = ARRAY_SIZE(gcc_pxo_pll3),
 			.ops = &clk_rcg_ops,
 			.flags = CLK_SET_RATE_GATE,
 		},
@@ -1919,7 +1919,7 @@ static struct clk_rcg sata_ref_src = {
 		.hw.init = &(struct clk_init_data){
 			.name = "sata_ref_src",
 			.parent_data = gcc_pxo_pll3,
-			.num_parents = 2,
+			.num_parents = ARRAY_SIZE(gcc_pxo_pll3),
 			.ops = &clk_rcg_ops,
 			.flags = CLK_SET_RATE_GATE,
 		},
@@ -2062,7 +2062,7 @@ static struct clk_rcg usb30_master_clk_src = {
 		.hw.init = &(struct clk_init_data){
 			.name = "usb30_master_ref_src",
 			.parent_data = gcc_pxo_pll8_pll0,
-			.num_parents = 3,
+			.num_parents = ARRAY_SIZE(gcc_pxo_pll8_pll0),
 			.ops = &clk_rcg_ops,
 			.flags = CLK_SET_RATE_GATE,
 		},
@@ -2136,7 +2136,7 @@ static struct clk_rcg usb30_utmi_clk = {
 		.hw.init = &(struct clk_init_data){
 			.name = "usb30_utmi_clk",
 			.parent_data = gcc_pxo_pll8_pll0,
-			.num_parents = 3,
+			.num_parents = ARRAY_SIZE(gcc_pxo_pll8_pll0),
 			.ops = &clk_rcg_ops,
 			.flags = CLK_SET_RATE_GATE,
 		},
@@ -2210,7 +2210,7 @@ static struct clk_rcg usb_hs1_xcvr_clk_src = {
 		.hw.init = &(struct clk_init_data){
 			.name = "usb_hs1_xcvr_src",
 			.parent_data = gcc_pxo_pll8_pll0,
-			.num_parents = 3,
+			.num_parents = ARRAY_SIZE(gcc_pxo_pll8_pll0),
 			.ops = &clk_rcg_ops,
 			.flags = CLK_SET_RATE_GATE,
 		},
@@ -2276,7 +2276,7 @@ static struct clk_rcg usb_fs1_xcvr_clk_src = {
 		.hw.init = &(struct clk_init_data){
 			.name = "usb_fs1_xcvr_src",
 			.parent_data = gcc_pxo_pll8_pll0,
-			.num_parents = 3,
+			.num_parents = ARRAY_SIZE(gcc_pxo_pll8_pll0),
 			.ops = &clk_rcg_ops,
 			.flags = CLK_SET_RATE_GATE,
 		},
@@ -2412,7 +2412,7 @@ static struct clk_dyn_rcg gmac_core1_src = {
 		.hw.init = &(struct clk_init_data){
 			.name = "gmac_core1_src",
 			.parent_data = gcc_pxo_pll8_pll14_pll18_pll0,
-			.num_parents = 5,
+			.num_parents = ARRAY_SIZE(gcc_pxo_pll8_pll14_pll18_pll0),
 			.ops = &clk_dyn_rcg_ops,
 		},
 	},
@@ -2484,7 +2484,7 @@ static struct clk_dyn_rcg gmac_core2_src = {
 		.hw.init = &(struct clk_init_data){
 			.name = "gmac_core2_src",
 			.parent_data = gcc_pxo_pll8_pll14_pll18_pll0,
-			.num_parents = 5,
+			.num_parents = ARRAY_SIZE(gcc_pxo_pll8_pll14_pll18_pll0),
 			.ops = &clk_dyn_rcg_ops,
 		},
 	},
@@ -2556,7 +2556,7 @@ static struct clk_dyn_rcg gmac_core3_src = {
 		.hw.init = &(struct clk_init_data){
 			.name = "gmac_core3_src",
 			.parent_data = gcc_pxo_pll8_pll14_pll18_pll0,
-			.num_parents = 5,
+			.num_parents = ARRAY_SIZE(gcc_pxo_pll8_pll14_pll18_pll0),
 			.ops = &clk_dyn_rcg_ops,
 		},
 	},
@@ -2628,7 +2628,7 @@ static struct clk_dyn_rcg gmac_core4_src = {
 		.hw.init = &(struct clk_init_data){
 			.name = "gmac_core4_src",
 			.parent_data = gcc_pxo_pll8_pll14_pll18_pll0,
-			.num_parents = 5,
+			.num_parents = ARRAY_SIZE(gcc_pxo_pll8_pll14_pll18_pll0),
 			.ops = &clk_dyn_rcg_ops,
 		},
 	},
@@ -2688,7 +2688,7 @@ static struct clk_dyn_rcg nss_tcm_src = {
 		.hw.init = &(struct clk_init_data){
 			.name = "nss_tcm_src",
 			.parent_data = gcc_pxo_pll8_pll14_pll18_pll0,
-			.num_parents = 5,
+			.num_parents = ARRAY_SIZE(gcc_pxo_pll8_pll14_pll18_pll0),
 			.ops = &clk_dyn_rcg_ops,
 		},
 	},
@@ -2766,7 +2766,7 @@ static struct clk_dyn_rcg ubi32_core1_src_clk = {
 		.hw.init = &(struct clk_init_data){
 			.name = "ubi32_core1_src_clk",
 			.parent_data = gcc_pxo_pll8_pll14_pll18_pll0,
-			.num_parents = 5,
+			.num_parents = ARRAY_SIZE(gcc_pxo_pll8_pll14_pll18_pll0),
 			.ops = &clk_dyn_rcg_ops,
 			.flags = CLK_SET_RATE_PARENT | CLK_GET_RATE_NOCACHE,
 		},
@@ -2819,7 +2819,7 @@ static struct clk_dyn_rcg ubi32_core2_src_clk = {
 		.hw.init = &(struct clk_init_data){
 			.name = "ubi32_core2_src_clk",
 			.parent_data = gcc_pxo_pll8_pll14_pll18_pll0,
-			.num_parents = 5,
+			.num_parents = ARRAY_SIZE(gcc_pxo_pll8_pll14_pll18_pll0),
 			.ops = &clk_dyn_rcg_ops,
 			.flags = CLK_SET_RATE_PARENT | CLK_GET_RATE_NOCACHE,
 		},
-- 
2.33.1

[PATCH 05/14] drivers: clk: qcom: gcc-ipq806x: drop hardcoded pxo and cxo source clk

[Ansuel Smith]

We now define these clk in dts. Drop pxo and cxo hardcoded in the gcc
probe function.

Signed-off-by: Ansuel Smith <ansuelsmth@gmail.com>
---
 drivers/clk/qcom/gcc-ipq806x.c | 11 +----------
 1 file changed, 1 insertion(+), 10 deletions(-)

diff --git a/drivers/clk/qcom/gcc-ipq806x.c b/drivers/clk/qcom/gcc-ipq806x.c
index 17ce61f36b08..383494280e3e 100644
--- a/drivers/clk/qcom/gcc-ipq806x.c
+++ b/drivers/clk/qcom/gcc-ipq806x.c
@@ -3133,23 +3133,14 @@ MODULE_DEVICE_TABLE(of, gcc_ipq806x_match_table);
 
 static int gcc_ipq806x_probe(struct platform_device *pdev)
 {
-	struct device *dev = &pdev->dev;
 	struct regmap *regmap;
 	int ret;
 
-	ret = qcom_cc_register_board_clk(dev, "cxo_board", "cxo", 25000000);
-	if (ret)
-		return ret;
-
-	ret = qcom_cc_register_board_clk(dev, "pxo_board", "pxo", 25000000);
-	if (ret)
-		return ret;
-
 	ret = qcom_cc_probe(pdev, &gcc_ipq806x_desc);
 	if (ret)
 		return ret;
 
-	regmap = dev_get_regmap(dev, NULL);
+	regmap = dev_get_regmap(&pdev->dev, NULL);
 	if (!regmap)
 		return -ENODEV;
 
-- 
2.33.1

[PATCH 06/14] drivers: clk: qcom: gcc-ipq806x: use parent_hws where possible

[Ansuel Smith]

Use parent_hws instead of generic parent_data when parents all the
parent are defined in the ipq806x gcc driver.

Signed-off-by: Ansuel Smith <ansuelsmth@gmail.com>
---
 drivers/clk/qcom/gcc-ipq806x.c | 156 ++++++++++++++++-----------------
 1 file changed, 78 insertions(+), 78 deletions(-)

diff --git a/drivers/clk/qcom/gcc-ipq806x.c b/drivers/clk/qcom/gcc-ipq806x.c
index 383494280e3e..ce5654d3e937 100644
--- a/drivers/clk/qcom/gcc-ipq806x.c
+++ b/drivers/clk/qcom/gcc-ipq806x.c
@@ -48,8 +48,8 @@ static struct clk_regmap pll0_vote = {
 	.enable_mask = BIT(0),
 	.hw.init = &(struct clk_init_data){
 		.name = "pll0_vote",
-		.parent_data = &(const struct clk_parent_data){
-			.hw = &pll0.clkr.hw,
+		.parent_hws = (const struct clk_hw*[]){
+			&pll0.clkr.hw,
 		},
 		.num_parents = 1,
 		.ops = &clk_pll_vote_ops,
@@ -108,8 +108,8 @@ static struct clk_regmap pll8_vote = {
 	.enable_mask = BIT(8),
 	.hw.init = &(struct clk_init_data){
 		.name = "pll8_vote",
-		.parent_data = &(const struct clk_parent_data){
-			.hw = &pll8.clkr.hw,
+		.parent_hws = (const struct clk_hw*[]){
+			&pll8.clkr.hw,
 		},
 		.num_parents = 1,
 		.ops = &clk_pll_vote_ops,
@@ -223,8 +223,8 @@ static struct clk_regmap pll14_vote = {
 	.enable_mask = BIT(14),
 	.hw.init = &(struct clk_init_data){
 		.name = "pll14_vote",
-		.parent_data = &(const struct clk_parent_data){
-			.hw = &pll14.clkr.hw,
+		.parent_hws = (const struct clk_hw*[]){
+			&pll14.clkr.hw,
 		},
 		.num_parents = 1,
 		.ops = &clk_pll_vote_ops,
@@ -400,8 +400,8 @@ static struct clk_branch gsbi1_uart_clk = {
 		.enable_mask = BIT(9),
 		.hw.init = &(struct clk_init_data){
 			.name = "gsbi1_uart_clk",
-			.parent_data = &(const struct clk_parent_data){
-				.hw = &gsbi1_uart_src.clkr.hw,
+			.parent_hws = (const struct clk_hw*[]){
+				&gsbi1_uart_src.clkr.hw,
 			},
 			.num_parents = 1,
 			.ops = &clk_branch_ops,
@@ -451,8 +451,8 @@ static struct clk_branch gsbi2_uart_clk = {
 		.enable_mask = BIT(9),
 		.hw.init = &(struct clk_init_data){
 			.name = "gsbi2_uart_clk",
-			.parent_data = &(const struct clk_parent_data){
-				.hw = &gsbi2_uart_src.clkr.hw,
+			.parent_hws = (const struct clk_hw*[]){
+				&gsbi2_uart_src.clkr.hw,
 			},
 			.num_parents = 1,
 			.ops = &clk_branch_ops,
@@ -502,8 +502,8 @@ static struct clk_branch gsbi4_uart_clk = {
 		.enable_mask = BIT(9),
 		.hw.init = &(struct clk_init_data){
 			.name = "gsbi4_uart_clk",
-			.parent_data = &(const struct clk_parent_data){
-				.hw = &gsbi4_uart_src.clkr.hw,
+			.parent_hws = (const struct clk_hw*[]){
+				&gsbi4_uart_src.clkr.hw,
 			},
 			.num_parents = 1,
 			.ops = &clk_branch_ops,
@@ -553,8 +553,8 @@ static struct clk_branch gsbi5_uart_clk = {
 		.enable_mask = BIT(9),
 		.hw.init = &(struct clk_init_data){
 			.name = "gsbi5_uart_clk",
-			.parent_data = &(const struct clk_parent_data){
-				.hw = &gsbi5_uart_src.clkr.hw,
+			.parent_hws = (const struct clk_hw*[]){
+				&gsbi5_uart_src.clkr.hw,
 			},
 			.num_parents = 1,
 			.ops = &clk_branch_ops,
@@ -604,8 +604,8 @@ static struct clk_branch gsbi6_uart_clk = {
 		.enable_mask = BIT(9),
 		.hw.init = &(struct clk_init_data){
 			.name = "gsbi6_uart_clk",
-			.parent_data = &(const struct clk_parent_data){
-				.hw = &gsbi6_uart_src.clkr.hw,
+			.parent_hws = (const struct clk_hw*[]){
+				&gsbi6_uart_src.clkr.hw,
 			},
 			.num_parents = 1,
 			.ops = &clk_branch_ops,
@@ -655,8 +655,8 @@ static struct clk_branch gsbi7_uart_clk = {
 		.enable_mask = BIT(9),
 		.hw.init = &(struct clk_init_data){
 			.name = "gsbi7_uart_clk",
-			.parent_data = &(const struct clk_parent_data){
-				.hw = &gsbi7_uart_src.clkr.hw,
+			.parent_hws = (const struct clk_hw*[]){
+				&gsbi7_uart_src.clkr.hw,
 			},
 			.num_parents = 1,
 			.ops = &clk_branch_ops,
@@ -719,8 +719,8 @@ static struct clk_branch gsbi1_qup_clk = {
 		.enable_mask = BIT(9),
 		.hw.init = &(struct clk_init_data){
 			.name = "gsbi1_qup_clk",
-			.parent_data = &(const struct clk_parent_data){
-				.hw = &gsbi1_qup_src.clkr.hw,
+			.parent_hws = (const struct clk_hw*[]){
+				&gsbi1_qup_src.clkr.hw,
 			},
 			.num_parents = 1,
 			.ops = &clk_branch_ops,
@@ -770,8 +770,8 @@ static struct clk_branch gsbi2_qup_clk = {
 		.enable_mask = BIT(9),
 		.hw.init = &(struct clk_init_data){
 			.name = "gsbi2_qup_clk",
-			.parent_data = &(const struct clk_parent_data){
-				.hw = &gsbi2_qup_src.clkr.hw,
+			.parent_hws = (const struct clk_hw*[]){
+				&gsbi2_qup_src.clkr.hw,
 			},
 			.num_parents = 1,
 			.ops = &clk_branch_ops,
@@ -821,8 +821,8 @@ static struct clk_branch gsbi4_qup_clk = {
 		.enable_mask = BIT(9),
 		.hw.init = &(struct clk_init_data){
 			.name = "gsbi4_qup_clk",
-			.parent_data = &(const struct clk_parent_data){
-				.hw = &gsbi4_qup_src.clkr.hw,
+			.parent_hws = (const struct clk_hw*[]){
+				&gsbi4_qup_src.clkr.hw,
 			},
 			.num_parents = 1,
 			.ops = &clk_branch_ops,
@@ -872,8 +872,8 @@ static struct clk_branch gsbi5_qup_clk = {
 		.enable_mask = BIT(9),
 		.hw.init = &(struct clk_init_data){
 			.name = "gsbi5_qup_clk",
-			.parent_data = &(const struct clk_parent_data){
-				.hw = &gsbi5_qup_src.clkr.hw,
+			.parent_hws = (const struct clk_hw*[]){
+				&gsbi5_qup_src.clkr.hw,
 			},
 			.num_parents = 1,
 			.ops = &clk_branch_ops,
@@ -923,8 +923,8 @@ static struct clk_branch gsbi6_qup_clk = {
 		.enable_mask = BIT(9),
 		.hw.init = &(struct clk_init_data){
 			.name = "gsbi6_qup_clk",
-			.parent_data = &(const struct clk_parent_data){
-				.hw = &gsbi6_qup_src.clkr.hw,
+			.parent_hws = (const struct clk_hw*[]){
+				&gsbi6_qup_src.clkr.hw,
 			},
 			.num_parents = 1,
 			.ops = &clk_branch_ops,
@@ -974,8 +974,8 @@ static struct clk_branch gsbi7_qup_clk = {
 		.enable_mask = BIT(9),
 		.hw.init = &(struct clk_init_data){
 			.name = "gsbi7_qup_clk",
-			.parent_data = &(const struct clk_parent_data){
-				.hw = &gsbi7_qup_src.clkr.hw,
+			.parent_hws = (const struct clk_hw*[]){
+				&gsbi7_qup_src.clkr.hw,
 			},
 			.num_parents = 1,
 			.ops = &clk_branch_ops,
@@ -1126,8 +1126,8 @@ static struct clk_branch gp0_clk = {
 		.enable_mask = BIT(9),
 		.hw.init = &(struct clk_init_data){
 			.name = "gp0_clk",
-			.parent_data = &(const struct clk_parent_data){
-				.hw = &gp0_src.clkr.hw,
+			.parent_hws = (const struct clk_hw*[]){
+				&gp0_src.clkr.hw,
 			},
 			.num_parents = 1,
 			.ops = &clk_branch_ops,
@@ -1177,8 +1177,8 @@ static struct clk_branch gp1_clk = {
 		.enable_mask = BIT(9),
 		.hw.init = &(struct clk_init_data){
 			.name = "gp1_clk",
-			.parent_data = &(const struct clk_parent_data){
-				.hw = &gp1_src.clkr.hw,
+			.parent_hws = (const struct clk_hw*[]){
+				&gp1_src.clkr.hw,
 			},
 			.num_parents = 1,
 			.ops = &clk_branch_ops,
@@ -1228,8 +1228,8 @@ static struct clk_branch gp2_clk = {
 		.enable_mask = BIT(9),
 		.hw.init = &(struct clk_init_data){
 			.name = "gp2_clk",
-			.parent_data = &(const struct clk_parent_data){
-				.hw = &gp2_src.clkr.hw,
+			.parent_hws = (const struct clk_hw*[]){
+				&gp2_src.clkr.hw,
 			},
 			.num_parents = 1,
 			.ops = &clk_branch_ops,
@@ -1284,8 +1284,8 @@ static struct clk_branch prng_clk = {
 		.enable_mask = BIT(10),
 		.hw.init = &(struct clk_init_data){
 			.name = "prng_clk",
-			.parent_data = &(const struct clk_parent_data){
-				.hw = &prng_src.clkr.hw,
+			.parent_hws = (const struct clk_hw*[]){
+				&prng_src.clkr.hw,
 			},
 			.num_parents = 1,
 			.ops = &clk_branch_ops,
@@ -1347,8 +1347,8 @@ static struct clk_branch sdc1_clk = {
 		.enable_mask = BIT(9),
 		.hw.init = &(struct clk_init_data){
 			.name = "sdc1_clk",
-			.parent_data = &(const struct clk_parent_data){
-				.hw = &sdc1_src.clkr.hw,
+			.parent_hws = (const struct clk_hw*[]){
+				&sdc1_src.clkr.hw,
 			},
 			.num_parents = 1,
 			.ops = &clk_branch_ops,
@@ -1397,8 +1397,8 @@ static struct clk_branch sdc3_clk = {
 		.enable_mask = BIT(9),
 		.hw.init = &(struct clk_init_data){
 			.name = "sdc3_clk",
-			.parent_data = &(const struct clk_parent_data){
-				.hw = &sdc3_src.clkr.hw,
+			.parent_hws = (const struct clk_hw*[]){
+				&sdc3_src.clkr.hw,
 			},
 			.num_parents = 1,
 			.ops = &clk_branch_ops,
@@ -1482,8 +1482,8 @@ static struct clk_branch tsif_ref_clk = {
 		.enable_mask = BIT(9),
 		.hw.init = &(struct clk_init_data){
 			.name = "tsif_ref_clk",
-			.parent_data = &(const struct clk_parent_data){
-				.hw = &tsif_ref_src.clkr.hw,
+			.parent_hws = (const struct clk_hw*[]){
+				&tsif_ref_src.clkr.hw,
 			},
 			.num_parents = 1,
 			.ops = &clk_branch_ops,
@@ -1647,8 +1647,8 @@ static struct clk_branch pcie_ref_src_clk = {
 		.enable_mask = BIT(9),
 		.hw.init = &(struct clk_init_data){
 			.name = "pcie_ref_src_clk",
-			.parent_data = &(const struct clk_parent_data){
-				.hw = &pcie_ref_src.clkr.hw,
+			.parent_hws = (const struct clk_hw*[]){
+				&pcie_ref_src.clkr.hw,
 			},
 			.num_parents = 1,
 			.ops = &clk_branch_ops,
@@ -1741,8 +1741,8 @@ static struct clk_branch pcie1_ref_src_clk = {
 		.enable_mask = BIT(9),
 		.hw.init = &(struct clk_init_data){
 			.name = "pcie1_ref_src_clk",
-			.parent_data = &(const struct clk_parent_data){
-				.hw = &pcie1_ref_src.clkr.hw,
+			.parent_hws = (const struct clk_hw*[]){
+				&pcie1_ref_src.clkr.hw,
 			},
 			.num_parents = 1,
 			.ops = &clk_branch_ops,
@@ -1835,8 +1835,8 @@ static struct clk_branch pcie2_ref_src_clk = {
 		.enable_mask = BIT(9),
 		.hw.init = &(struct clk_init_data){
 			.name = "pcie2_ref_src_clk",
-			.parent_data = &(const struct clk_parent_data){
-				.hw = &pcie2_ref_src.clkr.hw,
+			.parent_hws = (const struct clk_hw*[]){
+				&pcie2_ref_src.clkr.hw,
 			},
 			.num_parents = 1,
 			.ops = &clk_branch_ops,
@@ -1934,8 +1934,8 @@ static struct clk_branch sata_rxoob_clk = {
 		.enable_mask = BIT(4),
 		.hw.init = &(struct clk_init_data){
 			.name = "sata_rxoob_clk",
-			.parent_data = &(const struct clk_parent_data){
-				.hw = &sata_ref_src.clkr.hw,
+			.parent_hws = (const struct clk_hw*[]){
+				&sata_ref_src.clkr.hw,
 			},
 			.num_parents = 1,
 			.ops = &clk_branch_ops,
@@ -1952,8 +1952,8 @@ static struct clk_branch sata_pmalive_clk = {
 		.enable_mask = BIT(4),
 		.hw.init = &(struct clk_init_data){
 			.name = "sata_pmalive_clk",
-			.parent_data = &(const struct clk_parent_data){
-				.hw = &sata_ref_src.clkr.hw,
+			.parent_hws = (const struct clk_hw*[]){
+				&sata_ref_src.clkr.hw,
 			},
 			.num_parents = 1,
 			.ops = &clk_branch_ops,
@@ -2077,8 +2077,8 @@ static struct clk_branch usb30_0_branch_clk = {
 		.enable_mask = BIT(4),
 		.hw.init = &(struct clk_init_data){
 			.name = "usb30_0_branch_clk",
-			.parent_data = &(const struct clk_parent_data){
-				.hw = &usb30_master_clk_src.clkr.hw,
+			.parent_hws = (const struct clk_hw*[]){
+				&usb30_master_clk_src.clkr.hw,
 			},
 			.num_parents = 1,
 			.ops = &clk_branch_ops,
@@ -2095,8 +2095,8 @@ static struct clk_branch usb30_1_branch_clk = {
 		.enable_mask = BIT(4),
 		.hw.init = &(struct clk_init_data){
 			.name = "usb30_1_branch_clk",
-			.parent_data = &(const struct clk_parent_data){
-				.hw = &usb30_master_clk_src.clkr.hw,
+			.parent_hws = (const struct clk_hw*[]){
+				&usb30_master_clk_src.clkr.hw,
 			},
 			.num_parents = 1,
 			.ops = &clk_branch_ops,
@@ -2151,8 +2151,8 @@ static struct clk_branch usb30_0_utmi_clk_ctl = {
 		.enable_mask = BIT(4),
 		.hw.init = &(struct clk_init_data){
 			.name = "usb30_0_utmi_clk_ctl",
-			.parent_data = &(const struct clk_parent_data){
-				.hw = &usb30_utmi_clk.clkr.hw,
+			.parent_hws = (const struct clk_hw*[]){
+				&usb30_utmi_clk.clkr.hw,
 			},
 			.num_parents = 1,
 			.ops = &clk_branch_ops,
@@ -2169,8 +2169,8 @@ static struct clk_branch usb30_1_utmi_clk_ctl = {
 		.enable_mask = BIT(4),
 		.hw.init = &(struct clk_init_data){
 			.name = "usb30_1_utmi_clk_ctl",
-			.parent_data = &(const struct clk_parent_data){
-				.hw = &usb30_utmi_clk.clkr.hw,
+			.parent_hws = (const struct clk_hw*[]){
+				&usb30_utmi_clk.clkr.hw,
 			},
 			.num_parents = 1,
 			.ops = &clk_branch_ops,
@@ -2225,8 +2225,8 @@ static struct clk_branch usb_hs1_xcvr_clk = {
 		.enable_mask = BIT(9),
 		.hw.init = &(struct clk_init_data){
 			.name = "usb_hs1_xcvr_clk",
-			.parent_data = &(const struct clk_parent_data){
-				.hw = &usb_hs1_xcvr_clk_src.clkr.hw,
+			.parent_hws = (const struct clk_hw*[]){
+				&usb_hs1_xcvr_clk_src.clkr.hw,
 			},
 			.num_parents = 1,
 			.ops = &clk_branch_ops,
@@ -2291,8 +2291,8 @@ static struct clk_branch usb_fs1_xcvr_clk = {
 		.enable_mask = BIT(9),
 		.hw.init = &(struct clk_init_data){
 			.name = "usb_fs1_xcvr_clk",
-			.parent_data = &(const struct clk_parent_data){
-				.hw = &usb_fs1_xcvr_clk_src.clkr.hw,
+			.parent_hws = (const struct clk_hw*[]){
+				&usb_fs1_xcvr_clk_src.clkr.hw,
 			},
 			.num_parents = 1,
 			.ops = &clk_branch_ops,
@@ -2309,8 +2309,8 @@ static struct clk_branch usb_fs1_sys_clk = {
 		.enable_mask = BIT(4),
 		.hw.init = &(struct clk_init_data){
 			.name = "usb_fs1_sys_clk",
-			.parent_data = &(const struct clk_parent_data){
-				.hw = &usb_fs1_xcvr_clk_src.clkr.hw,
+			.parent_hws = (const struct clk_hw*[]){
+				&usb_fs1_xcvr_clk_src.clkr.hw,
 			},
 			.num_parents = 1,
 			.ops = &clk_branch_ops,
@@ -2428,8 +2428,8 @@ static struct clk_branch gmac_core1_clk = {
 		.enable_mask = BIT(4),
 		.hw.init = &(struct clk_init_data){
 			.name = "gmac_core1_clk",
-			.parent_data = &(const struct clk_parent_data){
-				.hw = &gmac_core1_src.clkr.hw,
+			.parent_hws = (const struct clk_hw*[]){
+				&gmac_core1_src.clkr.hw,
 			},
 			.num_parents = 1,
 			.ops = &clk_branch_ops,
@@ -2500,8 +2500,8 @@ static struct clk_branch gmac_core2_clk = {
 		.enable_mask = BIT(4),
 		.hw.init = &(struct clk_init_data){
 			.name = "gmac_core2_clk",
-			.parent_data = &(const struct clk_parent_data){
-				.hw = &gmac_core2_src.clkr.hw,
+			.parent_hws = (const struct clk_hw*[]){
+				&gmac_core2_src.clkr.hw,
 			},
 			.num_parents = 1,
 			.ops = &clk_branch_ops,
@@ -2572,8 +2572,8 @@ static struct clk_branch gmac_core3_clk = {
 		.enable_mask = BIT(4),
 		.hw.init = &(struct clk_init_data){
 			.name = "gmac_core3_clk",
-			.parent_data = &(const struct clk_parent_data){
-				.hw = &gmac_core3_src.clkr.hw,
+			.parent_hws = (const struct clk_hw*[]){
+				&gmac_core3_src.clkr.hw,
 			},
 			.num_parents = 1,
 			.ops = &clk_branch_ops,
@@ -2644,8 +2644,8 @@ static struct clk_branch gmac_core4_clk = {
 		.enable_mask = BIT(4),
 		.hw.init = &(struct clk_init_data){
 			.name = "gmac_core4_clk",
-			.parent_data = &(const struct clk_parent_data){
-				.hw = &gmac_core4_src.clkr.hw,
+			.parent_hws = (const struct clk_hw*[]){
+				&gmac_core4_src.clkr.hw,
 			},
 			.num_parents = 1,
 			.ops = &clk_branch_ops,
@@ -2702,8 +2702,8 @@ static struct clk_branch nss_tcm_clk = {
 		.enable_mask = BIT(6) | BIT(4),
 		.hw.init = &(struct clk_init_data){
 			.name = "nss_tcm_clk",
-			.parent_data = &(const struct clk_parent_data){
-				.hw = &nss_tcm_src.clkr.hw,
+			.parent_hws = (const struct clk_hw*[]){
+				&nss_tcm_src.clkr.hw,
 			},
 			.num_parents = 1,
 			.ops = &clk_branch_ops,
-- 
2.33.1

[PATCH 07/14] drivers: clk: qcom: gcc-ipq806x: add additional freq nss cores

[Ansuel Smith]

Ipq8065 SoC (an evolution of ipq8064 SoC) contains nss cores that can be
clocked to 800MHz. Add these missing freq to the gcc driver.

Signed-off-by: Ansuel Smith <ansuelsmth@gmail.com>
---
 drivers/clk/qcom/gcc-ipq806x.c | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/drivers/clk/qcom/gcc-ipq806x.c b/drivers/clk/qcom/gcc-ipq806x.c
index ce5654d3e937..d0c5441eb98e 100644
--- a/drivers/clk/qcom/gcc-ipq806x.c
+++ b/drivers/clk/qcom/gcc-ipq806x.c
@@ -242,7 +242,9 @@ static struct clk_regmap pll14_vote = {
 
 static struct pll_freq_tbl pll18_freq_tbl[] = {
 	NSS_PLL_RATE(550000000, 44, 0, 1, 0x01495625),
+	NSS_PLL_RATE(600000000, 48, 0, 1, 0x01495625),
 	NSS_PLL_RATE(733000000, 58, 16, 25, 0x014b5625),
+	NSS_PLL_RATE(800000000, 64, 0, 1, 0x01495625),
 };
 
 static struct clk_pll pll18 = {
@@ -2716,7 +2718,9 @@ static const struct freq_tbl clk_tbl_nss[] = {
 	{ 110000000, P_PLL18, 1, 1, 5 },
 	{ 275000000, P_PLL18, 2, 0, 0 },
 	{ 550000000, P_PLL18, 1, 0, 0 },
+	{ 600000000, P_PLL18, 1, 0, 0 },
 	{ 733000000, P_PLL18, 1, 0, 0 },
+	{ 800000000, P_PLL18, 1, 0, 0 },
 	{ }
 };
 
-- 
2.33.1

[PATCH 08/14] drivers: clk: qcom: gcc-ipq806x: add unusued flag for critical clock

[Ansuel Smith]

Some clocks are used by other devices present on the SoC. For example
the gsbi4_h_clk is used by RPM and is if disabled cause the RPM to
reject any regulator change command. These clock should never be
disabled.

Signed-off-by: Ansuel Smith <ansuelsmth@gmail.com>
---
 drivers/clk/qcom/gcc-ipq806x.c | 9 +++++----
 1 file changed, 5 insertions(+), 4 deletions(-)

diff --git a/drivers/clk/qcom/gcc-ipq806x.c b/drivers/clk/qcom/gcc-ipq806x.c
index d0c5441eb98e..7d1ddbbbc8ec 100644
--- a/drivers/clk/qcom/gcc-ipq806x.c
+++ b/drivers/clk/qcom/gcc-ipq806x.c
@@ -810,7 +810,7 @@ static struct clk_rcg gsbi4_qup_src = {
 			.parent_data = gcc_pxo_pll8,
 			.num_parents = ARRAY_SIZE(gcc_pxo_pll8),
 			.ops = &clk_rcg_ops,
-			.flags = CLK_SET_PARENT_GATE,
+			.flags = CLK_SET_PARENT_GATE | CLK_IGNORE_UNUSED,
 		},
 	},
 };
@@ -828,7 +828,7 @@ static struct clk_branch gsbi4_qup_clk = {
 			},
 			.num_parents = 1,
 			.ops = &clk_branch_ops,
-			.flags = CLK_SET_RATE_PARENT,
+			.flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
 		},
 	},
 };
@@ -912,7 +912,7 @@ static struct clk_rcg gsbi6_qup_src = {
 			.parent_data = gcc_pxo_pll8,
 			.num_parents = ARRAY_SIZE(gcc_pxo_pll8),
 			.ops = &clk_rcg_ops,
-			.flags = CLK_SET_PARENT_GATE,
+			.flags = CLK_SET_PARENT_GATE | CLK_IGNORE_UNUSED,
 		},
 	},
 };
@@ -981,7 +981,7 @@ static struct clk_branch gsbi7_qup_clk = {
 			},
 			.num_parents = 1,
 			.ops = &clk_branch_ops,
-			.flags = CLK_SET_RATE_PARENT,
+			.flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
 		},
 	},
 };
@@ -1027,6 +1027,7 @@ static struct clk_branch gsbi4_h_clk = {
 		.hw.init = &(struct clk_init_data){
 			.name = "gsbi4_h_clk",
 			.ops = &clk_branch_ops,
+			.flags = CLK_IGNORE_UNUSED,
 		},
 	},
 };
-- 
2.33.1

[PATCH 09/14] drivers: clk: qcom: gcc-ipq806x: add additional freq for sdc table

[Ansuel Smith]

Add additional freq supported for the sdc table.

Signed-off-by: Ansuel Smith <ansuelsmth@gmail.com>
---
 drivers/clk/qcom/gcc-ipq806x.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/clk/qcom/gcc-ipq806x.c b/drivers/clk/qcom/gcc-ipq806x.c
index 7d1ddbbbc8ec..0923d7f79a1c 100644
--- a/drivers/clk/qcom/gcc-ipq806x.c
+++ b/drivers/clk/qcom/gcc-ipq806x.c
@@ -1304,6 +1304,7 @@ static const struct freq_tbl clk_tbl_sdc[] = {
 	{  20210000, P_PLL8,  1, 1,  19 },
 	{  24000000, P_PLL8,  4, 1,   4 },
 	{  48000000, P_PLL8,  4, 1,   2 },
+	{  52000000, P_PLL8,  1, 2,  15 }, /* 51.2 Mhz */
 	{  64000000, P_PLL8,  3, 1,   2 },
 	{  96000000, P_PLL8,  4, 0,   0 },
 	{ 192000000, P_PLL8,  2, 0,   0 },
-- 
2.33.1

[PATCH 10/14] dt-bindings: clock: add ipq8064 ce5 clk define

[Ansuel Smith]

Add ipq8064 ce5 clk define needed for CryptoEngine in gcc driver.

Signed-off-by: Ansuel Smith <ansuelsmth@gmail.com>
---
 include/dt-bindings/clock/qcom,gcc-ipq806x.h | 5 ++++-
 1 file changed, 4 insertions(+), 1 deletion(-)

diff --git a/include/dt-bindings/clock/qcom,gcc-ipq806x.h b/include/dt-bindings/clock/qcom,gcc-ipq806x.h
index 7deec14a6dee..02262d2ac899 100644
--- a/include/dt-bindings/clock/qcom,gcc-ipq806x.h
+++ b/include/dt-bindings/clock/qcom,gcc-ipq806x.h
@@ -240,7 +240,7 @@
 #define PLL14					232
 #define PLL14_VOTE				233
 #define PLL18					234
-#define CE5_SRC					235
+#define CE5_A_CLK				235
 #define CE5_H_CLK				236
 #define CE5_CORE_CLK				237
 #define CE3_SLEEP_CLK				238
@@ -283,5 +283,8 @@
 #define EBI2_AON_CLK				281
 #define NSSTCM_CLK_SRC				282
 #define NSSTCM_CLK				283
+#define CE5_A_CLK_SRC				285
+#define CE5_H_CLK_SRC				286
+#define CE5_CORE_CLK_SRC			287
 
 #endif
-- 
2.33.1

[PATCH 11/14] drivers: clk: qcom: gcc-ipq806x: add CryptoEngine clocks

[Ansuel Smith]

Add missing CryptoEngine clocks and pll11 required clock.

Signed-off-by: Ansuel Smith <ansuelsmth@gmail.com>
---
 drivers/clk/qcom/gcc-ipq806x.c | 244 +++++++++++++++++++++++++++++++++
 1 file changed, 244 insertions(+)

diff --git a/drivers/clk/qcom/gcc-ipq806x.c b/drivers/clk/qcom/gcc-ipq806x.c
index 0923d7f79a1c..46d0fe511868 100644
--- a/drivers/clk/qcom/gcc-ipq806x.c
+++ b/drivers/clk/qcom/gcc-ipq806x.c
@@ -268,6 +268,24 @@ static struct clk_pll pll18 = {
 	},
 };
 
+static struct clk_pll pll11 = {
+	.l_reg = 0x3184,
+	.m_reg = 0x3188,
+	.n_reg = 0x318c,
+	.config_reg = 0x3194,
+	.mode_reg = 0x3180,
+	.status_reg = 0x3198,
+	.status_bit = 16,
+	.clkr.hw.init = &(struct clk_init_data){
+		.name = "pll11",
+		.parent_data = &(const struct clk_parent_data){
+			.fw_name = "pxo",
+		},
+		.num_parents = 1,
+		.ops = &clk_pll_ops,
+	},
+};
+
 enum {
 	P_PXO,
 	P_PLL8,
@@ -276,6 +294,7 @@ enum {
 	P_CXO,
 	P_PLL14,
 	P_PLL18,
+	P_PLL11,
 };
 
 static const struct parent_map gcc_pxo_pll8_map[] = {
@@ -343,6 +362,44 @@ static const struct clk_parent_data gcc_pxo_pll8_pll14_pll18_pll0[] = {
 	{ .hw = &pll18.clkr.hw },
 };
 
+static const struct parent_map gcc_pxo_pll8_pll0_pll14_pll18_pll11_map[] = {
+	{ P_PXO, 0 },
+	{ P_PLL8, 4 },
+	{ P_PLL0, 2 },
+	{ P_PLL14, 5 },
+	{ P_PLL18, 1 },
+	{ P_PLL11, 3 },
+};
+
+static const struct clk_parent_data gcc_pxo_pll8_pll0_pll14_pll18_pll11[] = {
+	{ .fw_name = "pxo" },
+	{ .hw = &pll8_vote.hw },
+	{ .hw = &pll0_vote.hw },
+	{ .hw = &pll14.clkr.hw },
+	{ .hw = &pll18.clkr.hw },
+	{ .hw = &pll11.clkr.hw },
+
+};
+
+static const struct parent_map gcc_pxo_pll3_pll0_pll14_pll18_pll11_map[] = {
+	{ P_PXO, 0 },
+	{ P_PLL3, 6 },
+	{ P_PLL0, 2 },
+	{ P_PLL14, 5 },
+	{ P_PLL18, 1 },
+	{ P_PLL11, 3 },
+};
+
+static const struct clk_parent_data gcc_pxo_pll3_pll0_pll14_pll18_pll11[] = {
+	{ .fw_name = "pxo" },
+	{ .hw = &pll3.clkr.hw },
+	{ .hw = &pll0_vote.hw },
+	{ .hw = &pll14.clkr.hw },
+	{ .hw = &pll18.clkr.hw },
+	{ .hw = &pll11.clkr.hw },
+
+};
+
 static struct freq_tbl clk_tbl_gsbi_uart[] = {
 	{  1843200, P_PLL8, 2,  6, 625 },
 	{  3686400, P_PLL8, 2, 12, 625 },
@@ -2832,6 +2889,186 @@ static struct clk_dyn_rcg ubi32_core2_src_clk = {
 	},
 };
 
+static const struct freq_tbl clk_tbl_ce5_core[] = {
+	{ 150000000, P_PLL3, 8, 1, 1 },
+	{ 213200000, P_PLL11, 5, 1, 1 },
+	{ }
+};
+
+static struct clk_dyn_rcg ce5_core_src = {
+	.ns_reg[0] = 0x36C4,
+	.ns_reg[1] = 0x36C8,
+	.bank_reg = 0x36C0,
+	.s[0] = {
+		.src_sel_shift = 0,
+		.parent_map = gcc_pxo_pll3_pll0_pll14_pll18_pll11_map,
+	},
+	.s[1] = {
+		.src_sel_shift = 0,
+		.parent_map = gcc_pxo_pll3_pll0_pll14_pll18_pll11_map,
+	},
+	.p[0] = {
+		.pre_div_shift = 3,
+		.pre_div_width = 4,
+	},
+	.p[1] = {
+		.pre_div_shift = 3,
+		.pre_div_width = 4,
+	},
+	.mux_sel_bit = 0,
+	.freq_tbl = clk_tbl_ce5_core,
+	.clkr = {
+		.enable_reg = 0x36C0,
+		.enable_mask = BIT(1),
+		.hw.init = &(struct clk_init_data){
+			.name = "ce5_core_src",
+			.parent_data = gcc_pxo_pll3_pll0_pll14_pll18_pll11,
+			.num_parents = ARRAY_SIZE(gcc_pxo_pll3_pll0_pll14_pll18_pll11),
+			.ops = &clk_dyn_rcg_ops,
+		},
+	},
+};
+
+static struct clk_branch ce5_core_clk = {
+	.halt_reg = 0x2FDC,
+	.halt_bit = 5,
+	.hwcg_reg = 0x36CC,
+	.hwcg_bit = 6,
+	.clkr = {
+		.enable_reg = 0x36CC,
+		.enable_mask = BIT(4),
+		.hw.init = &(struct clk_init_data){
+			.name = "ce5_core_clk",
+			.parent_hws = (const struct clk_hw*[]){
+				&ce5_core_src.clkr.hw,
+			},
+			.num_parents = 1,
+			.ops = &clk_branch_ops,
+			.flags = CLK_SET_RATE_PARENT,
+		},
+	},
+};
+
+static const struct freq_tbl clk_tbl_ce5_a_clk[] = {
+	{ 160000000, P_PLL0, 5, 1, 1 },
+	{ 213200000, P_PLL11, 5, 1, 1 },
+	{ }
+};
+
+static struct clk_dyn_rcg ce5_a_clk_src = {
+	.ns_reg[0] = 0x3d84,
+	.ns_reg[1] = 0x3d88,
+	.bank_reg = 0x3d80,
+	.s[0] = {
+		.src_sel_shift = 0,
+		.parent_map = gcc_pxo_pll8_pll0_pll14_pll18_pll11_map,
+	},
+	.s[1] = {
+		.src_sel_shift = 0,
+		.parent_map = gcc_pxo_pll8_pll0_pll14_pll18_pll11_map,
+	},
+	.p[0] = {
+		.pre_div_shift = 3,
+		.pre_div_width = 4,
+	},
+	.p[1] = {
+		.pre_div_shift = 3,
+		.pre_div_width = 4,
+	},
+	.mux_sel_bit = 0,
+	.freq_tbl = clk_tbl_ce5_a_clk,
+	.clkr = {
+		.enable_reg = 0x3d80,
+		.enable_mask = BIT(1),
+		.hw.init = &(struct clk_init_data){
+			.name = "ce5_a_clk_src",
+			.parent_data = gcc_pxo_pll8_pll0_pll14_pll18_pll11,
+			.num_parents = ARRAY_SIZE(gcc_pxo_pll8_pll0_pll14_pll18_pll11),
+			.ops = &clk_dyn_rcg_ops,
+		},
+	},
+};
+
+static struct clk_branch ce5_a_clk = {
+	.halt_reg = 0x3c20,
+	.halt_bit = 12,
+	.hwcg_reg = 0x3d8c,
+	.hwcg_bit = 6,
+	.clkr = {
+		.enable_reg = 0x3d8c,
+		.enable_mask = BIT(4),
+		.hw.init = &(struct clk_init_data){
+			.name = "ce5_a_clk",
+			.parent_hws = (const struct clk_hw*[]){
+				&ce5_a_clk_src.clkr.hw,
+			},
+			.num_parents = 1,
+			.ops = &clk_branch_ops,
+			.flags = CLK_SET_RATE_PARENT,
+		},
+	},
+};
+
+static const struct freq_tbl clk_tbl_ce5_h_clk[] = {
+	{ 160000000, P_PLL0, 5, 1, 1 },
+	{ 213200000, P_PLL11, 5, 1, 1 },
+	{ }
+};
+
+static struct clk_dyn_rcg ce5_h_clk_src = {
+	.ns_reg[0] = 0x3c64,
+	.ns_reg[1] = 0x3c68,
+	.bank_reg = 0x3c60,
+	.s[0] = {
+		.src_sel_shift = 0,
+		.parent_map = gcc_pxo_pll8_pll0_pll14_pll18_pll11_map,
+	},
+	.s[1] = {
+		.src_sel_shift = 0,
+		.parent_map = gcc_pxo_pll8_pll0_pll14_pll18_pll11_map,
+	},
+	.p[0] = {
+		.pre_div_shift = 3,
+		.pre_div_width = 4,
+	},
+	.p[1] = {
+		.pre_div_shift = 3,
+		.pre_div_width = 4,
+	},
+	.mux_sel_bit = 0,
+	.freq_tbl = clk_tbl_ce5_h_clk,
+	.clkr = {
+		.enable_reg = 0x3c60,
+		.enable_mask = BIT(1),
+		.hw.init = &(struct clk_init_data){
+			.name = "ce5_h_clk_src",
+			.parent_data = gcc_pxo_pll8_pll0_pll14_pll18_pll11,
+			.num_parents = ARRAY_SIZE(gcc_pxo_pll8_pll0_pll14_pll18_pll11),
+			.ops = &clk_dyn_rcg_ops,
+		},
+	},
+};
+
+static struct clk_branch ce5_h_clk = {
+	.halt_reg = 0x3c20,
+	.halt_bit = 11,
+	.hwcg_reg = 0x3c6c,
+	.hwcg_bit = 6,
+	.clkr = {
+		.enable_reg = 0x3c6c,
+		.enable_mask = BIT(4),
+		.hw.init = &(struct clk_init_data){
+			.name = "ce5_h_clk",
+			.parent_hws = (const struct clk_hw*[]){
+				&ce5_h_clk_src.clkr.hw,
+			},
+			.num_parents = 1,
+			.ops = &clk_branch_ops,
+			.flags = CLK_SET_RATE_PARENT,
+		},
+	},
+};
+
 static struct clk_regmap *gcc_ipq806x_clks[] = {
 	[PLL0] = &pll0.clkr,
 	[PLL0_VOTE] = &pll0_vote,
@@ -2839,6 +3076,7 @@ static struct clk_regmap *gcc_ipq806x_clks[] = {
 	[PLL4_VOTE] = &pll4_vote,
 	[PLL8] = &pll8.clkr,
 	[PLL8_VOTE] = &pll8_vote,
+	[PLL11] = &pll11.clkr,
 	[PLL14] = &pll14.clkr,
 	[PLL14_VOTE] = &pll14_vote,
 	[PLL18] = &pll18.clkr,
@@ -2953,6 +3191,12 @@ static struct clk_regmap *gcc_ipq806x_clks[] = {
 	[PLL9] = &hfpll0.clkr,
 	[PLL10] = &hfpll1.clkr,
 	[PLL12] = &hfpll_l2.clkr,
+	[CE5_A_CLK_SRC] = &ce5_a_clk_src.clkr,
+	[CE5_A_CLK] = &ce5_a_clk.clkr,
+	[CE5_H_CLK_SRC] = &ce5_h_clk_src.clkr,
+	[CE5_H_CLK] = &ce5_h_clk.clkr,
+	[CE5_CORE_CLK_SRC] = &ce5_core_src.clkr,
+	[CE5_CORE_CLK] = &ce5_core_clk.clkr,
 };
 
 static const struct qcom_reset_map gcc_ipq806x_resets[] = {
-- 
2.33.1

[PATCH 12/14] dt-bindings: reset: add ipq8064 ce5 resets

[Ansuel Smith]

Add ipq8064 ce5 resets needed for CryptoEngine gcc driver.

Signed-off-by: Ansuel Smith <ansuelsmth@gmail.com>
---
 include/dt-bindings/reset/qcom,gcc-ipq806x.h | 5 +++++
 1 file changed, 5 insertions(+)

diff --git a/include/dt-bindings/reset/qcom,gcc-ipq806x.h b/include/dt-bindings/reset/qcom,gcc-ipq806x.h
index 26b6f9200620..020c9cf18751 100644
--- a/include/dt-bindings/reset/qcom,gcc-ipq806x.h
+++ b/include/dt-bindings/reset/qcom,gcc-ipq806x.h
@@ -163,5 +163,10 @@
 #define NSS_CAL_PRBS_RST_N_RESET			154
 #define NSS_LCKDT_RST_N_RESET				155
 #define NSS_SRDS_N_RESET				156
+#define CRYPTO_ENG1_RESET				157
+#define CRYPTO_ENG2_RESET				158
+#define CRYPTO_ENG3_RESET				159
+#define CRYPTO_ENG4_RESET				160
+#define CRYPTO_AHB_RESET				161
 
 #endif
-- 
2.33.1

[PATCH 13/14] drivers: clk: qcom: gcc-ipq806x: add CryptoEngine resets

[Ansuel Smith]

Add missing CryptoEngine resets.

Signed-off-by: Ansuel Smith <ansuelsmth@gmail.com>
---
 drivers/clk/qcom/gcc-ipq806x.c | 5 +++++
 1 file changed, 5 insertions(+)

diff --git a/drivers/clk/qcom/gcc-ipq806x.c b/drivers/clk/qcom/gcc-ipq806x.c
index 46d0fe511868..201c967fc74d 100644
--- a/drivers/clk/qcom/gcc-ipq806x.c
+++ b/drivers/clk/qcom/gcc-ipq806x.c
@@ -3328,6 +3328,11 @@ static const struct qcom_reset_map gcc_ipq806x_resets[] = {
 	[GMAC_CORE3_RESET] = { 0x3cfc, 0 },
 	[GMAC_CORE4_RESET] = { 0x3d1c, 0 },
 	[GMAC_AHB_RESET] = { 0x3e24, 0 },
+	[CRYPTO_ENG1_RESET] = { 0x3e00, 0},
+	[CRYPTO_ENG2_RESET] = { 0x3e04, 0},
+	[CRYPTO_ENG3_RESET] = { 0x3e08, 0},
+	[CRYPTO_ENG4_RESET] = { 0x3e0c, 0},
+	[CRYPTO_AHB_RESET] = { 0x3e10, 0},
 	[NSS_CH0_RST_RX_CLK_N_RESET] = { 0x3b60, 0 },
 	[NSS_CH0_RST_TX_CLK_N_RESET] = { 0x3b60, 1 },
 	[NSS_CH0_RST_RX_125M_N_RESET] = { 0x3b60, 2 },
-- 
2.33.1

[PATCH 14/14] ARM: dts: qcom: Add syscon and cxo/pxo clock to gcc node for ipq8064

[Ansuel Smith]

Add syscon compatible required for tsens driver to correctly probe driver
and access the reg. Also add cxo and pxo tag and declare them as gcc clock
now requires them for the ipq8064 gcc driver that has now been modernized.

Signed-off-by: Ansuel Smith <ansuelsmth@gmail.com>
---
 arch/arm/boot/dts/qcom-ipq8064.dtsi | 8 +++++---
 1 file changed, 5 insertions(+), 3 deletions(-)

diff --git a/arch/arm/boot/dts/qcom-ipq8064.dtsi b/arch/arm/boot/dts/qcom-ipq8064.dtsi
index 11481313bdb6..5524a68cf3d1 100644
--- a/arch/arm/boot/dts/qcom-ipq8064.dtsi
+++ b/arch/arm/boot/dts/qcom-ipq8064.dtsi
@@ -298,13 +298,13 @@ smem: smem@41000000 {
 	};
 
 	clocks {
-		cxo_board {
+		cxo_board: cxo_board {
 			compatible = "fixed-clock";
 			#clock-cells = <0>;
 			clock-frequency = <25000000>;
 		};
 
-		pxo_board {
+		pxo_board: pxo_board {
 			compatible = "fixed-clock";
 			#clock-cells = <0>;
 			clock-frequency = <25000000>;
@@ -736,7 +736,9 @@ tsens_calib_backup: calib_backup@410 {
 		};
 
 		gcc: clock-controller@900000 {
-			compatible = "qcom,gcc-ipq8064";
+			compatible = "qcom,gcc-ipq8064", "syscon";
+			clocks = <&pxo_board>, <&cxo_board>;
+			clock-names = "pxo", "cxo";
 			reg = <0x00900000 0x4000>;
 			#clock-cells = <1>;
 			#reset-cells = <1>;
-- 
2.33.1

Re: [PATCH 01/14] dt-bindings: clock: Document qcom,gcc-ipq8064 binding

[Rob Herring]

On Tue, 18 Jan 2022 01:44:21 +0100, Ansuel Smith wrote:
> Document qcom,gcc-ipq8064 binding needed to declare pxo and cxo source
> clocks. The gcc node is also used by the tsens driver, already Documented,
> to get the calib nvmem cells and the base reg from gcc.
> 
> Signed-off-by: Ansuel Smith <ansuelsmth@gmail.com>
> ---
>  .../bindings/clock/qcom,gcc-ipq8064.yaml      | 67 +++++++++++++++++++
>  1 file changed, 67 insertions(+)
>  create mode 100644 Documentation/devicetree/bindings/clock/qcom,gcc-ipq8064.yaml
> 

My bot found errors running 'make DT_CHECKER_FLAGS=-m dt_binding_check'
on your patch (DT_CHECKER_FLAGS is new in v5.13):

yamllint warnings/errors:

dtschema/dtc warnings/errors:
/builds/robherring/linux-dt-review/Documentation/devicetree/bindings/clock/qcom,gcc-ipq8064.example.dt.yaml: clock-controller@900000: compatible: ['qcom,gcc-ipq8064', 'syscon'] is too long
	From schema: /builds/robherring/linux-dt-review/Documentation/devicetree/bindings/clock/qcom,gcc.yaml
/builds/robherring/linux-dt-review/Documentation/devicetree/bindings/clock/qcom,gcc-ipq8064.example.dt.yaml: clock-controller@900000: compatible: Additional items are not allowed ('syscon' was unexpected)
	From schema: /builds/robherring/linux-dt-review/Documentation/devicetree/bindings/clock/qcom,gcc.yaml
/builds/robherring/linux-dt-review/Documentation/devicetree/bindings/clock/qcom,gcc-ipq8064.example.dt.yaml: clock-controller@900000: 'clock-names', 'clocks' do not match any of the regexes: 'pinctrl-[0-9]+'
	From schema: /builds/robherring/linux-dt-review/Documentation/devicetree/bindings/clock/qcom,gcc.yaml
/builds/robherring/linux-dt-review/Documentation/devicetree/bindings/clock/qcom,gcc-ipq8064.example.dt.yaml: clock-controller@900000: compatible: ['qcom,gcc-ipq8064', 'syscon'] is too long
	From schema: /builds/robherring/linux-dt-review/Documentation/devicetree/bindings/clock/qcom,gcc-ipq8064.yaml
/builds/robherring/linux-dt-review/Documentation/devicetree/bindings/clock/qcom,gcc-ipq8064.example.dt.yaml: clock-controller@900000: compatible: Additional items are not allowed ('syscon' was unexpected)
	From schema: /builds/robherring/linux-dt-review/Documentation/devicetree/bindings/clock/qcom,gcc-ipq8064.yaml

doc reference errors (make refcheckdocs):

See https://patchwork.ozlabs.org/patch/1581028

This check can fail if there are any dependencies. The base for a patch
series is generally the most recent rc1.

If you already ran 'make dt_binding_check' and didn't see the above
error(s), then make sure 'yamllint' is installed and dt-schema is up to
date:

pip3 install dtschema --upgrade

Please check and re-submit.

Re: [PATCH 03/14] drivers: clk: qcom: gcc-ipq806x: convert parent_names to parent_data

[Marijn Suijten]

On 2022-01-18 01:44:23, Ansuel Smith wrote:
> Convert parent_names to parent_data to modernize the driver.
> 
> Signed-off-by: Ansuel Smith <ansuelsmth@gmail.com>
> ---
>  drivers/clk/qcom/gcc-ipq806x.c | 300 ++++++++++++++++++++-------------
>  1 file changed, 187 insertions(+), 113 deletions(-)
> 
> diff --git a/drivers/clk/qcom/gcc-ipq806x.c b/drivers/clk/qcom/gcc-ipq806x.c
> index 34cddf461dba..cbacd56f52d4 100644
> --- a/drivers/clk/qcom/gcc-ipq806x.c
> +++ b/drivers/clk/qcom/gcc-ipq806x.c
> @@ -35,7 +35,9 @@ static struct clk_pll pll0 = {
>  	.status_bit = 16,
>  	.clkr.hw.init = &(struct clk_init_data){
>  		.name = "pll0",
> -		.parent_names = (const char *[]){ "pxo" },
> +		.parent_data = &(const struct clk_parent_data){
> +			.fw_name = "pxo",
> +		},
>  		.num_parents = 1,
>  		.ops = &clk_pll_ops,
>  	},
> @@ -46,7 +48,9 @@ static struct clk_regmap pll0_vote = {
>  	.enable_mask = BIT(0),
>  	.hw.init = &(struct clk_init_data){
>  		.name = "pll0_vote",
> -		.parent_names = (const char *[]){ "pll0" },
> +		.parent_data = &(const struct clk_parent_data){
> +			.hw = &pll0.clkr.hw,

Much like the other "gcc modernization" patches referred to in the cover
letter, this could be converted to parent_hws directly instead of seeing
an intermediate clk_parent_data + .hw = state.  You can effectively
squash patch 06 into this and retitle.

- Marijn

> +		},
>  		.num_parents = 1,
>  		.ops = &clk_pll_vote_ops,
>  	},
> @@ -62,7 +66,9 @@ static struct clk_pll pll3 = {
>  	.status_bit = 16,
>  	.clkr.hw.init = &(struct clk_init_data){
>  		.name = "pll3",
> -		.parent_names = (const char *[]){ "pxo" },
> +		.parent_data = &(const struct clk_parent_data){
> +			.fw_name = "pxo",
> +		},
>  		.num_parents = 1,
>  		.ops = &clk_pll_ops,
>  	},
> @@ -89,7 +95,9 @@ static struct clk_pll pll8 = {
>  	.status_bit = 16,
>  	.clkr.hw.init = &(struct clk_init_data){
>  		.name = "pll8",
> -		.parent_names = (const char *[]){ "pxo" },
> +		.parent_data = &(const struct clk_parent_data){
> +			.fw_name = "pxo",
> +		},
>  		.num_parents = 1,
>  		.ops = &clk_pll_ops,
>  	},
> @@ -100,7 +108,9 @@ static struct clk_regmap pll8_vote = {
>  	.enable_mask = BIT(8),
>  	.hw.init = &(struct clk_init_data){
>  		.name = "pll8_vote",
> -		.parent_names = (const char *[]){ "pll8" },
> +		.parent_data = &(const struct clk_parent_data){
> +			.hw = &pll8.clkr.hw,
> +		},
>  		.num_parents = 1,
>  		.ops = &clk_pll_vote_ops,
>  	},
> @@ -123,7 +133,9 @@ static struct hfpll_data hfpll0_data = {
>  static struct clk_hfpll hfpll0 = {
>  	.d = &hfpll0_data,
>  	.clkr.hw.init = &(struct clk_init_data){
> -		.parent_names = (const char *[]){ "pxo" },
> +		.parent_data = &(const struct clk_parent_data){
> +			.fw_name = "pxo",
> +		},
>  		.num_parents = 1,
>  		.name = "hfpll0",
>  		.ops = &clk_ops_hfpll,
> @@ -149,7 +161,9 @@ static struct hfpll_data hfpll1_data = {
>  static struct clk_hfpll hfpll1 = {
>  	.d = &hfpll1_data,
>  	.clkr.hw.init = &(struct clk_init_data){
> -		.parent_names = (const char *[]){ "pxo" },
> +		.parent_data = &(const struct clk_parent_data){
> +			.fw_name = "pxo",
> +		},
>  		.num_parents = 1,
>  		.name = "hfpll1",
>  		.ops = &clk_ops_hfpll,
> @@ -175,7 +189,9 @@ static struct hfpll_data hfpll_l2_data = {
>  static struct clk_hfpll hfpll_l2 = {
>  	.d = &hfpll_l2_data,
>  	.clkr.hw.init = &(struct clk_init_data){
> -		.parent_names = (const char *[]){ "pxo" },
> +		.parent_data = &(const struct clk_parent_data){
> +			.fw_name = "pxo",
> +		},
>  		.num_parents = 1,
>  		.name = "hfpll_l2",
>  		.ops = &clk_ops_hfpll,
> @@ -194,7 +210,9 @@ static struct clk_pll pll14 = {
>  	.status_bit = 16,
>  	.clkr.hw.init = &(struct clk_init_data){
>  		.name = "pll14",
> -		.parent_names = (const char *[]){ "pxo" },
> +		.parent_data = &(const struct clk_parent_data){
> +			.fw_name = "pxo",
> +		},
>  		.num_parents = 1,
>  		.ops = &clk_pll_ops,
>  	},
> @@ -205,7 +223,9 @@ static struct clk_regmap pll14_vote = {
>  	.enable_mask = BIT(14),
>  	.hw.init = &(struct clk_init_data){
>  		.name = "pll14_vote",
> -		.parent_names = (const char *[]){ "pll14" },
> +		.parent_data = &(const struct clk_parent_data){
> +			.hw = &pll14.clkr.hw,
> +		},
>  		.num_parents = 1,
>  		.ops = &clk_pll_vote_ops,
>  	},
> @@ -238,7 +258,9 @@ static struct clk_pll pll18 = {
>  	.freq_tbl = pll18_freq_tbl,
>  	.clkr.hw.init = &(struct clk_init_data){
>  		.name = "pll18",
> -		.parent_names = (const char *[]){ "pxo" },
> +		.parent_data = &(const struct clk_parent_data){
> +			.fw_name = "pxo",
> +		},
>  		.num_parents = 1,
>  		.ops = &clk_pll_ops,
>  	},
> @@ -259,9 +281,9 @@ static const struct parent_map gcc_pxo_pll8_map[] = {
>  	{ P_PLL8, 3 }
>  };
>  
> -static const char * const gcc_pxo_pll8[] = {
> -	"pxo",
> -	"pll8_vote",
> +static const struct clk_parent_data gcc_pxo_pll8[] = {
> +	{ .fw_name = "pxo" },
> +	{ .hw = &pll8_vote.hw },
>  };
>  
>  static const struct parent_map gcc_pxo_pll8_cxo_map[] = {
> @@ -270,10 +292,10 @@ static const struct parent_map gcc_pxo_pll8_cxo_map[] = {
>  	{ P_CXO, 5 }
>  };
>  
> -static const char * const gcc_pxo_pll8_cxo[] = {
> -	"pxo",
> -	"pll8_vote",
> -	"cxo",
> +static const struct clk_parent_data gcc_pxo_pll8_cxo[] = {
> +	{ .fw_name = "pxo" },
> +	{ .hw = &pll8_vote.hw },
> +	{ .fw_name = "cxo" },
>  };
>  
>  static const struct parent_map gcc_pxo_pll3_map[] = {
> @@ -286,9 +308,9 @@ static const struct parent_map gcc_pxo_pll3_sata_map[] = {
>  	{ P_PLL3, 6 }
>  };
>  
> -static const char * const gcc_pxo_pll3[] = {
> -	"pxo",
> -	"pll3",
> +static const struct clk_parent_data gcc_pxo_pll3[] = {
> +	{ .fw_name = "pxo" },
> +	{ .hw = &pll3.clkr.hw },
>  };
>  
>  static const struct parent_map gcc_pxo_pll8_pll0_map[] = {
> @@ -297,10 +319,10 @@ static const struct parent_map gcc_pxo_pll8_pll0_map[] = {
>  	{ P_PLL0, 2 }
>  };
>  
> -static const char * const gcc_pxo_pll8_pll0[] = {
> -	"pxo",
> -	"pll8_vote",
> -	"pll0_vote",
> +static const struct clk_parent_data gcc_pxo_pll8_pll0[] = {
> +	{ .fw_name = "pxo" },
> +	{ .hw = &pll8_vote.hw },
> +	{ .hw = &pll0_vote.hw },
>  };
>  
>  static const struct parent_map gcc_pxo_pll8_pll14_pll18_pll0_map[] = {
> @@ -311,12 +333,12 @@ static const struct parent_map gcc_pxo_pll8_pll14_pll18_pll0_map[] = {
>  	{ P_PLL18, 1 }
>  };
>  
> -static const char * const gcc_pxo_pll8_pll14_pll18_pll0[] = {
> -	"pxo",
> -	"pll8_vote",
> -	"pll0_vote",
> -	"pll14",
> -	"pll18",
> +static const struct clk_parent_data gcc_pxo_pll8_pll14_pll18_pll0[] = {
> +	{ .fw_name = "pxo" },
> +	{ .hw = &pll8_vote.hw },
> +	{ .hw = &pll0_vote.hw },
> +	{ .hw = &pll14.clkr.hw },
> +	{ .hw = &pll18.clkr.hw },
>  };
>  
>  static struct freq_tbl clk_tbl_gsbi_uart[] = {
> @@ -362,7 +384,7 @@ static struct clk_rcg gsbi1_uart_src = {
>  		.enable_mask = BIT(11),
>  		.hw.init = &(struct clk_init_data){
>  			.name = "gsbi1_uart_src",
> -			.parent_names = gcc_pxo_pll8,
> +			.parent_data = gcc_pxo_pll8,
>  			.num_parents = 2,
>  			.ops = &clk_rcg_ops,
>  			.flags = CLK_SET_PARENT_GATE,
> @@ -378,8 +400,8 @@ static struct clk_branch gsbi1_uart_clk = {
>  		.enable_mask = BIT(9),
>  		.hw.init = &(struct clk_init_data){
>  			.name = "gsbi1_uart_clk",
> -			.parent_names = (const char *[]){
> -				"gsbi1_uart_src",
> +			.parent_data = &(const struct clk_parent_data){
> +				.hw = &gsbi1_uart_src.clkr.hw,
>  			},
>  			.num_parents = 1,
>  			.ops = &clk_branch_ops,
> @@ -413,7 +435,7 @@ static struct clk_rcg gsbi2_uart_src = {
>  		.enable_mask = BIT(11),
>  		.hw.init = &(struct clk_init_data){
>  			.name = "gsbi2_uart_src",
> -			.parent_names = gcc_pxo_pll8,
> +			.parent_data = gcc_pxo_pll8,
>  			.num_parents = 2,
>  			.ops = &clk_rcg_ops,
>  			.flags = CLK_SET_PARENT_GATE,
> @@ -429,8 +451,8 @@ static struct clk_branch gsbi2_uart_clk = {
>  		.enable_mask = BIT(9),
>  		.hw.init = &(struct clk_init_data){
>  			.name = "gsbi2_uart_clk",
> -			.parent_names = (const char *[]){
> -				"gsbi2_uart_src",
> +			.parent_data = &(const struct clk_parent_data){
> +				.hw = &gsbi2_uart_src.clkr.hw,
>  			},
>  			.num_parents = 1,
>  			.ops = &clk_branch_ops,
> @@ -464,7 +486,7 @@ static struct clk_rcg gsbi4_uart_src = {
>  		.enable_mask = BIT(11),
>  		.hw.init = &(struct clk_init_data){
>  			.name = "gsbi4_uart_src",
> -			.parent_names = gcc_pxo_pll8,
> +			.parent_data = gcc_pxo_pll8,
>  			.num_parents = 2,
>  			.ops = &clk_rcg_ops,
>  			.flags = CLK_SET_PARENT_GATE,
> @@ -480,8 +502,8 @@ static struct clk_branch gsbi4_uart_clk = {
>  		.enable_mask = BIT(9),
>  		.hw.init = &(struct clk_init_data){
>  			.name = "gsbi4_uart_clk",
> -			.parent_names = (const char *[]){
> -				"gsbi4_uart_src",
> +			.parent_data = &(const struct clk_parent_data){
> +				.hw = &gsbi4_uart_src.clkr.hw,
>  			},
>  			.num_parents = 1,
>  			.ops = &clk_branch_ops,
> @@ -515,7 +537,7 @@ static struct clk_rcg gsbi5_uart_src = {
>  		.enable_mask = BIT(11),
>  		.hw.init = &(struct clk_init_data){
>  			.name = "gsbi5_uart_src",
> -			.parent_names = gcc_pxo_pll8,
> +			.parent_data = gcc_pxo_pll8,
>  			.num_parents = 2,
>  			.ops = &clk_rcg_ops,
>  			.flags = CLK_SET_PARENT_GATE,
> @@ -531,8 +553,8 @@ static struct clk_branch gsbi5_uart_clk = {
>  		.enable_mask = BIT(9),
>  		.hw.init = &(struct clk_init_data){
>  			.name = "gsbi5_uart_clk",
> -			.parent_names = (const char *[]){
> -				"gsbi5_uart_src",
> +			.parent_data = &(const struct clk_parent_data){
> +				.hw = &gsbi5_uart_src.clkr.hw,
>  			},
>  			.num_parents = 1,
>  			.ops = &clk_branch_ops,
> @@ -566,7 +588,7 @@ static struct clk_rcg gsbi6_uart_src = {
>  		.enable_mask = BIT(11),
>  		.hw.init = &(struct clk_init_data){
>  			.name = "gsbi6_uart_src",
> -			.parent_names = gcc_pxo_pll8,
> +			.parent_data = gcc_pxo_pll8,
>  			.num_parents = 2,
>  			.ops = &clk_rcg_ops,
>  			.flags = CLK_SET_PARENT_GATE,
> @@ -582,8 +604,8 @@ static struct clk_branch gsbi6_uart_clk = {
>  		.enable_mask = BIT(9),
>  		.hw.init = &(struct clk_init_data){
>  			.name = "gsbi6_uart_clk",
> -			.parent_names = (const char *[]){
> -				"gsbi6_uart_src",
> +			.parent_data = &(const struct clk_parent_data){
> +				.hw = &gsbi6_uart_src.clkr.hw,
>  			},
>  			.num_parents = 1,
>  			.ops = &clk_branch_ops,
> @@ -617,7 +639,7 @@ static struct clk_rcg gsbi7_uart_src = {
>  		.enable_mask = BIT(11),
>  		.hw.init = &(struct clk_init_data){
>  			.name = "gsbi7_uart_src",
> -			.parent_names = gcc_pxo_pll8,
> +			.parent_data = gcc_pxo_pll8,
>  			.num_parents = 2,
>  			.ops = &clk_rcg_ops,
>  			.flags = CLK_SET_PARENT_GATE,
> @@ -633,8 +655,8 @@ static struct clk_branch gsbi7_uart_clk = {
>  		.enable_mask = BIT(9),
>  		.hw.init = &(struct clk_init_data){
>  			.name = "gsbi7_uart_clk",
> -			.parent_names = (const char *[]){
> -				"gsbi7_uart_src",
> +			.parent_data = &(const struct clk_parent_data){
> +				.hw = &gsbi7_uart_src.clkr.hw,
>  			},
>  			.num_parents = 1,
>  			.ops = &clk_branch_ops,
> @@ -681,7 +703,7 @@ static struct clk_rcg gsbi1_qup_src = {
>  		.enable_mask = BIT(11),
>  		.hw.init = &(struct clk_init_data){
>  			.name = "gsbi1_qup_src",
> -			.parent_names = gcc_pxo_pll8,
> +			.parent_data = gcc_pxo_pll8,
>  			.num_parents = 2,
>  			.ops = &clk_rcg_ops,
>  			.flags = CLK_SET_PARENT_GATE,
> @@ -697,7 +719,9 @@ static struct clk_branch gsbi1_qup_clk = {
>  		.enable_mask = BIT(9),
>  		.hw.init = &(struct clk_init_data){
>  			.name = "gsbi1_qup_clk",
> -			.parent_names = (const char *[]){ "gsbi1_qup_src" },
> +			.parent_data = &(const struct clk_parent_data){
> +				.hw = &gsbi1_qup_src.clkr.hw,
> +			},
>  			.num_parents = 1,
>  			.ops = &clk_branch_ops,
>  			.flags = CLK_SET_RATE_PARENT,
> @@ -730,7 +754,7 @@ static struct clk_rcg gsbi2_qup_src = {
>  		.enable_mask = BIT(11),
>  		.hw.init = &(struct clk_init_data){
>  			.name = "gsbi2_qup_src",
> -			.parent_names = gcc_pxo_pll8,
> +			.parent_data = gcc_pxo_pll8,
>  			.num_parents = 2,
>  			.ops = &clk_rcg_ops,
>  			.flags = CLK_SET_PARENT_GATE,
> @@ -746,7 +770,9 @@ static struct clk_branch gsbi2_qup_clk = {
>  		.enable_mask = BIT(9),
>  		.hw.init = &(struct clk_init_data){
>  			.name = "gsbi2_qup_clk",
> -			.parent_names = (const char *[]){ "gsbi2_qup_src" },
> +			.parent_data = &(const struct clk_parent_data){
> +				.hw = &gsbi2_qup_src.clkr.hw,
> +			},
>  			.num_parents = 1,
>  			.ops = &clk_branch_ops,
>  			.flags = CLK_SET_RATE_PARENT,
> @@ -779,7 +805,7 @@ static struct clk_rcg gsbi4_qup_src = {
>  		.enable_mask = BIT(11),
>  		.hw.init = &(struct clk_init_data){
>  			.name = "gsbi4_qup_src",
> -			.parent_names = gcc_pxo_pll8,
> +			.parent_data = gcc_pxo_pll8,
>  			.num_parents = 2,
>  			.ops = &clk_rcg_ops,
>  			.flags = CLK_SET_PARENT_GATE,
> @@ -795,7 +821,9 @@ static struct clk_branch gsbi4_qup_clk = {
>  		.enable_mask = BIT(9),
>  		.hw.init = &(struct clk_init_data){
>  			.name = "gsbi4_qup_clk",
> -			.parent_names = (const char *[]){ "gsbi4_qup_src" },
> +			.parent_data = &(const struct clk_parent_data){
> +				.hw = &gsbi4_qup_src.clkr.hw,
> +			},
>  			.num_parents = 1,
>  			.ops = &clk_branch_ops,
>  			.flags = CLK_SET_RATE_PARENT,
> @@ -828,7 +856,7 @@ static struct clk_rcg gsbi5_qup_src = {
>  		.enable_mask = BIT(11),
>  		.hw.init = &(struct clk_init_data){
>  			.name = "gsbi5_qup_src",
> -			.parent_names = gcc_pxo_pll8,
> +			.parent_data = gcc_pxo_pll8,
>  			.num_parents = 2,
>  			.ops = &clk_rcg_ops,
>  			.flags = CLK_SET_PARENT_GATE,
> @@ -844,7 +872,9 @@ static struct clk_branch gsbi5_qup_clk = {
>  		.enable_mask = BIT(9),
>  		.hw.init = &(struct clk_init_data){
>  			.name = "gsbi5_qup_clk",
> -			.parent_names = (const char *[]){ "gsbi5_qup_src" },
> +			.parent_data = &(const struct clk_parent_data){
> +				.hw = &gsbi5_qup_src.clkr.hw,
> +			},
>  			.num_parents = 1,
>  			.ops = &clk_branch_ops,
>  			.flags = CLK_SET_RATE_PARENT,
> @@ -877,7 +907,7 @@ static struct clk_rcg gsbi6_qup_src = {
>  		.enable_mask = BIT(11),
>  		.hw.init = &(struct clk_init_data){
>  			.name = "gsbi6_qup_src",
> -			.parent_names = gcc_pxo_pll8,
> +			.parent_data = gcc_pxo_pll8,
>  			.num_parents = 2,
>  			.ops = &clk_rcg_ops,
>  			.flags = CLK_SET_PARENT_GATE,
> @@ -893,7 +923,9 @@ static struct clk_branch gsbi6_qup_clk = {
>  		.enable_mask = BIT(9),
>  		.hw.init = &(struct clk_init_data){
>  			.name = "gsbi6_qup_clk",
> -			.parent_names = (const char *[]){ "gsbi6_qup_src" },
> +			.parent_data = &(const struct clk_parent_data){
> +				.hw = &gsbi6_qup_src.clkr.hw,
> +			},
>  			.num_parents = 1,
>  			.ops = &clk_branch_ops,
>  			.flags = CLK_SET_RATE_PARENT,
> @@ -926,7 +958,7 @@ static struct clk_rcg gsbi7_qup_src = {
>  		.enable_mask = BIT(11),
>  		.hw.init = &(struct clk_init_data){
>  			.name = "gsbi7_qup_src",
> -			.parent_names = gcc_pxo_pll8,
> +			.parent_data = gcc_pxo_pll8,
>  			.num_parents = 2,
>  			.ops = &clk_rcg_ops,
>  			.flags = CLK_SET_PARENT_GATE,
> @@ -942,7 +974,9 @@ static struct clk_branch gsbi7_qup_clk = {
>  		.enable_mask = BIT(9),
>  		.hw.init = &(struct clk_init_data){
>  			.name = "gsbi7_qup_clk",
> -			.parent_names = (const char *[]){ "gsbi7_qup_src" },
> +			.parent_data = &(const struct clk_parent_data){
> +				.hw = &gsbi7_qup_src.clkr.hw,
> +			},
>  			.num_parents = 1,
>  			.ops = &clk_branch_ops,
>  			.flags = CLK_SET_RATE_PARENT,
> @@ -1076,7 +1110,7 @@ static struct clk_rcg gp0_src = {
>  		.enable_mask = BIT(11),
>  		.hw.init = &(struct clk_init_data){
>  			.name = "gp0_src",
> -			.parent_names = gcc_pxo_pll8_cxo,
> +			.parent_data = gcc_pxo_pll8_cxo,
>  			.num_parents = 3,
>  			.ops = &clk_rcg_ops,
>  			.flags = CLK_SET_PARENT_GATE,
> @@ -1092,7 +1126,9 @@ static struct clk_branch gp0_clk = {
>  		.enable_mask = BIT(9),
>  		.hw.init = &(struct clk_init_data){
>  			.name = "gp0_clk",
> -			.parent_names = (const char *[]){ "gp0_src" },
> +			.parent_data = &(const struct clk_parent_data){
> +				.hw = &gp0_src.clkr.hw,
> +			},
>  			.num_parents = 1,
>  			.ops = &clk_branch_ops,
>  			.flags = CLK_SET_RATE_PARENT,
> @@ -1125,7 +1161,7 @@ static struct clk_rcg gp1_src = {
>  		.enable_mask = BIT(11),
>  		.hw.init = &(struct clk_init_data){
>  			.name = "gp1_src",
> -			.parent_names = gcc_pxo_pll8_cxo,
> +			.parent_data = gcc_pxo_pll8_cxo,
>  			.num_parents = 3,
>  			.ops = &clk_rcg_ops,
>  			.flags = CLK_SET_RATE_GATE,
> @@ -1141,7 +1177,9 @@ static struct clk_branch gp1_clk = {
>  		.enable_mask = BIT(9),
>  		.hw.init = &(struct clk_init_data){
>  			.name = "gp1_clk",
> -			.parent_names = (const char *[]){ "gp1_src" },
> +			.parent_data = &(const struct clk_parent_data){
> +				.hw = &gp1_src.clkr.hw,
> +			},
>  			.num_parents = 1,
>  			.ops = &clk_branch_ops,
>  			.flags = CLK_SET_RATE_PARENT,
> @@ -1174,7 +1212,7 @@ static struct clk_rcg gp2_src = {
>  		.enable_mask = BIT(11),
>  		.hw.init = &(struct clk_init_data){
>  			.name = "gp2_src",
> -			.parent_names = gcc_pxo_pll8_cxo,
> +			.parent_data = gcc_pxo_pll8_cxo,
>  			.num_parents = 3,
>  			.ops = &clk_rcg_ops,
>  			.flags = CLK_SET_RATE_GATE,
> @@ -1190,7 +1228,9 @@ static struct clk_branch gp2_clk = {
>  		.enable_mask = BIT(9),
>  		.hw.init = &(struct clk_init_data){
>  			.name = "gp2_clk",
> -			.parent_names = (const char *[]){ "gp2_src" },
> +			.parent_data = &(const struct clk_parent_data){
> +				.hw = &gp2_src.clkr.hw,
> +			},
>  			.num_parents = 1,
>  			.ops = &clk_branch_ops,
>  			.flags = CLK_SET_RATE_PARENT,
> @@ -1228,7 +1268,7 @@ static struct clk_rcg prng_src = {
>  		.enable_mask = BIT(11),
>  		.hw.init = &(struct clk_init_data){
>  			.name = "prng_src",
> -			.parent_names = gcc_pxo_pll8,
> +			.parent_data = gcc_pxo_pll8,
>  			.num_parents = 2,
>  			.ops = &clk_rcg_ops,
>  		},
> @@ -1244,7 +1284,9 @@ static struct clk_branch prng_clk = {
>  		.enable_mask = BIT(10),
>  		.hw.init = &(struct clk_init_data){
>  			.name = "prng_clk",
> -			.parent_names = (const char *[]){ "prng_src" },
> +			.parent_data = &(const struct clk_parent_data){
> +				.hw = &prng_src.clkr.hw,
> +			},
>  			.num_parents = 1,
>  			.ops = &clk_branch_ops,
>  		},
> @@ -1290,7 +1332,7 @@ static struct clk_rcg sdc1_src = {
>  		.enable_mask = BIT(11),
>  		.hw.init = &(struct clk_init_data){
>  			.name = "sdc1_src",
> -			.parent_names = gcc_pxo_pll8,
> +			.parent_data = gcc_pxo_pll8,
>  			.num_parents = 2,
>  			.ops = &clk_rcg_ops,
>  		},
> @@ -1305,7 +1347,9 @@ static struct clk_branch sdc1_clk = {
>  		.enable_mask = BIT(9),
>  		.hw.init = &(struct clk_init_data){
>  			.name = "sdc1_clk",
> -			.parent_names = (const char *[]){ "sdc1_src" },
> +			.parent_data = &(const struct clk_parent_data){
> +				.hw = &sdc1_src.clkr.hw,
> +			},
>  			.num_parents = 1,
>  			.ops = &clk_branch_ops,
>  			.flags = CLK_SET_RATE_PARENT,
> @@ -1338,7 +1382,7 @@ static struct clk_rcg sdc3_src = {
>  		.enable_mask = BIT(11),
>  		.hw.init = &(struct clk_init_data){
>  			.name = "sdc3_src",
> -			.parent_names = gcc_pxo_pll8,
> +			.parent_data = gcc_pxo_pll8,
>  			.num_parents = 2,
>  			.ops = &clk_rcg_ops,
>  		},
> @@ -1353,7 +1397,9 @@ static struct clk_branch sdc3_clk = {
>  		.enable_mask = BIT(9),
>  		.hw.init = &(struct clk_init_data){
>  			.name = "sdc3_clk",
> -			.parent_names = (const char *[]){ "sdc3_src" },
> +			.parent_data = &(const struct clk_parent_data){
> +				.hw = &sdc3_src.clkr.hw,
> +			},
>  			.num_parents = 1,
>  			.ops = &clk_branch_ops,
>  			.flags = CLK_SET_RATE_PARENT,
> @@ -1421,7 +1467,7 @@ static struct clk_rcg tsif_ref_src = {
>  		.enable_mask = BIT(11),
>  		.hw.init = &(struct clk_init_data){
>  			.name = "tsif_ref_src",
> -			.parent_names = gcc_pxo_pll8,
> +			.parent_data = gcc_pxo_pll8,
>  			.num_parents = 2,
>  			.ops = &clk_rcg_ops,
>  		},
> @@ -1436,7 +1482,9 @@ static struct clk_branch tsif_ref_clk = {
>  		.enable_mask = BIT(9),
>  		.hw.init = &(struct clk_init_data){
>  			.name = "tsif_ref_clk",
> -			.parent_names = (const char *[]){ "tsif_ref_src" },
> +			.parent_data = &(const struct clk_parent_data){
> +				.hw = &tsif_ref_src.clkr.hw,
> +			},
>  			.num_parents = 1,
>  			.ops = &clk_branch_ops,
>  			.flags = CLK_SET_RATE_PARENT,
> @@ -1583,7 +1631,7 @@ static struct clk_rcg pcie_ref_src = {
>  		.enable_mask = BIT(11),
>  		.hw.init = &(struct clk_init_data){
>  			.name = "pcie_ref_src",
> -			.parent_names = gcc_pxo_pll3,
> +			.parent_data = gcc_pxo_pll3,
>  			.num_parents = 2,
>  			.ops = &clk_rcg_ops,
>  			.flags = CLK_SET_RATE_GATE,
> @@ -1599,7 +1647,9 @@ static struct clk_branch pcie_ref_src_clk = {
>  		.enable_mask = BIT(9),
>  		.hw.init = &(struct clk_init_data){
>  			.name = "pcie_ref_src_clk",
> -			.parent_names = (const char *[]){ "pcie_ref_src" },
> +			.parent_data = &(const struct clk_parent_data){
> +				.hw = &pcie_ref_src.clkr.hw,
> +			},
>  			.num_parents = 1,
>  			.ops = &clk_branch_ops,
>  			.flags = CLK_SET_RATE_PARENT,
> @@ -1675,7 +1725,7 @@ static struct clk_rcg pcie1_ref_src = {
>  		.enable_mask = BIT(11),
>  		.hw.init = &(struct clk_init_data){
>  			.name = "pcie1_ref_src",
> -			.parent_names = gcc_pxo_pll3,
> +			.parent_data = gcc_pxo_pll3,
>  			.num_parents = 2,
>  			.ops = &clk_rcg_ops,
>  			.flags = CLK_SET_RATE_GATE,
> @@ -1691,7 +1741,9 @@ static struct clk_branch pcie1_ref_src_clk = {
>  		.enable_mask = BIT(9),
>  		.hw.init = &(struct clk_init_data){
>  			.name = "pcie1_ref_src_clk",
> -			.parent_names = (const char *[]){ "pcie1_ref_src" },
> +			.parent_data = &(const struct clk_parent_data){
> +				.hw = &pcie1_ref_src.clkr.hw,
> +			},
>  			.num_parents = 1,
>  			.ops = &clk_branch_ops,
>  			.flags = CLK_SET_RATE_PARENT,
> @@ -1767,7 +1819,7 @@ static struct clk_rcg pcie2_ref_src = {
>  		.enable_mask = BIT(11),
>  		.hw.init = &(struct clk_init_data){
>  			.name = "pcie2_ref_src",
> -			.parent_names = gcc_pxo_pll3,
> +			.parent_data = gcc_pxo_pll3,
>  			.num_parents = 2,
>  			.ops = &clk_rcg_ops,
>  			.flags = CLK_SET_RATE_GATE,
> @@ -1783,7 +1835,9 @@ static struct clk_branch pcie2_ref_src_clk = {
>  		.enable_mask = BIT(9),
>  		.hw.init = &(struct clk_init_data){
>  			.name = "pcie2_ref_src_clk",
> -			.parent_names = (const char *[]){ "pcie2_ref_src" },
> +			.parent_data = &(const struct clk_parent_data){
> +				.hw = &pcie2_ref_src.clkr.hw,
> +			},
>  			.num_parents = 1,
>  			.ops = &clk_branch_ops,
>  			.flags = CLK_SET_RATE_PARENT,
> @@ -1864,7 +1918,7 @@ static struct clk_rcg sata_ref_src = {
>  		.enable_mask = BIT(7),
>  		.hw.init = &(struct clk_init_data){
>  			.name = "sata_ref_src",
> -			.parent_names = gcc_pxo_pll3,
> +			.parent_data = gcc_pxo_pll3,
>  			.num_parents = 2,
>  			.ops = &clk_rcg_ops,
>  			.flags = CLK_SET_RATE_GATE,
> @@ -1880,7 +1934,9 @@ static struct clk_branch sata_rxoob_clk = {
>  		.enable_mask = BIT(4),
>  		.hw.init = &(struct clk_init_data){
>  			.name = "sata_rxoob_clk",
> -			.parent_names = (const char *[]){ "sata_ref_src" },
> +			.parent_data = &(const struct clk_parent_data){
> +				.hw = &sata_ref_src.clkr.hw,
> +			},
>  			.num_parents = 1,
>  			.ops = &clk_branch_ops,
>  			.flags = CLK_SET_RATE_PARENT,
> @@ -1896,7 +1952,9 @@ static struct clk_branch sata_pmalive_clk = {
>  		.enable_mask = BIT(4),
>  		.hw.init = &(struct clk_init_data){
>  			.name = "sata_pmalive_clk",
> -			.parent_names = (const char *[]){ "sata_ref_src" },
> +			.parent_data = &(const struct clk_parent_data){
> +				.hw = &sata_ref_src.clkr.hw,
> +			},
>  			.num_parents = 1,
>  			.ops = &clk_branch_ops,
>  			.flags = CLK_SET_RATE_PARENT,
> @@ -1912,7 +1970,9 @@ static struct clk_branch sata_phy_ref_clk = {
>  		.enable_mask = BIT(4),
>  		.hw.init = &(struct clk_init_data){
>  			.name = "sata_phy_ref_clk",
> -			.parent_names = (const char *[]){ "pxo" },
> +			.parent_data = &(const struct clk_parent_data){
> +				.fw_name = "pxo",
> +			},
>  			.num_parents = 1,
>  			.ops = &clk_branch_ops,
>  		},
> @@ -2001,7 +2061,7 @@ static struct clk_rcg usb30_master_clk_src = {
>  		.enable_mask = BIT(11),
>  		.hw.init = &(struct clk_init_data){
>  			.name = "usb30_master_ref_src",
> -			.parent_names = gcc_pxo_pll8_pll0,
> +			.parent_data = gcc_pxo_pll8_pll0,
>  			.num_parents = 3,
>  			.ops = &clk_rcg_ops,
>  			.flags = CLK_SET_RATE_GATE,
> @@ -2017,7 +2077,9 @@ static struct clk_branch usb30_0_branch_clk = {
>  		.enable_mask = BIT(4),
>  		.hw.init = &(struct clk_init_data){
>  			.name = "usb30_0_branch_clk",
> -			.parent_names = (const char *[]){ "usb30_master_ref_src", },
> +			.parent_data = &(const struct clk_parent_data){
> +				.hw = &usb30_master_clk_src.clkr.hw,
> +			},
>  			.num_parents = 1,
>  			.ops = &clk_branch_ops,
>  			.flags = CLK_SET_RATE_PARENT,
> @@ -2033,7 +2095,9 @@ static struct clk_branch usb30_1_branch_clk = {
>  		.enable_mask = BIT(4),
>  		.hw.init = &(struct clk_init_data){
>  			.name = "usb30_1_branch_clk",
> -			.parent_names = (const char *[]){ "usb30_master_ref_src", },
> +			.parent_data = &(const struct clk_parent_data){
> +				.hw = &usb30_master_clk_src.clkr.hw,
> +			},
>  			.num_parents = 1,
>  			.ops = &clk_branch_ops,
>  			.flags = CLK_SET_RATE_PARENT,
> @@ -2071,7 +2135,7 @@ static struct clk_rcg usb30_utmi_clk = {
>  		.enable_mask = BIT(11),
>  		.hw.init = &(struct clk_init_data){
>  			.name = "usb30_utmi_clk",
> -			.parent_names = gcc_pxo_pll8_pll0,
> +			.parent_data = gcc_pxo_pll8_pll0,
>  			.num_parents = 3,
>  			.ops = &clk_rcg_ops,
>  			.flags = CLK_SET_RATE_GATE,
> @@ -2087,7 +2151,9 @@ static struct clk_branch usb30_0_utmi_clk_ctl = {
>  		.enable_mask = BIT(4),
>  		.hw.init = &(struct clk_init_data){
>  			.name = "usb30_0_utmi_clk_ctl",
> -			.parent_names = (const char *[]){ "usb30_utmi_clk", },
> +			.parent_data = &(const struct clk_parent_data){
> +				.hw = &usb30_utmi_clk.clkr.hw,
> +			},
>  			.num_parents = 1,
>  			.ops = &clk_branch_ops,
>  			.flags = CLK_SET_RATE_PARENT,
> @@ -2103,7 +2169,9 @@ static struct clk_branch usb30_1_utmi_clk_ctl = {
>  		.enable_mask = BIT(4),
>  		.hw.init = &(struct clk_init_data){
>  			.name = "usb30_1_utmi_clk_ctl",
> -			.parent_names = (const char *[]){ "usb30_utmi_clk", },
> +			.parent_data = &(const struct clk_parent_data){
> +				.hw = &usb30_utmi_clk.clkr.hw,
> +			},
>  			.num_parents = 1,
>  			.ops = &clk_branch_ops,
>  			.flags = CLK_SET_RATE_PARENT,
> @@ -2141,7 +2209,7 @@ static struct clk_rcg usb_hs1_xcvr_clk_src = {
>  		.enable_mask = BIT(11),
>  		.hw.init = &(struct clk_init_data){
>  			.name = "usb_hs1_xcvr_src",
> -			.parent_names = gcc_pxo_pll8_pll0,
> +			.parent_data = gcc_pxo_pll8_pll0,
>  			.num_parents = 3,
>  			.ops = &clk_rcg_ops,
>  			.flags = CLK_SET_RATE_GATE,
> @@ -2157,7 +2225,9 @@ static struct clk_branch usb_hs1_xcvr_clk = {
>  		.enable_mask = BIT(9),
>  		.hw.init = &(struct clk_init_data){
>  			.name = "usb_hs1_xcvr_clk",
> -			.parent_names = (const char *[]){ "usb_hs1_xcvr_src" },
> +			.parent_data = &(const struct clk_parent_data){
> +				.hw = &usb_hs1_xcvr_clk_src.clkr.hw,
> +			},
>  			.num_parents = 1,
>  			.ops = &clk_branch_ops,
>  			.flags = CLK_SET_RATE_PARENT,
> @@ -2205,7 +2275,7 @@ static struct clk_rcg usb_fs1_xcvr_clk_src = {
>  		.enable_mask = BIT(11),
>  		.hw.init = &(struct clk_init_data){
>  			.name = "usb_fs1_xcvr_src",
> -			.parent_names = gcc_pxo_pll8_pll0,
> +			.parent_data = gcc_pxo_pll8_pll0,
>  			.num_parents = 3,
>  			.ops = &clk_rcg_ops,
>  			.flags = CLK_SET_RATE_GATE,
> @@ -2221,7 +2291,9 @@ static struct clk_branch usb_fs1_xcvr_clk = {
>  		.enable_mask = BIT(9),
>  		.hw.init = &(struct clk_init_data){
>  			.name = "usb_fs1_xcvr_clk",
> -			.parent_names = (const char *[]){ "usb_fs1_xcvr_src", },
> +			.parent_data = &(const struct clk_parent_data){
> +				.hw = &usb_fs1_xcvr_clk_src.clkr.hw,
> +			},
>  			.num_parents = 1,
>  			.ops = &clk_branch_ops,
>  			.flags = CLK_SET_RATE_PARENT,
> @@ -2237,7 +2309,9 @@ static struct clk_branch usb_fs1_sys_clk = {
>  		.enable_mask = BIT(4),
>  		.hw.init = &(struct clk_init_data){
>  			.name = "usb_fs1_sys_clk",
> -			.parent_names = (const char *[]){ "usb_fs1_xcvr_src", },
> +			.parent_data = &(const struct clk_parent_data){
> +				.hw = &usb_fs1_xcvr_clk_src.clkr.hw,
> +			},
>  			.num_parents = 1,
>  			.ops = &clk_branch_ops,
>  			.flags = CLK_SET_RATE_PARENT,
> @@ -2337,7 +2411,7 @@ static struct clk_dyn_rcg gmac_core1_src = {
>  		.enable_mask = BIT(1),
>  		.hw.init = &(struct clk_init_data){
>  			.name = "gmac_core1_src",
> -			.parent_names = gcc_pxo_pll8_pll14_pll18_pll0,
> +			.parent_data = gcc_pxo_pll8_pll14_pll18_pll0,
>  			.num_parents = 5,
>  			.ops = &clk_dyn_rcg_ops,
>  		},
> @@ -2354,8 +2428,8 @@ static struct clk_branch gmac_core1_clk = {
>  		.enable_mask = BIT(4),
>  		.hw.init = &(struct clk_init_data){
>  			.name = "gmac_core1_clk",
> -			.parent_names = (const char *[]){
> -				"gmac_core1_src",
> +			.parent_data = &(const struct clk_parent_data){
> +				.hw = &gmac_core1_src.clkr.hw,
>  			},
>  			.num_parents = 1,
>  			.ops = &clk_branch_ops,
> @@ -2409,7 +2483,7 @@ static struct clk_dyn_rcg gmac_core2_src = {
>  		.enable_mask = BIT(1),
>  		.hw.init = &(struct clk_init_data){
>  			.name = "gmac_core2_src",
> -			.parent_names = gcc_pxo_pll8_pll14_pll18_pll0,
> +			.parent_data = gcc_pxo_pll8_pll14_pll18_pll0,
>  			.num_parents = 5,
>  			.ops = &clk_dyn_rcg_ops,
>  		},
> @@ -2426,8 +2500,8 @@ static struct clk_branch gmac_core2_clk = {
>  		.enable_mask = BIT(4),
>  		.hw.init = &(struct clk_init_data){
>  			.name = "gmac_core2_clk",
> -			.parent_names = (const char *[]){
> -				"gmac_core2_src",
> +			.parent_data = &(const struct clk_parent_data){
> +				.hw = &gmac_core2_src.clkr.hw,
>  			},
>  			.num_parents = 1,
>  			.ops = &clk_branch_ops,
> @@ -2481,7 +2555,7 @@ static struct clk_dyn_rcg gmac_core3_src = {
>  		.enable_mask = BIT(1),
>  		.hw.init = &(struct clk_init_data){
>  			.name = "gmac_core3_src",
> -			.parent_names = gcc_pxo_pll8_pll14_pll18_pll0,
> +			.parent_data = gcc_pxo_pll8_pll14_pll18_pll0,
>  			.num_parents = 5,
>  			.ops = &clk_dyn_rcg_ops,
>  		},
> @@ -2498,8 +2572,8 @@ static struct clk_branch gmac_core3_clk = {
>  		.enable_mask = BIT(4),
>  		.hw.init = &(struct clk_init_data){
>  			.name = "gmac_core3_clk",
> -			.parent_names = (const char *[]){
> -				"gmac_core3_src",
> +			.parent_data = &(const struct clk_parent_data){
> +				.hw = &gmac_core3_src.clkr.hw,
>  			},
>  			.num_parents = 1,
>  			.ops = &clk_branch_ops,
> @@ -2553,7 +2627,7 @@ static struct clk_dyn_rcg gmac_core4_src = {
>  		.enable_mask = BIT(1),
>  		.hw.init = &(struct clk_init_data){
>  			.name = "gmac_core4_src",
> -			.parent_names = gcc_pxo_pll8_pll14_pll18_pll0,
> +			.parent_data = gcc_pxo_pll8_pll14_pll18_pll0,
>  			.num_parents = 5,
>  			.ops = &clk_dyn_rcg_ops,
>  		},
> @@ -2570,8 +2644,8 @@ static struct clk_branch gmac_core4_clk = {
>  		.enable_mask = BIT(4),
>  		.hw.init = &(struct clk_init_data){
>  			.name = "gmac_core4_clk",
> -			.parent_names = (const char *[]){
> -				"gmac_core4_src",
> +			.parent_data = &(const struct clk_parent_data){
> +				.hw = &gmac_core4_src.clkr.hw,
>  			},
>  			.num_parents = 1,
>  			.ops = &clk_branch_ops,
> @@ -2613,7 +2687,7 @@ static struct clk_dyn_rcg nss_tcm_src = {
>  		.enable_mask = BIT(1),
>  		.hw.init = &(struct clk_init_data){
>  			.name = "nss_tcm_src",
> -			.parent_names = gcc_pxo_pll8_pll14_pll18_pll0,
> +			.parent_data = gcc_pxo_pll8_pll14_pll18_pll0,
>  			.num_parents = 5,
>  			.ops = &clk_dyn_rcg_ops,
>  		},
> @@ -2628,8 +2702,8 @@ static struct clk_branch nss_tcm_clk = {
>  		.enable_mask = BIT(6) | BIT(4),
>  		.hw.init = &(struct clk_init_data){
>  			.name = "nss_tcm_clk",
> -			.parent_names = (const char *[]){
> -				"nss_tcm_src",
> +			.parent_data = &(const struct clk_parent_data){
> +				.hw = &nss_tcm_src.clkr.hw,
>  			},
>  			.num_parents = 1,
>  			.ops = &clk_branch_ops,
> @@ -2691,7 +2765,7 @@ static struct clk_dyn_rcg ubi32_core1_src_clk = {
>  		.enable_mask = BIT(1),
>  		.hw.init = &(struct clk_init_data){
>  			.name = "ubi32_core1_src_clk",
> -			.parent_names = gcc_pxo_pll8_pll14_pll18_pll0,
> +			.parent_data = gcc_pxo_pll8_pll14_pll18_pll0,
>  			.num_parents = 5,
>  			.ops = &clk_dyn_rcg_ops,
>  			.flags = CLK_SET_RATE_PARENT | CLK_GET_RATE_NOCACHE,
> @@ -2744,7 +2818,7 @@ static struct clk_dyn_rcg ubi32_core2_src_clk = {
>  		.enable_mask = BIT(1),
>  		.hw.init = &(struct clk_init_data){
>  			.name = "ubi32_core2_src_clk",
> -			.parent_names = gcc_pxo_pll8_pll14_pll18_pll0,
> +			.parent_data = gcc_pxo_pll8_pll14_pll18_pll0,
>  			.num_parents = 5,
>  			.ops = &clk_dyn_rcg_ops,
>  			.flags = CLK_SET_RATE_PARENT | CLK_GET_RATE_NOCACHE,
> -- 
> 2.33.1
> 

Re: [PATCH 03/14] drivers: clk: qcom: gcc-ipq806x: convert parent_names to parent_data

[Ansuel Smith]

On Tue, Jan 18, 2022 at 07:41:19PM +0100, Marijn Suijten wrote:
> On 2022-01-18 01:44:23, Ansuel Smith wrote:
> > Convert parent_names to parent_data to modernize the driver.
> > 
> > Signed-off-by: Ansuel Smith <ansuelsmth@gmail.com>
> > ---
> >  drivers/clk/qcom/gcc-ipq806x.c | 300 ++++++++++++++++++++-------------
> >  1 file changed, 187 insertions(+), 113 deletions(-)
> > 
> > diff --git a/drivers/clk/qcom/gcc-ipq806x.c b/drivers/clk/qcom/gcc-ipq806x.c
> > index 34cddf461dba..cbacd56f52d4 100644
> > --- a/drivers/clk/qcom/gcc-ipq806x.c
> > +++ b/drivers/clk/qcom/gcc-ipq806x.c
> > @@ -35,7 +35,9 @@ static struct clk_pll pll0 = {
> >  	.status_bit = 16,
> >  	.clkr.hw.init = &(struct clk_init_data){
> >  		.name = "pll0",
> > -		.parent_names = (const char *[]){ "pxo" },
> > +		.parent_data = &(const struct clk_parent_data){
> > +			.fw_name = "pxo",
> > +		},
> >  		.num_parents = 1,
> >  		.ops = &clk_pll_ops,
> >  	},
> > @@ -46,7 +48,9 @@ static struct clk_regmap pll0_vote = {
> >  	.enable_mask = BIT(0),
> >  	.hw.init = &(struct clk_init_data){
> >  		.name = "pll0_vote",
> > -		.parent_names = (const char *[]){ "pll0" },
> > +		.parent_data = &(const struct clk_parent_data){
> > +			.hw = &pll0.clkr.hw,
> 
> Much like the other "gcc modernization" patches referred to in the cover
> letter, this could be converted to parent_hws directly instead of seeing
> an intermediate clk_parent_data + .hw = state.  You can effectively
> squash patch 06 into this and retitle.
> 
> - Marijn
>

The idea was to keep changes well split, following how it was done with
others gcc driver. But ok will make the change directly and squash the 2
patch.

> > +		},
> >  		.num_parents = 1,
> >  		.ops = &clk_pll_vote_ops,
> >  	},
> > @@ -62,7 +66,9 @@ static struct clk_pll pll3 = {
> >  	.status_bit = 16,
> >  	.clkr.hw.init = &(struct clk_init_data){
> >  		.name = "pll3",
> > -		.parent_names = (const char *[]){ "pxo" },
> > +		.parent_data = &(const struct clk_parent_data){
> > +			.fw_name = "pxo",
> > +		},
> >  		.num_parents = 1,
> >  		.ops = &clk_pll_ops,
> >  	},
> > @@ -89,7 +95,9 @@ static struct clk_pll pll8 = {
> >  	.status_bit = 16,
> >  	.clkr.hw.init = &(struct clk_init_data){
> >  		.name = "pll8",
> > -		.parent_names = (const char *[]){ "pxo" },
> > +		.parent_data = &(const struct clk_parent_data){
> > +			.fw_name = "pxo",
> > +		},
> >  		.num_parents = 1,
> >  		.ops = &clk_pll_ops,
> >  	},
> > @@ -100,7 +108,9 @@ static struct clk_regmap pll8_vote = {
> >  	.enable_mask = BIT(8),
> >  	.hw.init = &(struct clk_init_data){
> >  		.name = "pll8_vote",
> > -		.parent_names = (const char *[]){ "pll8" },
> > +		.parent_data = &(const struct clk_parent_data){
> > +			.hw = &pll8.clkr.hw,
> > +		},
> >  		.num_parents = 1,
> >  		.ops = &clk_pll_vote_ops,
> >  	},
> > @@ -123,7 +133,9 @@ static struct hfpll_data hfpll0_data = {
> >  static struct clk_hfpll hfpll0 = {
> >  	.d = &hfpll0_data,
> >  	.clkr.hw.init = &(struct clk_init_data){
> > -		.parent_names = (const char *[]){ "pxo" },
> > +		.parent_data = &(const struct clk_parent_data){
> > +			.fw_name = "pxo",
> > +		},
> >  		.num_parents = 1,
> >  		.name = "hfpll0",
> >  		.ops = &clk_ops_hfpll,
> > @@ -149,7 +161,9 @@ static struct hfpll_data hfpll1_data = {
> >  static struct clk_hfpll hfpll1 = {
> >  	.d = &hfpll1_data,
> >  	.clkr.hw.init = &(struct clk_init_data){
> > -		.parent_names = (const char *[]){ "pxo" },
> > +		.parent_data = &(const struct clk_parent_data){
> > +			.fw_name = "pxo",
> > +		},
> >  		.num_parents = 1,
> >  		.name = "hfpll1",
> >  		.ops = &clk_ops_hfpll,
> > @@ -175,7 +189,9 @@ static struct hfpll_data hfpll_l2_data = {
> >  static struct clk_hfpll hfpll_l2 = {
> >  	.d = &hfpll_l2_data,
> >  	.clkr.hw.init = &(struct clk_init_data){
> > -		.parent_names = (const char *[]){ "pxo" },
> > +		.parent_data = &(const struct clk_parent_data){
> > +			.fw_name = "pxo",
> > +		},
> >  		.num_parents = 1,
> >  		.name = "hfpll_l2",
> >  		.ops = &clk_ops_hfpll,
> > @@ -194,7 +210,9 @@ static struct clk_pll pll14 = {
> >  	.status_bit = 16,
> >  	.clkr.hw.init = &(struct clk_init_data){
> >  		.name = "pll14",
> > -		.parent_names = (const char *[]){ "pxo" },
> > +		.parent_data = &(const struct clk_parent_data){
> > +			.fw_name = "pxo",
> > +		},
> >  		.num_parents = 1,
> >  		.ops = &clk_pll_ops,
> >  	},
> > @@ -205,7 +223,9 @@ static struct clk_regmap pll14_vote = {
> >  	.enable_mask = BIT(14),
> >  	.hw.init = &(struct clk_init_data){
> >  		.name = "pll14_vote",
> > -		.parent_names = (const char *[]){ "pll14" },
> > +		.parent_data = &(const struct clk_parent_data){
> > +			.hw = &pll14.clkr.hw,
> > +		},
> >  		.num_parents = 1,
> >  		.ops = &clk_pll_vote_ops,
> >  	},
> > @@ -238,7 +258,9 @@ static struct clk_pll pll18 = {
> >  	.freq_tbl = pll18_freq_tbl,
> >  	.clkr.hw.init = &(struct clk_init_data){
> >  		.name = "pll18",
> > -		.parent_names = (const char *[]){ "pxo" },
> > +		.parent_data = &(const struct clk_parent_data){
> > +			.fw_name = "pxo",
> > +		},
> >  		.num_parents = 1,
> >  		.ops = &clk_pll_ops,
> >  	},
> > @@ -259,9 +281,9 @@ static const struct parent_map gcc_pxo_pll8_map[] = {
> >  	{ P_PLL8, 3 }
> >  };
> >  
> > -static const char * const gcc_pxo_pll8[] = {
> > -	"pxo",
> > -	"pll8_vote",
> > +static const struct clk_parent_data gcc_pxo_pll8[] = {
> > +	{ .fw_name = "pxo" },
> > +	{ .hw = &pll8_vote.hw },
> >  };
> >  
> >  static const struct parent_map gcc_pxo_pll8_cxo_map[] = {
> > @@ -270,10 +292,10 @@ static const struct parent_map gcc_pxo_pll8_cxo_map[] = {
> >  	{ P_CXO, 5 }
> >  };
> >  
> > -static const char * const gcc_pxo_pll8_cxo[] = {
> > -	"pxo",
> > -	"pll8_vote",
> > -	"cxo",
> > +static const struct clk_parent_data gcc_pxo_pll8_cxo[] = {
> > +	{ .fw_name = "pxo" },
> > +	{ .hw = &pll8_vote.hw },
> > +	{ .fw_name = "cxo" },
> >  };
> >  
> >  static const struct parent_map gcc_pxo_pll3_map[] = {
> > @@ -286,9 +308,9 @@ static const struct parent_map gcc_pxo_pll3_sata_map[] = {
> >  	{ P_PLL3, 6 }
> >  };
> >  
> > -static const char * const gcc_pxo_pll3[] = {
> > -	"pxo",
> > -	"pll3",
> > +static const struct clk_parent_data gcc_pxo_pll3[] = {
> > +	{ .fw_name = "pxo" },
> > +	{ .hw = &pll3.clkr.hw },
> >  };
> >  
> >  static const struct parent_map gcc_pxo_pll8_pll0_map[] = {
> > @@ -297,10 +319,10 @@ static const struct parent_map gcc_pxo_pll8_pll0_map[] = {
> >  	{ P_PLL0, 2 }
> >  };
> >  
> > -static const char * const gcc_pxo_pll8_pll0[] = {
> > -	"pxo",
> > -	"pll8_vote",
> > -	"pll0_vote",
> > +static const struct clk_parent_data gcc_pxo_pll8_pll0[] = {
> > +	{ .fw_name = "pxo" },
> > +	{ .hw = &pll8_vote.hw },
> > +	{ .hw = &pll0_vote.hw },
> >  };
> >  
> >  static const struct parent_map gcc_pxo_pll8_pll14_pll18_pll0_map[] = {
> > @@ -311,12 +333,12 @@ static const struct parent_map gcc_pxo_pll8_pll14_pll18_pll0_map[] = {
> >  	{ P_PLL18, 1 }
> >  };
> >  
> > -static const char * const gcc_pxo_pll8_pll14_pll18_pll0[] = {
> > -	"pxo",
> > -	"pll8_vote",
> > -	"pll0_vote",
> > -	"pll14",
> > -	"pll18",
> > +static const struct clk_parent_data gcc_pxo_pll8_pll14_pll18_pll0[] = {
> > +	{ .fw_name = "pxo" },
> > +	{ .hw = &pll8_vote.hw },
> > +	{ .hw = &pll0_vote.hw },
> > +	{ .hw = &pll14.clkr.hw },
> > +	{ .hw = &pll18.clkr.hw },
> >  };
> >  
> >  static struct freq_tbl clk_tbl_gsbi_uart[] = {
> > @@ -362,7 +384,7 @@ static struct clk_rcg gsbi1_uart_src = {
> >  		.enable_mask = BIT(11),
> >  		.hw.init = &(struct clk_init_data){
> >  			.name = "gsbi1_uart_src",
> > -			.parent_names = gcc_pxo_pll8,
> > +			.parent_data = gcc_pxo_pll8,
> >  			.num_parents = 2,
> >  			.ops = &clk_rcg_ops,
> >  			.flags = CLK_SET_PARENT_GATE,
> > @@ -378,8 +400,8 @@ static struct clk_branch gsbi1_uart_clk = {
> >  		.enable_mask = BIT(9),
> >  		.hw.init = &(struct clk_init_data){
> >  			.name = "gsbi1_uart_clk",
> > -			.parent_names = (const char *[]){
> > -				"gsbi1_uart_src",
> > +			.parent_data = &(const struct clk_parent_data){
> > +				.hw = &gsbi1_uart_src.clkr.hw,
> >  			},
> >  			.num_parents = 1,
> >  			.ops = &clk_branch_ops,
> > @@ -413,7 +435,7 @@ static struct clk_rcg gsbi2_uart_src = {
> >  		.enable_mask = BIT(11),
> >  		.hw.init = &(struct clk_init_data){
> >  			.name = "gsbi2_uart_src",
> > -			.parent_names = gcc_pxo_pll8,
> > +			.parent_data = gcc_pxo_pll8,
> >  			.num_parents = 2,
> >  			.ops = &clk_rcg_ops,
> >  			.flags = CLK_SET_PARENT_GATE,
> > @@ -429,8 +451,8 @@ static struct clk_branch gsbi2_uart_clk = {
> >  		.enable_mask = BIT(9),
> >  		.hw.init = &(struct clk_init_data){
> >  			.name = "gsbi2_uart_clk",
> > -			.parent_names = (const char *[]){
> > -				"gsbi2_uart_src",
> > +			.parent_data = &(const struct clk_parent_data){
> > +				.hw = &gsbi2_uart_src.clkr.hw,
> >  			},
> >  			.num_parents = 1,
> >  			.ops = &clk_branch_ops,
> > @@ -464,7 +486,7 @@ static struct clk_rcg gsbi4_uart_src = {
> >  		.enable_mask = BIT(11),
> >  		.hw.init = &(struct clk_init_data){
> >  			.name = "gsbi4_uart_src",
> > -			.parent_names = gcc_pxo_pll8,
> > +			.parent_data = gcc_pxo_pll8,
> >  			.num_parents = 2,
> >  			.ops = &clk_rcg_ops,
> >  			.flags = CLK_SET_PARENT_GATE,
> > @@ -480,8 +502,8 @@ static struct clk_branch gsbi4_uart_clk = {
> >  		.enable_mask = BIT(9),
> >  		.hw.init = &(struct clk_init_data){
> >  			.name = "gsbi4_uart_clk",
> > -			.parent_names = (const char *[]){
> > -				"gsbi4_uart_src",
> > +			.parent_data = &(const struct clk_parent_data){
> > +				.hw = &gsbi4_uart_src.clkr.hw,
> >  			},
> >  			.num_parents = 1,
> >  			.ops = &clk_branch_ops,
> > @@ -515,7 +537,7 @@ static struct clk_rcg gsbi5_uart_src = {
> >  		.enable_mask = BIT(11),
> >  		.hw.init = &(struct clk_init_data){
> >  			.name = "gsbi5_uart_src",
> > -			.parent_names = gcc_pxo_pll8,
> > +			.parent_data = gcc_pxo_pll8,
> >  			.num_parents = 2,
> >  			.ops = &clk_rcg_ops,
> >  			.flags = CLK_SET_PARENT_GATE,
> > @@ -531,8 +553,8 @@ static struct clk_branch gsbi5_uart_clk = {
> >  		.enable_mask = BIT(9),
> >  		.hw.init = &(struct clk_init_data){
> >  			.name = "gsbi5_uart_clk",
> > -			.parent_names = (const char *[]){
> > -				"gsbi5_uart_src",
> > +			.parent_data = &(const struct clk_parent_data){
> > +				.hw = &gsbi5_uart_src.clkr.hw,
> >  			},
> >  			.num_parents = 1,
> >  			.ops = &clk_branch_ops,
> > @@ -566,7 +588,7 @@ static struct clk_rcg gsbi6_uart_src = {
> >  		.enable_mask = BIT(11),
> >  		.hw.init = &(struct clk_init_data){
> >  			.name = "gsbi6_uart_src",
> > -			.parent_names = gcc_pxo_pll8,
> > +			.parent_data = gcc_pxo_pll8,
> >  			.num_parents = 2,
> >  			.ops = &clk_rcg_ops,
> >  			.flags = CLK_SET_PARENT_GATE,
> > @@ -582,8 +604,8 @@ static struct clk_branch gsbi6_uart_clk = {
> >  		.enable_mask = BIT(9),
> >  		.hw.init = &(struct clk_init_data){
> >  			.name = "gsbi6_uart_clk",
> > -			.parent_names = (const char *[]){
> > -				"gsbi6_uart_src",
> > +			.parent_data = &(const struct clk_parent_data){
> > +				.hw = &gsbi6_uart_src.clkr.hw,
> >  			},
> >  			.num_parents = 1,
> >  			.ops = &clk_branch_ops,
> > @@ -617,7 +639,7 @@ static struct clk_rcg gsbi7_uart_src = {
> >  		.enable_mask = BIT(11),
> >  		.hw.init = &(struct clk_init_data){
> >  			.name = "gsbi7_uart_src",
> > -			.parent_names = gcc_pxo_pll8,
> > +			.parent_data = gcc_pxo_pll8,
> >  			.num_parents = 2,
> >  			.ops = &clk_rcg_ops,
> >  			.flags = CLK_SET_PARENT_GATE,
> > @@ -633,8 +655,8 @@ static struct clk_branch gsbi7_uart_clk = {
> >  		.enable_mask = BIT(9),
> >  		.hw.init = &(struct clk_init_data){
> >  			.name = "gsbi7_uart_clk",
> > -			.parent_names = (const char *[]){
> > -				"gsbi7_uart_src",
> > +			.parent_data = &(const struct clk_parent_data){
> > +				.hw = &gsbi7_uart_src.clkr.hw,
> >  			},
> >  			.num_parents = 1,
> >  			.ops = &clk_branch_ops,
> > @@ -681,7 +703,7 @@ static struct clk_rcg gsbi1_qup_src = {
> >  		.enable_mask = BIT(11),
> >  		.hw.init = &(struct clk_init_data){
> >  			.name = "gsbi1_qup_src",
> > -			.parent_names = gcc_pxo_pll8,
> > +			.parent_data = gcc_pxo_pll8,
> >  			.num_parents = 2,
> >  			.ops = &clk_rcg_ops,
> >  			.flags = CLK_SET_PARENT_GATE,
> > @@ -697,7 +719,9 @@ static struct clk_branch gsbi1_qup_clk = {
> >  		.enable_mask = BIT(9),
> >  		.hw.init = &(struct clk_init_data){
> >  			.name = "gsbi1_qup_clk",
> > -			.parent_names = (const char *[]){ "gsbi1_qup_src" },
> > +			.parent_data = &(const struct clk_parent_data){
> > +				.hw = &gsbi1_qup_src.clkr.hw,
> > +			},
> >  			.num_parents = 1,
> >  			.ops = &clk_branch_ops,
> >  			.flags = CLK_SET_RATE_PARENT,
> > @@ -730,7 +754,7 @@ static struct clk_rcg gsbi2_qup_src = {
> >  		.enable_mask = BIT(11),
> >  		.hw.init = &(struct clk_init_data){
> >  			.name = "gsbi2_qup_src",
> > -			.parent_names = gcc_pxo_pll8,
> > +			.parent_data = gcc_pxo_pll8,
> >  			.num_parents = 2,
> >  			.ops = &clk_rcg_ops,
> >  			.flags = CLK_SET_PARENT_GATE,
> > @@ -746,7 +770,9 @@ static struct clk_branch gsbi2_qup_clk = {
> >  		.enable_mask = BIT(9),
> >  		.hw.init = &(struct clk_init_data){
> >  			.name = "gsbi2_qup_clk",
> > -			.parent_names = (const char *[]){ "gsbi2_qup_src" },
> > +			.parent_data = &(const struct clk_parent_data){
> > +				.hw = &gsbi2_qup_src.clkr.hw,
> > +			},
> >  			.num_parents = 1,
> >  			.ops = &clk_branch_ops,
> >  			.flags = CLK_SET_RATE_PARENT,
> > @@ -779,7 +805,7 @@ static struct clk_rcg gsbi4_qup_src = {
> >  		.enable_mask = BIT(11),
> >  		.hw.init = &(struct clk_init_data){
> >  			.name = "gsbi4_qup_src",
> > -			.parent_names = gcc_pxo_pll8,
> > +			.parent_data = gcc_pxo_pll8,
> >  			.num_parents = 2,
> >  			.ops = &clk_rcg_ops,
> >  			.flags = CLK_SET_PARENT_GATE,
> > @@ -795,7 +821,9 @@ static struct clk_branch gsbi4_qup_clk = {
> >  		.enable_mask = BIT(9),
> >  		.hw.init = &(struct clk_init_data){
> >  			.name = "gsbi4_qup_clk",
> > -			.parent_names = (const char *[]){ "gsbi4_qup_src" },
> > +			.parent_data = &(const struct clk_parent_data){
> > +				.hw = &gsbi4_qup_src.clkr.hw,
> > +			},
> >  			.num_parents = 1,
> >  			.ops = &clk_branch_ops,
> >  			.flags = CLK_SET_RATE_PARENT,
> > @@ -828,7 +856,7 @@ static struct clk_rcg gsbi5_qup_src = {
> >  		.enable_mask = BIT(11),
> >  		.hw.init = &(struct clk_init_data){
> >  			.name = "gsbi5_qup_src",
> > -			.parent_names = gcc_pxo_pll8,
> > +			.parent_data = gcc_pxo_pll8,
> >  			.num_parents = 2,
> >  			.ops = &clk_rcg_ops,
> >  			.flags = CLK_SET_PARENT_GATE,
> > @@ -844,7 +872,9 @@ static struct clk_branch gsbi5_qup_clk = {
> >  		.enable_mask = BIT(9),
> >  		.hw.init = &(struct clk_init_data){
> >  			.name = "gsbi5_qup_clk",
> > -			.parent_names = (const char *[]){ "gsbi5_qup_src" },
> > +			.parent_data = &(const struct clk_parent_data){
> > +				.hw = &gsbi5_qup_src.clkr.hw,
> > +			},
> >  			.num_parents = 1,
> >  			.ops = &clk_branch_ops,
> >  			.flags = CLK_SET_RATE_PARENT,
> > @@ -877,7 +907,7 @@ static struct clk_rcg gsbi6_qup_src = {
> >  		.enable_mask = BIT(11),
> >  		.hw.init = &(struct clk_init_data){
> >  			.name = "gsbi6_qup_src",
> > -			.parent_names = gcc_pxo_pll8,
> > +			.parent_data = gcc_pxo_pll8,
> >  			.num_parents = 2,
> >  			.ops = &clk_rcg_ops,
> >  			.flags = CLK_SET_PARENT_GATE,
> > @@ -893,7 +923,9 @@ static struct clk_branch gsbi6_qup_clk = {
> >  		.enable_mask = BIT(9),
> >  		.hw.init = &(struct clk_init_data){
> >  			.name = "gsbi6_qup_clk",
> > -			.parent_names = (const char *[]){ "gsbi6_qup_src" },
> > +			.parent_data = &(const struct clk_parent_data){
> > +				.hw = &gsbi6_qup_src.clkr.hw,
> > +			},
> >  			.num_parents = 1,
> >  			.ops = &clk_branch_ops,
> >  			.flags = CLK_SET_RATE_PARENT,
> > @@ -926,7 +958,7 @@ static struct clk_rcg gsbi7_qup_src = {
> >  		.enable_mask = BIT(11),
> >  		.hw.init = &(struct clk_init_data){
> >  			.name = "gsbi7_qup_src",
> > -			.parent_names = gcc_pxo_pll8,
> > +			.parent_data = gcc_pxo_pll8,
> >  			.num_parents = 2,
> >  			.ops = &clk_rcg_ops,
> >  			.flags = CLK_SET_PARENT_GATE,
> > @@ -942,7 +974,9 @@ static struct clk_branch gsbi7_qup_clk = {
> >  		.enable_mask = BIT(9),
> >  		.hw.init = &(struct clk_init_data){
> >  			.name = "gsbi7_qup_clk",
> > -			.parent_names = (const char *[]){ "gsbi7_qup_src" },
> > +			.parent_data = &(const struct clk_parent_data){
> > +				.hw = &gsbi7_qup_src.clkr.hw,
> > +			},
> >  			.num_parents = 1,
> >  			.ops = &clk_branch_ops,
> >  			.flags = CLK_SET_RATE_PARENT,
> > @@ -1076,7 +1110,7 @@ static struct clk_rcg gp0_src = {
> >  		.enable_mask = BIT(11),
> >  		.hw.init = &(struct clk_init_data){
> >  			.name = "gp0_src",
> > -			.parent_names = gcc_pxo_pll8_cxo,
> > +			.parent_data = gcc_pxo_pll8_cxo,
> >  			.num_parents = 3,
> >  			.ops = &clk_rcg_ops,
> >  			.flags = CLK_SET_PARENT_GATE,
> > @@ -1092,7 +1126,9 @@ static struct clk_branch gp0_clk = {
> >  		.enable_mask = BIT(9),
> >  		.hw.init = &(struct clk_init_data){
> >  			.name = "gp0_clk",
> > -			.parent_names = (const char *[]){ "gp0_src" },
> > +			.parent_data = &(const struct clk_parent_data){
> > +				.hw = &gp0_src.clkr.hw,
> > +			},
> >  			.num_parents = 1,
> >  			.ops = &clk_branch_ops,
> >  			.flags = CLK_SET_RATE_PARENT,
> > @@ -1125,7 +1161,7 @@ static struct clk_rcg gp1_src = {
> >  		.enable_mask = BIT(11),
> >  		.hw.init = &(struct clk_init_data){
> >  			.name = "gp1_src",
> > -			.parent_names = gcc_pxo_pll8_cxo,
> > +			.parent_data = gcc_pxo_pll8_cxo,
> >  			.num_parents = 3,
> >  			.ops = &clk_rcg_ops,
> >  			.flags = CLK_SET_RATE_GATE,
> > @@ -1141,7 +1177,9 @@ static struct clk_branch gp1_clk = {
> >  		.enable_mask = BIT(9),
> >  		.hw.init = &(struct clk_init_data){
> >  			.name = "gp1_clk",
> > -			.parent_names = (const char *[]){ "gp1_src" },
> > +			.parent_data = &(const struct clk_parent_data){
> > +				.hw = &gp1_src.clkr.hw,
> > +			},
> >  			.num_parents = 1,
> >  			.ops = &clk_branch_ops,
> >  			.flags = CLK_SET_RATE_PARENT,
> > @@ -1174,7 +1212,7 @@ static struct clk_rcg gp2_src = {
> >  		.enable_mask = BIT(11),
> >  		.hw.init = &(struct clk_init_data){
> >  			.name = "gp2_src",
> > -			.parent_names = gcc_pxo_pll8_cxo,
> > +			.parent_data = gcc_pxo_pll8_cxo,
> >  			.num_parents = 3,
> >  			.ops = &clk_rcg_ops,
> >  			.flags = CLK_SET_RATE_GATE,
> > @@ -1190,7 +1228,9 @@ static struct clk_branch gp2_clk = {
> >  		.enable_mask = BIT(9),
> >  		.hw.init = &(struct clk_init_data){
> >  			.name = "gp2_clk",
> > -			.parent_names = (const char *[]){ "gp2_src" },
> > +			.parent_data = &(const struct clk_parent_data){
> > +				.hw = &gp2_src.clkr.hw,
> > +			},
> >  			.num_parents = 1,
> >  			.ops = &clk_branch_ops,
> >  			.flags = CLK_SET_RATE_PARENT,
> > @@ -1228,7 +1268,7 @@ static struct clk_rcg prng_src = {
> >  		.enable_mask = BIT(11),
> >  		.hw.init = &(struct clk_init_data){
> >  			.name = "prng_src",
> > -			.parent_names = gcc_pxo_pll8,
> > +			.parent_data = gcc_pxo_pll8,
> >  			.num_parents = 2,
> >  			.ops = &clk_rcg_ops,
> >  		},
> > @@ -1244,7 +1284,9 @@ static struct clk_branch prng_clk = {
> >  		.enable_mask = BIT(10),
> >  		.hw.init = &(struct clk_init_data){
> >  			.name = "prng_clk",
> > -			.parent_names = (const char *[]){ "prng_src" },
> > +			.parent_data = &(const struct clk_parent_data){
> > +				.hw = &prng_src.clkr.hw,
> > +			},
> >  			.num_parents = 1,
> >  			.ops = &clk_branch_ops,
> >  		},
> > @@ -1290,7 +1332,7 @@ static struct clk_rcg sdc1_src = {
> >  		.enable_mask = BIT(11),
> >  		.hw.init = &(struct clk_init_data){
> >  			.name = "sdc1_src",
> > -			.parent_names = gcc_pxo_pll8,
> > +			.parent_data = gcc_pxo_pll8,
> >  			.num_parents = 2,
> >  			.ops = &clk_rcg_ops,
> >  		},
> > @@ -1305,7 +1347,9 @@ static struct clk_branch sdc1_clk = {
> >  		.enable_mask = BIT(9),
> >  		.hw.init = &(struct clk_init_data){
> >  			.name = "sdc1_clk",
> > -			.parent_names = (const char *[]){ "sdc1_src" },
> > +			.parent_data = &(const struct clk_parent_data){
> > +				.hw = &sdc1_src.clkr.hw,
> > +			},
> >  			.num_parents = 1,
> >  			.ops = &clk_branch_ops,
> >  			.flags = CLK_SET_RATE_PARENT,
> > @@ -1338,7 +1382,7 @@ static struct clk_rcg sdc3_src = {
> >  		.enable_mask = BIT(11),
> >  		.hw.init = &(struct clk_init_data){
> >  			.name = "sdc3_src",
> > -			.parent_names = gcc_pxo_pll8,
> > +			.parent_data = gcc_pxo_pll8,
> >  			.num_parents = 2,
> >  			.ops = &clk_rcg_ops,
> >  		},
> > @@ -1353,7 +1397,9 @@ static struct clk_branch sdc3_clk = {
> >  		.enable_mask = BIT(9),
> >  		.hw.init = &(struct clk_init_data){
> >  			.name = "sdc3_clk",
> > -			.parent_names = (const char *[]){ "sdc3_src" },
> > +			.parent_data = &(const struct clk_parent_data){
> > +				.hw = &sdc3_src.clkr.hw,
> > +			},
> >  			.num_parents = 1,
> >  			.ops = &clk_branch_ops,
> >  			.flags = CLK_SET_RATE_PARENT,
> > @@ -1421,7 +1467,7 @@ static struct clk_rcg tsif_ref_src = {
> >  		.enable_mask = BIT(11),
> >  		.hw.init = &(struct clk_init_data){
> >  			.name = "tsif_ref_src",
> > -			.parent_names = gcc_pxo_pll8,
> > +			.parent_data = gcc_pxo_pll8,
> >  			.num_parents = 2,
> >  			.ops = &clk_rcg_ops,
> >  		},
> > @@ -1436,7 +1482,9 @@ static struct clk_branch tsif_ref_clk = {
> >  		.enable_mask = BIT(9),
> >  		.hw.init = &(struct clk_init_data){
> >  			.name = "tsif_ref_clk",
> > -			.parent_names = (const char *[]){ "tsif_ref_src" },
> > +			.parent_data = &(const struct clk_parent_data){
> > +				.hw = &tsif_ref_src.clkr.hw,
> > +			},
> >  			.num_parents = 1,
> >  			.ops = &clk_branch_ops,
> >  			.flags = CLK_SET_RATE_PARENT,
> > @@ -1583,7 +1631,7 @@ static struct clk_rcg pcie_ref_src = {
> >  		.enable_mask = BIT(11),
> >  		.hw.init = &(struct clk_init_data){
> >  			.name = "pcie_ref_src",
> > -			.parent_names = gcc_pxo_pll3,
> > +			.parent_data = gcc_pxo_pll3,
> >  			.num_parents = 2,
> >  			.ops = &clk_rcg_ops,
> >  			.flags = CLK_SET_RATE_GATE,
> > @@ -1599,7 +1647,9 @@ static struct clk_branch pcie_ref_src_clk = {
> >  		.enable_mask = BIT(9),
> >  		.hw.init = &(struct clk_init_data){
> >  			.name = "pcie_ref_src_clk",
> > -			.parent_names = (const char *[]){ "pcie_ref_src" },
> > +			.parent_data = &(const struct clk_parent_data){
> > +				.hw = &pcie_ref_src.clkr.hw,
> > +			},
> >  			.num_parents = 1,
> >  			.ops = &clk_branch_ops,
> >  			.flags = CLK_SET_RATE_PARENT,
> > @@ -1675,7 +1725,7 @@ static struct clk_rcg pcie1_ref_src = {
> >  		.enable_mask = BIT(11),
> >  		.hw.init = &(struct clk_init_data){
> >  			.name = "pcie1_ref_src",
> > -			.parent_names = gcc_pxo_pll3,
> > +			.parent_data = gcc_pxo_pll3,
> >  			.num_parents = 2,
> >  			.ops = &clk_rcg_ops,
> >  			.flags = CLK_SET_RATE_GATE,
> > @@ -1691,7 +1741,9 @@ static struct clk_branch pcie1_ref_src_clk = {
> >  		.enable_mask = BIT(9),
> >  		.hw.init = &(struct clk_init_data){
> >  			.name = "pcie1_ref_src_clk",
> > -			.parent_names = (const char *[]){ "pcie1_ref_src" },
> > +			.parent_data = &(const struct clk_parent_data){
> > +				.hw = &pcie1_ref_src.clkr.hw,
> > +			},
> >  			.num_parents = 1,
> >  			.ops = &clk_branch_ops,
> >  			.flags = CLK_SET_RATE_PARENT,
> > @@ -1767,7 +1819,7 @@ static struct clk_rcg pcie2_ref_src = {
> >  		.enable_mask = BIT(11),
> >  		.hw.init = &(struct clk_init_data){
> >  			.name = "pcie2_ref_src",
> > -			.parent_names = gcc_pxo_pll3,
> > +			.parent_data = gcc_pxo_pll3,
> >  			.num_parents = 2,
> >  			.ops = &clk_rcg_ops,
> >  			.flags = CLK_SET_RATE_GATE,
> > @@ -1783,7 +1835,9 @@ static struct clk_branch pcie2_ref_src_clk = {
> >  		.enable_mask = BIT(9),
> >  		.hw.init = &(struct clk_init_data){
> >  			.name = "pcie2_ref_src_clk",
> > -			.parent_names = (const char *[]){ "pcie2_ref_src" },
> > +			.parent_data = &(const struct clk_parent_data){
> > +				.hw = &pcie2_ref_src.clkr.hw,
> > +			},
> >  			.num_parents = 1,
> >  			.ops = &clk_branch_ops,
> >  			.flags = CLK_SET_RATE_PARENT,
> > @@ -1864,7 +1918,7 @@ static struct clk_rcg sata_ref_src = {
> >  		.enable_mask = BIT(7),
> >  		.hw.init = &(struct clk_init_data){
> >  			.name = "sata_ref_src",
> > -			.parent_names = gcc_pxo_pll3,
> > +			.parent_data = gcc_pxo_pll3,
> >  			.num_parents = 2,
> >  			.ops = &clk_rcg_ops,
> >  			.flags = CLK_SET_RATE_GATE,
> > @@ -1880,7 +1934,9 @@ static struct clk_branch sata_rxoob_clk = {
> >  		.enable_mask = BIT(4),
> >  		.hw.init = &(struct clk_init_data){
> >  			.name = "sata_rxoob_clk",
> > -			.parent_names = (const char *[]){ "sata_ref_src" },
> > +			.parent_data = &(const struct clk_parent_data){
> > +				.hw = &sata_ref_src.clkr.hw,
> > +			},
> >  			.num_parents = 1,
> >  			.ops = &clk_branch_ops,
> >  			.flags = CLK_SET_RATE_PARENT,
> > @@ -1896,7 +1952,9 @@ static struct clk_branch sata_pmalive_clk = {
> >  		.enable_mask = BIT(4),
> >  		.hw.init = &(struct clk_init_data){
> >  			.name = "sata_pmalive_clk",
> > -			.parent_names = (const char *[]){ "sata_ref_src" },
> > +			.parent_data = &(const struct clk_parent_data){
> > +				.hw = &sata_ref_src.clkr.hw,
> > +			},
> >  			.num_parents = 1,
> >  			.ops = &clk_branch_ops,
> >  			.flags = CLK_SET_RATE_PARENT,
> > @@ -1912,7 +1970,9 @@ static struct clk_branch sata_phy_ref_clk = {
> >  		.enable_mask = BIT(4),
> >  		.hw.init = &(struct clk_init_data){
> >  			.name = "sata_phy_ref_clk",
> > -			.parent_names = (const char *[]){ "pxo" },
> > +			.parent_data = &(const struct clk_parent_data){
> > +				.fw_name = "pxo",
> > +			},
> >  			.num_parents = 1,
> >  			.ops = &clk_branch_ops,
> >  		},
> > @@ -2001,7 +2061,7 @@ static struct clk_rcg usb30_master_clk_src = {
> >  		.enable_mask = BIT(11),
> >  		.hw.init = &(struct clk_init_data){
> >  			.name = "usb30_master_ref_src",
> > -			.parent_names = gcc_pxo_pll8_pll0,
> > +			.parent_data = gcc_pxo_pll8_pll0,
> >  			.num_parents = 3,
> >  			.ops = &clk_rcg_ops,
> >  			.flags = CLK_SET_RATE_GATE,
> > @@ -2017,7 +2077,9 @@ static struct clk_branch usb30_0_branch_clk = {
> >  		.enable_mask = BIT(4),
> >  		.hw.init = &(struct clk_init_data){
> >  			.name = "usb30_0_branch_clk",
> > -			.parent_names = (const char *[]){ "usb30_master_ref_src", },
> > +			.parent_data = &(const struct clk_parent_data){
> > +				.hw = &usb30_master_clk_src.clkr.hw,
> > +			},
> >  			.num_parents = 1,
> >  			.ops = &clk_branch_ops,
> >  			.flags = CLK_SET_RATE_PARENT,
> > @@ -2033,7 +2095,9 @@ static struct clk_branch usb30_1_branch_clk = {
> >  		.enable_mask = BIT(4),
> >  		.hw.init = &(struct clk_init_data){
> >  			.name = "usb30_1_branch_clk",
> > -			.parent_names = (const char *[]){ "usb30_master_ref_src", },
> > +			.parent_data = &(const struct clk_parent_data){
> > +				.hw = &usb30_master_clk_src.clkr.hw,
> > +			},
> >  			.num_parents = 1,
> >  			.ops = &clk_branch_ops,
> >  			.flags = CLK_SET_RATE_PARENT,
> > @@ -2071,7 +2135,7 @@ static struct clk_rcg usb30_utmi_clk = {
> >  		.enable_mask = BIT(11),
> >  		.hw.init = &(struct clk_init_data){
> >  			.name = "usb30_utmi_clk",
> > -			.parent_names = gcc_pxo_pll8_pll0,
> > +			.parent_data = gcc_pxo_pll8_pll0,
> >  			.num_parents = 3,
> >  			.ops = &clk_rcg_ops,
> >  			.flags = CLK_SET_RATE_GATE,
> > @@ -2087,7 +2151,9 @@ static struct clk_branch usb30_0_utmi_clk_ctl = {
> >  		.enable_mask = BIT(4),
> >  		.hw.init = &(struct clk_init_data){
> >  			.name = "usb30_0_utmi_clk_ctl",
> > -			.parent_names = (const char *[]){ "usb30_utmi_clk", },
> > +			.parent_data = &(const struct clk_parent_data){
> > +				.hw = &usb30_utmi_clk.clkr.hw,
> > +			},
> >  			.num_parents = 1,
> >  			.ops = &clk_branch_ops,
> >  			.flags = CLK_SET_RATE_PARENT,
> > @@ -2103,7 +2169,9 @@ static struct clk_branch usb30_1_utmi_clk_ctl = {
> >  		.enable_mask = BIT(4),
> >  		.hw.init = &(struct clk_init_data){
> >  			.name = "usb30_1_utmi_clk_ctl",
> > -			.parent_names = (const char *[]){ "usb30_utmi_clk", },
> > +			.parent_data = &(const struct clk_parent_data){
> > +				.hw = &usb30_utmi_clk.clkr.hw,
> > +			},
> >  			.num_parents = 1,
> >  			.ops = &clk_branch_ops,
> >  			.flags = CLK_SET_RATE_PARENT,
> > @@ -2141,7 +2209,7 @@ static struct clk_rcg usb_hs1_xcvr_clk_src = {
> >  		.enable_mask = BIT(11),
> >  		.hw.init = &(struct clk_init_data){
> >  			.name = "usb_hs1_xcvr_src",
> > -			.parent_names = gcc_pxo_pll8_pll0,
> > +			.parent_data = gcc_pxo_pll8_pll0,
> >  			.num_parents = 3,
> >  			.ops = &clk_rcg_ops,
> >  			.flags = CLK_SET_RATE_GATE,
> > @@ -2157,7 +2225,9 @@ static struct clk_branch usb_hs1_xcvr_clk = {
> >  		.enable_mask = BIT(9),
> >  		.hw.init = &(struct clk_init_data){
> >  			.name = "usb_hs1_xcvr_clk",
> > -			.parent_names = (const char *[]){ "usb_hs1_xcvr_src" },
> > +			.parent_data = &(const struct clk_parent_data){
> > +				.hw = &usb_hs1_xcvr_clk_src.clkr.hw,
> > +			},
> >  			.num_parents = 1,
> >  			.ops = &clk_branch_ops,
> >  			.flags = CLK_SET_RATE_PARENT,
> > @@ -2205,7 +2275,7 @@ static struct clk_rcg usb_fs1_xcvr_clk_src = {
> >  		.enable_mask = BIT(11),
> >  		.hw.init = &(struct clk_init_data){
> >  			.name = "usb_fs1_xcvr_src",
> > -			.parent_names = gcc_pxo_pll8_pll0,
> > +			.parent_data = gcc_pxo_pll8_pll0,
> >  			.num_parents = 3,
> >  			.ops = &clk_rcg_ops,
> >  			.flags = CLK_SET_RATE_GATE,
> > @@ -2221,7 +2291,9 @@ static struct clk_branch usb_fs1_xcvr_clk = {
> >  		.enable_mask = BIT(9),
> >  		.hw.init = &(struct clk_init_data){
> >  			.name = "usb_fs1_xcvr_clk",
> > -			.parent_names = (const char *[]){ "usb_fs1_xcvr_src", },
> > +			.parent_data = &(const struct clk_parent_data){
> > +				.hw = &usb_fs1_xcvr_clk_src.clkr.hw,
> > +			},
> >  			.num_parents = 1,
> >  			.ops = &clk_branch_ops,
> >  			.flags = CLK_SET_RATE_PARENT,
> > @@ -2237,7 +2309,9 @@ static struct clk_branch usb_fs1_sys_clk = {
> >  		.enable_mask = BIT(4),
> >  		.hw.init = &(struct clk_init_data){
> >  			.name = "usb_fs1_sys_clk",
> > -			.parent_names = (const char *[]){ "usb_fs1_xcvr_src", },
> > +			.parent_data = &(const struct clk_parent_data){
> > +				.hw = &usb_fs1_xcvr_clk_src.clkr.hw,
> > +			},
> >  			.num_parents = 1,
> >  			.ops = &clk_branch_ops,
> >  			.flags = CLK_SET_RATE_PARENT,
> > @@ -2337,7 +2411,7 @@ static struct clk_dyn_rcg gmac_core1_src = {
> >  		.enable_mask = BIT(1),
> >  		.hw.init = &(struct clk_init_data){
> >  			.name = "gmac_core1_src",
> > -			.parent_names = gcc_pxo_pll8_pll14_pll18_pll0,
> > +			.parent_data = gcc_pxo_pll8_pll14_pll18_pll0,
> >  			.num_parents = 5,
> >  			.ops = &clk_dyn_rcg_ops,
> >  		},
> > @@ -2354,8 +2428,8 @@ static struct clk_branch gmac_core1_clk = {
> >  		.enable_mask = BIT(4),
> >  		.hw.init = &(struct clk_init_data){
> >  			.name = "gmac_core1_clk",
> > -			.parent_names = (const char *[]){
> > -				"gmac_core1_src",
> > +			.parent_data = &(const struct clk_parent_data){
> > +				.hw = &gmac_core1_src.clkr.hw,
> >  			},
> >  			.num_parents = 1,
> >  			.ops = &clk_branch_ops,
> > @@ -2409,7 +2483,7 @@ static struct clk_dyn_rcg gmac_core2_src = {
> >  		.enable_mask = BIT(1),
> >  		.hw.init = &(struct clk_init_data){
> >  			.name = "gmac_core2_src",
> > -			.parent_names = gcc_pxo_pll8_pll14_pll18_pll0,
> > +			.parent_data = gcc_pxo_pll8_pll14_pll18_pll0,
> >  			.num_parents = 5,
> >  			.ops = &clk_dyn_rcg_ops,
> >  		},
> > @@ -2426,8 +2500,8 @@ static struct clk_branch gmac_core2_clk = {
> >  		.enable_mask = BIT(4),
> >  		.hw.init = &(struct clk_init_data){
> >  			.name = "gmac_core2_clk",
> > -			.parent_names = (const char *[]){
> > -				"gmac_core2_src",
> > +			.parent_data = &(const struct clk_parent_data){
> > +				.hw = &gmac_core2_src.clkr.hw,
> >  			},
> >  			.num_parents = 1,
> >  			.ops = &clk_branch_ops,
> > @@ -2481,7 +2555,7 @@ static struct clk_dyn_rcg gmac_core3_src = {
> >  		.enable_mask = BIT(1),
> >  		.hw.init = &(struct clk_init_data){
> >  			.name = "gmac_core3_src",
> > -			.parent_names = gcc_pxo_pll8_pll14_pll18_pll0,
> > +			.parent_data = gcc_pxo_pll8_pll14_pll18_pll0,
> >  			.num_parents = 5,
> >  			.ops = &clk_dyn_rcg_ops,
> >  		},
> > @@ -2498,8 +2572,8 @@ static struct clk_branch gmac_core3_clk = {
> >  		.enable_mask = BIT(4),
> >  		.hw.init = &(struct clk_init_data){
> >  			.name = "gmac_core3_clk",
> > -			.parent_names = (const char *[]){
> > -				"gmac_core3_src",
> > +			.parent_data = &(const struct clk_parent_data){
> > +				.hw = &gmac_core3_src.clkr.hw,
> >  			},
> >  			.num_parents = 1,
> >  			.ops = &clk_branch_ops,
> > @@ -2553,7 +2627,7 @@ static struct clk_dyn_rcg gmac_core4_src = {
> >  		.enable_mask = BIT(1),
> >  		.hw.init = &(struct clk_init_data){
> >  			.name = "gmac_core4_src",
> > -			.parent_names = gcc_pxo_pll8_pll14_pll18_pll0,
> > +			.parent_data = gcc_pxo_pll8_pll14_pll18_pll0,
> >  			.num_parents = 5,
> >  			.ops = &clk_dyn_rcg_ops,
> >  		},
> > @@ -2570,8 +2644,8 @@ static struct clk_branch gmac_core4_clk = {
> >  		.enable_mask = BIT(4),
> >  		.hw.init = &(struct clk_init_data){
> >  			.name = "gmac_core4_clk",
> > -			.parent_names = (const char *[]){
> > -				"gmac_core4_src",
> > +			.parent_data = &(const struct clk_parent_data){
> > +				.hw = &gmac_core4_src.clkr.hw,
> >  			},
> >  			.num_parents = 1,
> >  			.ops = &clk_branch_ops,
> > @@ -2613,7 +2687,7 @@ static struct clk_dyn_rcg nss_tcm_src = {
> >  		.enable_mask = BIT(1),
> >  		.hw.init = &(struct clk_init_data){
> >  			.name = "nss_tcm_src",
> > -			.parent_names = gcc_pxo_pll8_pll14_pll18_pll0,
> > +			.parent_data = gcc_pxo_pll8_pll14_pll18_pll0,
> >  			.num_parents = 5,
> >  			.ops = &clk_dyn_rcg_ops,
> >  		},
> > @@ -2628,8 +2702,8 @@ static struct clk_branch nss_tcm_clk = {
> >  		.enable_mask = BIT(6) | BIT(4),
> >  		.hw.init = &(struct clk_init_data){
> >  			.name = "nss_tcm_clk",
> > -			.parent_names = (const char *[]){
> > -				"nss_tcm_src",
> > +			.parent_data = &(const struct clk_parent_data){
> > +				.hw = &nss_tcm_src.clkr.hw,
> >  			},
> >  			.num_parents = 1,
> >  			.ops = &clk_branch_ops,
> > @@ -2691,7 +2765,7 @@ static struct clk_dyn_rcg ubi32_core1_src_clk = {
> >  		.enable_mask = BIT(1),
> >  		.hw.init = &(struct clk_init_data){
> >  			.name = "ubi32_core1_src_clk",
> > -			.parent_names = gcc_pxo_pll8_pll14_pll18_pll0,
> > +			.parent_data = gcc_pxo_pll8_pll14_pll18_pll0,
> >  			.num_parents = 5,
> >  			.ops = &clk_dyn_rcg_ops,
> >  			.flags = CLK_SET_RATE_PARENT | CLK_GET_RATE_NOCACHE,
> > @@ -2744,7 +2818,7 @@ static struct clk_dyn_rcg ubi32_core2_src_clk = {
> >  		.enable_mask = BIT(1),
> >  		.hw.init = &(struct clk_init_data){
> >  			.name = "ubi32_core2_src_clk",
> > -			.parent_names = gcc_pxo_pll8_pll14_pll18_pll0,
> > +			.parent_data = gcc_pxo_pll8_pll14_pll18_pll0,
> >  			.num_parents = 5,
> >  			.ops = &clk_dyn_rcg_ops,
> >  			.flags = CLK_SET_RATE_PARENT | CLK_GET_RATE_NOCACHE,
> > -- 
> > 2.33.1
> > 

-- 
	Ansuel

Re: [PATCH 01/14] dt-bindings: clock: Document qcom,gcc-ipq8064 binding

[Rob Herring]

On Tue, Jan 18, 2022 at 01:44:21AM +0100, Ansuel Smith wrote:
> Document qcom,gcc-ipq8064 binding needed to declare pxo and cxo source
> clocks. The gcc node is also used by the tsens driver, already Documented,
> to get the calib nvmem cells and the base reg from gcc.
> 
> Signed-off-by: Ansuel Smith <ansuelsmth@gmail.com>
> ---
>  .../bindings/clock/qcom,gcc-ipq8064.yaml      | 67 +++++++++++++++++++
>  1 file changed, 67 insertions(+)
>  create mode 100644 Documentation/devicetree/bindings/clock/qcom,gcc-ipq8064.yaml
> 
> diff --git a/Documentation/devicetree/bindings/clock/qcom,gcc-ipq8064.yaml b/Documentation/devicetree/bindings/clock/qcom,gcc-ipq8064.yaml
> new file mode 100644
> index 000000000000..2dc254fdf161
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/clock/qcom,gcc-ipq8064.yaml
> @@ -0,0 +1,67 @@
> +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/clock/qcom,gcc-ipq8064.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Qualcomm Global Clock & Reset Controller Binding for IPQ8064
> +
> +maintainers:
> +  - Ansuel Smith <ansuelsmth@gmail.com>
> +
> +description: |
> +  Qualcomm global clock control module which supports the clocks, resets and
> +  power domains on IPQ8064.
> +
> +properties:
> +  compatible:
> +    const: qcom,gcc-ipq8064
> +
> +  '#clock-cells':
> +    const: 1
> +
> +  '#reset-cells':
> +    const: 1
> +
> +  '#power-domain-cells':
> +    const: 1
> +
> +  reg:
> +    maxItems: 1
> +
> +  clocks:
> +    items:
> +      - description: PXO source
> +      - description: CX0 source
> +
> +  clock-names:
> +    items:
> +      - const: pxo
> +      - const: cxo
> +
> +required:
> +  - compatible
> +  - reg
> +  - '#clock-cells'
> +  - '#reset-cells'
> +  - '#power-domain-cells'
> +  - clocks
> +  - clock-names
> +
> +additionalProperties: true

Must be 'false'. True is only for incomplete schemas included by other 
schemas.

> +
> +examples:
> +  - |
> +    gcc: clock-controller@900000 {
> +      compatible = "qcom,gcc-ipq8064", "syscon";
> +      reg = <0x00900000 0x4000>;
> +      clocks = <&pxo_board>, <&cxo_board>;
> +      clock-names = "pxo", "cxo";
> +      #clock-cells = <1>;
> +      #reset-cells = <1>;
> +      #power-domain-cells = <1>;
> +
> +      /* Tsens node definition */

You need to define child nodes.

> +
> +    };
> +...
> -- 
> 2.33.1
> 
> 

Re: [PATCH 01/14] dt-bindings: clock: Document qcom,gcc-ipq8064 binding

[Ansuel Smith]

On Wed, Jan 19, 2022 at 07:59:03AM -0600, Rob Herring wrote:
> On Tue, Jan 18, 2022 at 01:44:21AM +0100, Ansuel Smith wrote:
> > Document qcom,gcc-ipq8064 binding needed to declare pxo and cxo source
> > clocks. The gcc node is also used by the tsens driver, already Documented,
> > to get the calib nvmem cells and the base reg from gcc.
> > 
> > Signed-off-by: Ansuel Smith <ansuelsmth@gmail.com>
> > ---
> >  .../bindings/clock/qcom,gcc-ipq8064.yaml      | 67 +++++++++++++++++++
> >  1 file changed, 67 insertions(+)
> >  create mode 100644 Documentation/devicetree/bindings/clock/qcom,gcc-ipq8064.yaml
> > 
> > diff --git a/Documentation/devicetree/bindings/clock/qcom,gcc-ipq8064.yaml b/Documentation/devicetree/bindings/clock/qcom,gcc-ipq8064.yaml
> > new file mode 100644
> > index 000000000000..2dc254fdf161
> > --- /dev/null
> > +++ b/Documentation/devicetree/bindings/clock/qcom,gcc-ipq8064.yaml
> > @@ -0,0 +1,67 @@
> > +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
> > +%YAML 1.2
> > +---
> > +$id: http://devicetree.org/schemas/clock/qcom,gcc-ipq8064.yaml#
> > +$schema: http://devicetree.org/meta-schemas/core.yaml#
> > +
> > +title: Qualcomm Global Clock & Reset Controller Binding for IPQ8064
> > +
> > +maintainers:
> > +  - Ansuel Smith <ansuelsmth@gmail.com>
> > +
> > +description: |
> > +  Qualcomm global clock control module which supports the clocks, resets and
> > +  power domains on IPQ8064.
> > +
> > +properties:
> > +  compatible:
> > +    const: qcom,gcc-ipq8064
> > +
> > +  '#clock-cells':
> > +    const: 1
> > +
> > +  '#reset-cells':
> > +    const: 1
> > +
> > +  '#power-domain-cells':
> > +    const: 1
> > +
> > +  reg:
> > +    maxItems: 1
> > +
> > +  clocks:
> > +    items:
> > +      - description: PXO source
> > +      - description: CX0 source
> > +
> > +  clock-names:
> > +    items:
> > +      - const: pxo
> > +      - const: cxo
> > +
> > +required:
> > +  - compatible
> > +  - reg
> > +  - '#clock-cells'
> > +  - '#reset-cells'
> > +  - '#power-domain-cells'
> > +  - clocks
> > +  - clock-names
> > +
> > +additionalProperties: true
> 
> Must be 'false'. True is only for incomplete schemas included by other 
> schemas.
> 
> > +
> > +examples:
> > +  - |
> > +    gcc: clock-controller@900000 {
> > +      compatible = "qcom,gcc-ipq8064", "syscon";
> > +      reg = <0x00900000 0x4000>;
> > +      clocks = <&pxo_board>, <&cxo_board>;
> > +      clock-names = "pxo", "cxo";
> > +      #clock-cells = <1>;
> > +      #reset-cells = <1>;
> > +      #power-domain-cells = <1>;
> > +
> > +      /* Tsens node definition */
> 
> You need to define child nodes.
>

Is it correct to put in the example the tsens node Documented in another
file? Or should I just remove the comment?

> > +
> > +    };
> > +...
> > -- 
> > 2.33.1
> > 
> > 

-- 
	Ansuel