From: Ansuel Smith <ansuelsmth@gmail.com>
To: Rob Herring <robh@kernel.org>
Cc: Andy Gross <agross@kernel.org>,
Bjorn Andersson <bjorn.andersson@linaro.org>,
Michael Turquette <mturquette@baylibre.com>,
Stephen Boyd <sboyd@kernel.org>,
Philipp Zabel <p.zabel@pengutronix.de>,
Taniya Das <tdas@codeaurora.org>,
linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org,
devicetree@vger.kernel.org, linux-kernel@vger.kernel.org
Subject: Re: [PATCH v2 03/15] dt-bindings: clock: Document qcom,gcc-ipq8064 binding
Date: Fri, 21 Jan 2022 20:07:50 +0100 [thread overview]
Message-ID: <61eb0488.1c69fb81.d267e.3b1f@mx.google.com> (raw)
In-Reply-To: <YeoUk3t2iVbQwj5s@robh.at.kernel.org>
On Thu, Jan 20, 2022 at 08:04:03PM -0600, Rob Herring wrote:
> On Fri, Jan 21, 2022 at 12:20:16AM +0100, Ansuel Smith wrote:
> > Document qcom,gcc-ipq8064 binding needed to declare pxo and cxo source
> > clocks. The gcc node is also used by the tsens driver, already documented,
> > to get the calib nvmem cells and the base reg from gcc.
> >
> > Signed-off-by: Ansuel Smith <ansuelsmth@gmail.com>
> > ---
> > .../bindings/clock/qcom,gcc-ipq8064.yaml | 70 +++++++++++++++++++
> > 1 file changed, 70 insertions(+)
> > create mode 100644 Documentation/devicetree/bindings/clock/qcom,gcc-ipq8064.yaml
> >
> > diff --git a/Documentation/devicetree/bindings/clock/qcom,gcc-ipq8064.yaml b/Documentation/devicetree/bindings/clock/qcom,gcc-ipq8064.yaml
> > new file mode 100644
> > index 000000000000..abc76a46b2ca
> > --- /dev/null
> > +++ b/Documentation/devicetree/bindings/clock/qcom,gcc-ipq8064.yaml
> > @@ -0,0 +1,70 @@
> > +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
> > +%YAML 1.2
> > +---
> > +$id: http://devicetree.org/schemas/clock/qcom,gcc-ipq8064.yaml#
> > +$schema: http://devicetree.org/meta-schemas/core.yaml#
> > +
> > +title: Qualcomm Global Clock & Reset Controller Binding for IPQ8064
> > +
> > +allOf:
> > + - $ref: qcom,gcc.yaml#
> > +
> > +maintainers:
> > + - Ansuel Smith <ansuelsmth@gmail.com>
> > +
> > +description: |
> > + Qualcomm global clock control module which supports the clocks, resets and
> > + power domains on IPQ8064.
> > +
> > + See also:
> > + - dt-bindings/clock/qcom,gcc-ipq806x.h
> > + - dt-bindings/reset/qcom,gcc-ipq806x.h
> > +
> > +properties:
>
> This schema will never be applied because there is not a compatible
> property to use for matching. The base/common schema is the one that
> shouldn't have a compatible and then the specific schemas like this
> one do.
>
Just to make things clear. To fix things up, what changes should I do?
- I should remove the compatible from the base schema qcom,gcc.yaml
- Add the compatible to this schema
- Create another schema that includes all the others compatible?
Can I instead:
- Create a qcom,gcc-common.yaml schema
- Modify the qcom,gcc.yaml schema to ref the common one and drop the
other binding.
- Fix this schema with the missing compatible?
Tell me how I should proceed since it looks to me that all the
Documentation for the gcc driver looks a bit mess and full of
duplicated stuff.
> > + clocks:
> > + items:
> > + - description: PXO source
> > + - description: CXO source
> > +
> > + clock-names:
> > + items:
> > + - const: pxo
> > + - const: cxo
> > +
> > + thermal-sensor:
> > + type: object
> > +
> > + allOf:
> > + - $ref: /schemas/thermal/qcom-tsens.yaml#
> > +
> > +required:
> > + - clocks
> > + - clock-names
> > +
> > +additionalProperties: false
> > +
> > +examples:
> > + - |
> > + #include <dt-bindings/interrupt-controller/arm-gic.h>
> > +
> > + gcc: clock-controller@900000 {
> > + compatible = "qcom,gcc-ipq8064", "syscon";
> > + reg = <0x00900000 0x4000>;
> > + clocks = <&pxo_board>, <&cxo_board>;
> > + clock-names = "pxo", "cxo";
> > + #clock-cells = <1>;
> > + #reset-cells = <1>;
> > + #power-domain-cells = <1>;
> > +
> > + tsens: thermal-sensor {
> > + compatible = "qcom,ipq8064-tsens";
> > +
> > + nvmem-cells = <&tsens_calib>, <&tsens_calib_backup>;
> > + nvmem-cell-names = "calib", "calib_backup";
> > + interrupts = <GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>;
> > + interrupt-names = "uplow";
> > +
> > + #qcom,sensors = <11>;
> > + #thermal-sensor-cells = <1>;
> > + };
> > + };
> > --
> > 2.33.1
> >
> >
--
Ansuel
next prev parent reply other threads:[~2022-01-21 19:07 UTC|newest]
Thread overview: 24+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-01-20 23:20 [PATCH v2 00/15] Multiple addition and improvement to ipq8064 gcc Ansuel Smith
2022-01-20 23:20 ` [PATCH v2 01/15] dt-bindings: clock: permit additionalProprieties to qcom,gcc Ansuel Smith
2022-01-21 1:53 ` Rob Herring
2022-01-20 23:20 ` [PATCH v2 02/15] dt-bindings: clock: simplify qcom,gcc-apq8064 Documentation Ansuel Smith
2022-01-21 1:37 ` Rob Herring
2022-01-21 1:41 ` Ansuel Smith
2022-01-21 2:01 ` Rob Herring
2022-01-20 23:20 ` [PATCH v2 03/15] dt-bindings: clock: Document qcom,gcc-ipq8064 binding Ansuel Smith
2022-01-21 1:37 ` Rob Herring
2022-01-21 2:04 ` Rob Herring
2022-01-21 19:07 ` Ansuel Smith [this message]
2022-01-21 19:22 ` Rob Herring
2022-01-20 23:20 ` [PATCH v2 04/15] drivers: clk: qcom: gcc-ipq806x: fix wrong naming for gcc_pxo_pll8_pll0 Ansuel Smith
2022-01-20 23:20 ` [PATCH v2 05/15] drivers: clk: qcom: gcc-ipq806x: convert parent_names to parent_data Ansuel Smith
2022-01-20 23:20 ` [PATCH v2 06/15] drivers: clk: qcom: gcc-ipq806x: use ARRAY_SIZE for num_parents Ansuel Smith
2022-01-20 23:20 ` [PATCH v2 07/15] drivers: clk: qcom: gcc-ipq806x: drop hardcoded pxo and cxo source clk Ansuel Smith
2022-01-20 23:20 ` [PATCH v2 08/15] drivers: clk: qcom: gcc-ipq806x: add additional freq nss cores Ansuel Smith
2022-01-20 23:20 ` [PATCH v2 09/15] drivers: clk: qcom: gcc-ipq806x: add unusued flag for critical clock Ansuel Smith
2022-01-20 23:20 ` [PATCH v2 10/15] drivers: clk: qcom: gcc-ipq806x: add additional freq for sdc table Ansuel Smith
2022-01-20 23:20 ` [PATCH v2 11/15] dt-bindings: clock: add ipq8064 ce5 clk define Ansuel Smith
2022-01-20 23:20 ` [PATCH v2 12/15] drivers: clk: qcom: gcc-ipq806x: add CryptoEngine clocks Ansuel Smith
2022-01-20 23:20 ` [PATCH v2 13/15] dt-bindings: reset: add ipq8064 ce5 resets Ansuel Smith
2022-01-20 23:20 ` [PATCH v2 14/15] drivers: clk: qcom: gcc-ipq806x: add CryptoEngine resets Ansuel Smith
2022-01-20 23:20 ` [PATCH v2 15/15] ARM: dts: qcom: Add syscon and cxo/pxo clock to gcc node for ipq8064 Ansuel Smith
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=61eb0488.1c69fb81.d267e.3b1f@mx.google.com \
--to=ansuelsmth@gmail.com \
--cc=agross@kernel.org \
--cc=bjorn.andersson@linaro.org \
--cc=devicetree@vger.kernel.org \
--cc=linux-arm-msm@vger.kernel.org \
--cc=linux-clk@vger.kernel.org \
--cc=linux-kernel@vger.kernel.org \
--cc=mturquette@baylibre.com \
--cc=p.zabel@pengutronix.de \
--cc=robh@kernel.org \
--cc=sboyd@kernel.org \
--cc=tdas@codeaurora.org \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).