* [PATCH] arm64: dts: socfpga: stratix10: add L2 cache info
@ 2024-05-15 18:12 Beniamin Sandu
2024-06-03 13:26 ` Dinh Nguyen
0 siblings, 1 reply; 2+ messages in thread
From: Beniamin Sandu @ 2024-05-15 18:12 UTC (permalink / raw)
To: devicetree, dinguyen; +Cc: robh, krzk+dt, conor+dt, Beniamin Sandu
This removes cacheinfo warnings at boot, e.g.:
cacheinfo: Unable to detect cache hierarchy for CPU 0
Signed-off-by: Beniamin Sandu <beniaminsandu@gmail.com>
---
arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi | 10 ++++++++++
1 file changed, 10 insertions(+)
diff --git a/arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi b/arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi
index cbbc53c47921..0def0b0daaf7 100644
--- a/arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi
+++ b/arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi
@@ -34,6 +34,7 @@ cpu0: cpu@0 {
compatible = "arm,cortex-a53";
device_type = "cpu";
enable-method = "psci";
+ next-level-cache = <&l2_shared>;
reg = <0x0>;
};
@@ -41,6 +42,7 @@ cpu1: cpu@1 {
compatible = "arm,cortex-a53";
device_type = "cpu";
enable-method = "psci";
+ next-level-cache = <&l2_shared>;
reg = <0x1>;
};
@@ -48,6 +50,7 @@ cpu2: cpu@2 {
compatible = "arm,cortex-a53";
device_type = "cpu";
enable-method = "psci";
+ next-level-cache = <&l2_shared>;
reg = <0x2>;
};
@@ -55,8 +58,15 @@ cpu3: cpu@3 {
compatible = "arm,cortex-a53";
device_type = "cpu";
enable-method = "psci";
+ next-level-cache = <&l2_shared>;
reg = <0x3>;
};
+
+ l2_shared: cache {
+ compatible = "cache";
+ cache-level = <2>;
+ cache-unified;
+ };
};
firmware {
--
2.34.1
^ permalink raw reply related [flat|nested] 2+ messages in thread* Re: [PATCH] arm64: dts: socfpga: stratix10: add L2 cache info
2024-05-15 18:12 [PATCH] arm64: dts: socfpga: stratix10: add L2 cache info Beniamin Sandu
@ 2024-06-03 13:26 ` Dinh Nguyen
0 siblings, 0 replies; 2+ messages in thread
From: Dinh Nguyen @ 2024-06-03 13:26 UTC (permalink / raw)
To: Beniamin Sandu, devicetree; +Cc: robh, krzk+dt, conor+dt
On 5/15/24 13:12, Beniamin Sandu wrote:
> This removes cacheinfo warnings at boot, e.g.:
> cacheinfo: Unable to detect cache hierarchy for CPU 0
>
> Signed-off-by: Beniamin Sandu <beniaminsandu@gmail.com>
> ---
> arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi | 10 ++++++++++
> 1 file changed, 10 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi b/arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi
> index cbbc53c47921..0def0b0daaf7 100644
> --- a/arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi
> +++ b/arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi
> @@ -34,6 +34,7 @@ cpu0: cpu@0 {
> compatible = "arm,cortex-a53";
> device_type = "cpu";
> enable-method = "psci";
> + next-level-cache = <&l2_shared>;
> reg = <0x0>;
> };
>
> @@ -41,6 +42,7 @@ cpu1: cpu@1 {
> compatible = "arm,cortex-a53";
> device_type = "cpu";
> enable-method = "psci";
> + next-level-cache = <&l2_shared>;
> reg = <0x1>;
> };
>
> @@ -48,6 +50,7 @@ cpu2: cpu@2 {
> compatible = "arm,cortex-a53";
> device_type = "cpu";
> enable-method = "psci";
> + next-level-cache = <&l2_shared>;
> reg = <0x2>;
> };
>
> @@ -55,8 +58,15 @@ cpu3: cpu@3 {
> compatible = "arm,cortex-a53";
> device_type = "cpu";
> enable-method = "psci";
> + next-level-cache = <&l2_shared>;
> reg = <0x3>;
> };
> +
> + l2_shared: cache {
> + compatible = "cache";
> + cache-level = <2>;
> + cache-unified;
> + };
> };
>
> firmware {
Applied!
Thanks,
Dinh
^ permalink raw reply [flat|nested] 2+ messages in thread
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2024-05-15 18:12 [PATCH] arm64: dts: socfpga: stratix10: add L2 cache info Beniamin Sandu
2024-06-03 13:26 ` Dinh Nguyen
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