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From: Heiko Stuebner <heiko@sntech.de>
To: Rudi Heitbaum <rudi@heitbaum.com>
Cc: robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org,
 devicetree@vger.kernel.org, linux-rockchip@lists.infradead.org,
 linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org,
 rudi@heitbaum.com
Subject:
 Re: [PATCH] arm64: dts: rockchip: rk3399pro-vmarc-som: add i2c2 scl timing
Date: Thu, 27 Aug 2026 15:18:01 +0200
Message-ID: <6298523.lOV4Wx5bFT@phil>
In-Reply-To: <aou1Q5-hdF7kRVpe@0d3a7a881997>
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Hi Rudi,

Am Montag, 24. August 2026, 05:06:43 Mitteleurop=C3=A4ische Sommerzeit schr=
ieb Rudi Heitbaum:
> The hym8563 on i2c2 does not ack:
>=20
>   rtc-hym8563 2-0051: could not init device, -6
>=20
> It is also the ext_clock for sdio-pwrseq, so wifi does not come up
> either.
>=20
> i2c2 runs at 400 kHz with no scl edge times. The core defaults both to
> 300 ns and rk3x-i2c calculates a 900 ns high period, which is short for
> this bus - it acks at 100 kHz. Set the edges to the values i2c3 already
> uses, giving 1050 ns at 400 kHz.
>=20
> Tested on a Radxa ROCK Pi N10: rtc0 registers and keeps time across a
> reboot, and wifi activates.

You tested on a Radxa Rock PI N10, but are changing the vmarc-som?
I'm not really understanding this.


Heiko

>=20
> Signed-off-by: Rudi Heitbaum <rudi@heitbaum.com>
> ---
>  arch/arm64/boot/dts/rockchip/rk3399pro-vmarc-som.dtsi | 2 ++
>  1 file changed, 2 insertions(+)
>=20
> diff --git a/arch/arm64/boot/dts/rockchip/rk3399pro-vmarc-som.dtsi b/arch=
/arm64/boot/dts/rockchip/rk3399pro-vmarc-som.dtsi
> index 64e6ba345739..074f09c6d11c 100644
> --- a/arch/arm64/boot/dts/rockchip/rk3399pro-vmarc-som.dtsi
> +++ b/arch/arm64/boot/dts/rockchip/rk3399pro-vmarc-som.dtsi
> @@ -296,6 +296,8 @@ &i2c1 {
> =20
>  &i2c2 {
>  	clock-frequency =3D <400000>;
> +	i2c-scl-falling-time-ns =3D <15>;
> +	i2c-scl-rising-time-ns =3D <450>;
>  	status =3D "okay";
> =20
>  	hym8563: rtc@51 {
>=20