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[93.42.70.190]) by smtp.gmail.com with ESMTPSA id d10-20020a1709063cea00b006f3ef214e5bsm10963516ejh.193.2022.06.09.10.10.36 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 09 Jun 2022 10:10:36 -0700 (PDT) Message-ID: <62a2298c.1c69fb81.bc909.d2d0@mx.google.com> X-Google-Original-Message-ID: Date: Thu, 9 Jun 2022 19:10:33 +0200 From: Ansuel Smith To: Manivannan Sadhasivam Cc: Andy Gross , Bjorn Andersson , Miquel Raynal , Richard Weinberger , Vignesh Raghavendra , Rob Herring , Krzysztof Kozlowski , linux-mtd@lists.infradead.org, linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: Re: [PATCH v6 1/3] mtd: nand: raw: qcom_nandc: reorder qcom_nand_host struct References: <20220609132344.17548-1-ansuelsmth@gmail.com> <20220609132344.17548-2-ansuelsmth@gmail.com> <20220609170722.GA5081@thinkpad> MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Disposition: inline Content-Transfer-Encoding: 8bit In-Reply-To: <20220609170722.GA5081@thinkpad> Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org On Thu, Jun 09, 2022 at 10:37:22PM +0530, Manivannan Sadhasivam wrote: > On Thu, Jun 09, 2022 at 03:23:42PM +0200, Ansuel Smith wrote: > > Reorder qcom_nand_host to save holes in the struct. > > You forgot to reorder other structs also as I requested :/ > > Thanks, > Mani > Mhhh I didn't find obvius hole in other struct. Think I will pass this with dwarf to better check them. Sorry! Feel free to point them if you notice obvius hole that I didn't notice. > > > > Signed-off-by: Ansuel Smith > > --- > > drivers/mtd/nand/raw/qcom_nandc.c | 10 ++++++---- > > 1 file changed, 6 insertions(+), 4 deletions(-) > > > > diff --git a/drivers/mtd/nand/raw/qcom_nandc.c b/drivers/mtd/nand/raw/qcom_nandc.c > > index 1a77542c6d67..7fbbd3e7784c 100644 > > --- a/drivers/mtd/nand/raw/qcom_nandc.c > > +++ b/drivers/mtd/nand/raw/qcom_nandc.c > > @@ -431,11 +431,12 @@ struct qcom_nand_controller { > > * and reserved bytes > > * @cw_data: the number of bytes within a codeword protected > > * by ECC > > + * @ecc_bytes_hw: ECC bytes used by controller hardware for this > > + * chip > > + * > > * @use_ecc: request the controller to use ECC for the > > * upcoming read/write > > * @bch_enabled: flag to tell whether BCH ECC mode is used > > - * @ecc_bytes_hw: ECC bytes used by controller hardware for this > > - * chip > > * @status: value to be returned if NAND_CMD_STATUS command > > * is executed > > * @last_command: keeps track of last command on this chip. used > > @@ -452,11 +453,12 @@ struct qcom_nand_host { > > int cs; > > int cw_size; > > int cw_data; > > - bool use_ecc; > > - bool bch_enabled; > > int ecc_bytes_hw; > > int spare_bytes; > > int bbm_size; > > + > > + bool use_ecc; > > + bool bch_enabled; > > u8 status; > > int last_command; > > > > -- > > 2.36.1 > > > > -- > மணிவண்ணன் சதாசிவம் -- Ansuel