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[93.42.70.190]) by smtp.gmail.com with ESMTPSA id e13-20020adfe7cd000000b0021b89181863sm9762729wrn.41.2022.06.21.13.23.17 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 21 Jun 2022 13:23:18 -0700 (PDT) Message-ID: <62b228b6.1c69fb81.e4673.34a2@mx.google.com> X-Google-Original-Message-ID: Date: Tue, 21 Jun 2022 22:23:16 +0200 From: Christian Marangi To: Dmitry Baryshkov Cc: Bjorn Andersson , Andy Gross , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org Subject: Re: [PATCH v2 3/3] clk: qcom: lcc-ipq806x: convert to parent data References: <20220621163326.16858-1-ansuelsmth@gmail.com> <20220621163326.16858-3-ansuelsmth@gmail.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org On Tue, Jun 21, 2022 at 08:15:57PM +0300, Dmitry Baryshkov wrote: > On Tue, 21 Jun 2022 at 19:33, Christian Marangi wrote: > > > > Convert lcc-ipq806x driver to parent_data API. > > > > Signed-off-by: Christian Marangi > > --- > > v2: > > - Fix Sob tag > > > > drivers/clk/qcom/lcc-ipq806x.c | 79 +++++++++++++++++++--------------- > > 1 file changed, 44 insertions(+), 35 deletions(-) > > > > diff --git a/drivers/clk/qcom/lcc-ipq806x.c b/drivers/clk/qcom/lcc-ipq806x.c > > index ba90bebba597..c07ca8dc6e3a 100644 > > --- a/drivers/clk/qcom/lcc-ipq806x.c > > +++ b/drivers/clk/qcom/lcc-ipq806x.c > > @@ -24,6 +24,10 @@ > > #include "clk-regmap-mux.h" > > #include "reset.h" > > > > +static const struct clk_parent_data gcc_pxo[] = { > > + { .fw_name = "pxo", .name = "pxo" }, > > I think you'd use .name = "pxo_board" here. You don't need to use the > interim clock. > In gcc and in the rest of this driver we use pxo. Wonder what is right? > > +}; > > + > > static struct clk_pll pll4 = { > > .l_reg = 0x4, > > .m_reg = 0x8, > > @@ -34,7 +38,7 @@ static struct clk_pll pll4 = { > > .status_bit = 16, > > .clkr.hw.init = &(struct clk_init_data){ > > .name = "pll4", > > - .parent_names = (const char *[]){ "pxo" }, > > + .parent_data = gcc_pxo, > > .num_parents = 1, > > Could you please either inline the gcc_pxo here (yes, it's ugly, but > it works for small arrays) or use ARRAY_SIZE here. > Yes will inline gcc_pxo. > > .ops = &clk_pll_ops, > > }, > > @@ -64,9 +68,9 @@ static const struct parent_map lcc_pxo_pll4_map[] = { > > { P_PLL4, 2 } > > }; > > > > -static const char * const lcc_pxo_pll4[] = { > > - "pxo", > > - "pll4_vote", > > +static const struct clk_parent_data lcc_pxo_pll4[] = { > > + { .fw_name = "pxo", .name = "pxo" }, > > + { .fw_name = "pll4_vote", .name = "pll4_vote" }, > > }; > > > > static struct freq_tbl clk_tbl_aif_mi2s[] = { > > @@ -131,18 +135,14 @@ static struct clk_rcg mi2s_osr_src = { > > .enable_mask = BIT(9), > > .hw.init = &(struct clk_init_data){ > > .name = "mi2s_osr_src", > > - .parent_names = lcc_pxo_pll4, > > - .num_parents = 2, > > + .parent_data = lcc_pxo_pll4, > > + .num_parents = ARRAY_SIZE(lcc_pxo_pll4), > > .ops = &clk_rcg_ops, > > .flags = CLK_SET_RATE_GATE, > > }, > > }, > > }; > > > > -static const char * const lcc_mi2s_parents[] = { > > - "mi2s_osr_src", > > -}; > > - > > static struct clk_branch mi2s_osr_clk = { > > .halt_reg = 0x50, > > .halt_bit = 1, > > @@ -152,7 +152,9 @@ static struct clk_branch mi2s_osr_clk = { > > .enable_mask = BIT(17), > > .hw.init = &(struct clk_init_data){ > > .name = "mi2s_osr_clk", > > - .parent_names = lcc_mi2s_parents, > > + .parent_hws = (const struct clk_hw*[]){ > > + &mi2s_osr_src.clkr.hw, > > + }, > > .num_parents = 1, > > .ops = &clk_branch_ops, > > .flags = CLK_SET_RATE_PARENT, > > @@ -167,7 +169,9 @@ static struct clk_regmap_div mi2s_div_clk = { > > .clkr = { > > .hw.init = &(struct clk_init_data){ > > .name = "mi2s_div_clk", > > - .parent_names = lcc_mi2s_parents, > > + .parent_hws = (const struct clk_hw*[]){ > > + &mi2s_osr_src.clkr.hw, > > + }, > > .num_parents = 1, > > .ops = &clk_regmap_div_ops, > > }, > > @@ -183,7 +187,9 @@ static struct clk_branch mi2s_bit_div_clk = { > > .enable_mask = BIT(15), > > .hw.init = &(struct clk_init_data){ > > .name = "mi2s_bit_div_clk", > > - .parent_names = (const char *[]){ "mi2s_div_clk" }, > > + .parent_hws = (const struct clk_hw*[]){ > > + &mi2s_div_clk.clkr.hw, > > + }, > > .num_parents = 1, > > .ops = &clk_branch_ops, > > .flags = CLK_SET_RATE_PARENT, > > @@ -191,6 +197,10 @@ static struct clk_branch mi2s_bit_div_clk = { > > }, > > }; > > > > +static const struct clk_parent_data lcc_mi2s_bit_div_codec_clk[] = { > > + { .hw = &mi2s_bit_div_clk.clkr.hw, }, > > + { .fw_name = "mi2s_codec_clk", .name = "mi2s_codec_clk" }, > > +}; > > > > static struct clk_regmap_mux mi2s_bit_clk = { > > .reg = 0x48, > > @@ -199,11 +209,8 @@ static struct clk_regmap_mux mi2s_bit_clk = { > > .clkr = { > > .hw.init = &(struct clk_init_data){ > > .name = "mi2s_bit_clk", > > - .parent_names = (const char *[]){ > > - "mi2s_bit_div_clk", > > - "mi2s_codec_clk", > > - }, > > - .num_parents = 2, > > + .parent_data = lcc_mi2s_bit_div_codec_clk, > > + .num_parents = ARRAY_SIZE(lcc_mi2s_bit_div_codec_clk), > > .ops = &clk_regmap_mux_closest_ops, > > .flags = CLK_SET_RATE_PARENT, > > }, > > @@ -245,8 +252,8 @@ static struct clk_rcg pcm_src = { > > .enable_mask = BIT(9), > > .hw.init = &(struct clk_init_data){ > > .name = "pcm_src", > > - .parent_names = lcc_pxo_pll4, > > - .num_parents = 2, > > + .parent_data = lcc_pxo_pll4, > > + .num_parents = ARRAY_SIZE(lcc_pxo_pll4), > > .ops = &clk_rcg_ops, > > .flags = CLK_SET_RATE_GATE, > > }, > > @@ -262,7 +269,9 @@ static struct clk_branch pcm_clk_out = { > > .enable_mask = BIT(11), > > .hw.init = &(struct clk_init_data){ > > .name = "pcm_clk_out", > > - .parent_names = (const char *[]){ "pcm_src" }, > > + .parent_hws = (const struct clk_hw*[]){ > > + &pcm_src.clkr.hw, > > + }, > > .num_parents = 1, > > .ops = &clk_branch_ops, > > .flags = CLK_SET_RATE_PARENT, > > @@ -270,6 +279,11 @@ static struct clk_branch pcm_clk_out = { > > }, > > }; > > > > +static const struct clk_parent_data lcc_pcm_clk_out_codec_clk[] = { > > + { .hw = &pcm_clk_out.clkr.hw, }, > > + { .fw_name = "pcm_codec_clk", .name = "pcm_codec_clk" }, > > +}; > > + > > static struct clk_regmap_mux pcm_clk = { > > .reg = 0x54, > > .shift = 10, > > @@ -277,11 +291,8 @@ static struct clk_regmap_mux pcm_clk = { > > .clkr = { > > .hw.init = &(struct clk_init_data){ > > .name = "pcm_clk", > > - .parent_names = (const char *[]){ > > - "pcm_clk_out", > > - "pcm_codec_clk", > > - }, > > - .num_parents = 2, > > + .parent_data = lcc_pcm_clk_out_codec_clk, > > + .num_parents = ARRAY_SIZE(lcc_pcm_clk_out_codec_clk), > > .ops = &clk_regmap_mux_closest_ops, > > .flags = CLK_SET_RATE_PARENT, > > }, > > @@ -325,18 +336,14 @@ static struct clk_rcg spdif_src = { > > .enable_mask = BIT(9), > > .hw.init = &(struct clk_init_data){ > > .name = "spdif_src", > > - .parent_names = lcc_pxo_pll4, > > - .num_parents = 2, > > + .parent_data = lcc_pxo_pll4, > > + .num_parents = ARRAY_SIZE(lcc_pxo_pll4), > > .ops = &clk_rcg_ops, > > .flags = CLK_SET_RATE_GATE, > > }, > > }, > > }; > > > > -static const char * const lcc_spdif_parents[] = { > > - "spdif_src", > > -}; > > - > > static struct clk_branch spdif_clk = { > > .halt_reg = 0xd4, > > .halt_bit = 1, > > @@ -346,7 +353,9 @@ static struct clk_branch spdif_clk = { > > .enable_mask = BIT(12), > > .hw.init = &(struct clk_init_data){ > > .name = "spdif_clk", > > - .parent_names = lcc_spdif_parents, > > + .parent_hws = (const struct clk_hw*[]){ > > + &spdif_src.clkr.hw, > > + }, > > .num_parents = 1, > > .ops = &clk_branch_ops, > > .flags = CLK_SET_RATE_PARENT, > > @@ -384,8 +393,8 @@ static struct clk_rcg ahbix_clk = { > > .enable_mask = BIT(11), > > .hw.init = &(struct clk_init_data){ > > .name = "ahbix", > > - .parent_names = lcc_pxo_pll4, > > - .num_parents = 2, > > + .parent_data = lcc_pxo_pll4, > > + .num_parents = ARRAY_SIZE(lcc_pxo_pll4), > > .ops = &clk_rcg_lcc_ops, > > }, > > }, > > -- > > 2.36.1 > > > > > -- > With best wishes > Dmitry -- Ansuel