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From: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
To: Simon Horman <horms@verge.net.au>,
	Rob Herring <robh+dt@kernel.org>,
	Catalin Marinas <catalin.marinas@arm.com>,
	Will Deacon <will.deacon@arm.com>,
	linux-renesas-soc@vger.kernel.org, devicetree@vger.kernel.org
Cc: Mark Rutland <mark.rutland@arm.com>,
	Magnus Damm <magnus.damm@gmail.com>,
	linux-arm-kernel@lists.infradead.org
Subject: [PATCH 3/3] arm64: dts: renesas: condor: add PCIe support
Date: Fri, 6 Apr 2018 23:19:59 +0300	[thread overview]
Message-ID: <62d9dbbe-9f11-303c-56dd-3dcdaf48bcc1@cogentembedded.com> (raw)
In-Reply-To: <f07e6173-75b3-fe10-81d6-915942a5f4fe@cogentembedded.com>

Enable PCIe PHY and PCIEC and specify the PCIe bus clock for the Condor
board.

Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>

---
 arch/arm64/boot/dts/renesas/r8a77980-condor.dts |   12 ++++++++++++
 1 file changed, 12 insertions(+)

Index: renesas/arch/arm64/boot/dts/renesas/r8a77980-condor.dts
===================================================================
--- renesas.orig/arch/arm64/boot/dts/renesas/r8a77980-condor.dts
+++ renesas/arch/arm64/boot/dts/renesas/r8a77980-condor.dts
@@ -49,6 +49,18 @@
 	clock-frequency = <32768>;
 };
 
+&pciec {
+	status = "okay";
+};
+
+&pcie_bus_clk {
+	clock-frequency = <100000000>;
+};
+
+&pcie_phy {
+	status = "okay";
+};
+
 &scif0 {
 	status = "okay";
 };

  parent reply	other threads:[~2018-04-06 20:19 UTC|newest]

Thread overview: 5+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2018-04-06 20:11 [PATCH 0/3] Add R8A77980/Condor PCIe support Sergei Shtylyov
2018-04-06 20:17 ` [PATCH 1/3] arm64: dts: renesas: r8a77980: add PCIe PHY support Sergei Shtylyov
2018-04-06 20:18 ` [PATCH 2/3] arm64: dts: renesas: r8a77980: add PCIEC support Sergei Shtylyov
2018-04-06 20:19 ` Sergei Shtylyov [this message]
2018-04-18 13:57 ` [PATCH 0/3] Add R8A77980/Condor PCIe support Simon Horman

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