From mboxrd@z Thu Jan 1 00:00:00 1970 From: Sergei Shtylyov Subject: [PATCH 3/3] arm64: dts: renesas: condor: add PCIe support Date: Fri, 6 Apr 2018 23:19:59 +0300 Message-ID: <62d9dbbe-9f11-303c-56dd-3dcdaf48bcc1@cogentembedded.com> References: Mime-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Return-path: In-Reply-To: Content-Language: en-MW List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=m.gmane.org@lists.infradead.org To: Simon Horman , Rob Herring , Catalin Marinas , Will Deacon , linux-renesas-soc@vger.kernel.org, devicetree@vger.kernel.org Cc: Mark Rutland , Magnus Damm , linux-arm-kernel@lists.infradead.org List-Id: devicetree@vger.kernel.org Enable PCIe PHY and PCIEC and specify the PCIe bus clock for the Condor board. Signed-off-by: Sergei Shtylyov --- arch/arm64/boot/dts/renesas/r8a77980-condor.dts | 12 ++++++++++++ 1 file changed, 12 insertions(+) Index: renesas/arch/arm64/boot/dts/renesas/r8a77980-condor.dts =================================================================== --- renesas.orig/arch/arm64/boot/dts/renesas/r8a77980-condor.dts +++ renesas/arch/arm64/boot/dts/renesas/r8a77980-condor.dts @@ -49,6 +49,18 @@ clock-frequency = <32768>; }; +&pciec { + status = "okay"; +}; + +&pcie_bus_clk { + clock-frequency = <100000000>; +}; + +&pcie_phy { + status = "okay"; +}; + &scif0 { status = "okay"; };