From mboxrd@z Thu Jan 1 00:00:00 1970 From: Arnd Bergmann Subject: Re: [PATCH v12 10/12] PCI: Assign unassigned bus resources in pci_scan_root_bus() Date: Mon, 29 Sep 2014 20:18:02 +0200 Message-ID: <6332476.od04BfvKGr@wuerfel> References: <1411498874-9864-1-git-send-email-Liviu.Dudau@arm.com> <54287AA5.3060408@amd.com> Mime-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7Bit Return-path: In-Reply-To: <54287AA5.3060408@amd.com> Sender: linux-pci-owner@vger.kernel.org To: linux-arm-kernel@lists.infradead.org Cc: Suravee Suthikulpanit , Bjorn Helgaas , Liviu Dudau , linux-arch , Grant Likely , Kukjin Kim , Russell King , Device Tree ML , linux-pci , Benjamin Herrenschmidt , Linus Walleij , Jingoo Han , Liviu Dudau , LKML , Will Deacon , Jason Gunthorpe , Rob Herring , Tanmay Inamdar , Catalin Marinas , Sinan Kaya List-Id: devicetree@vger.kernel.org On Sunday 28 September 2014 16:16:21 Suravee Suthikulpanit wrote: > > > > I'm not opposed to it, but I have the same question as for setting up > > the domain: how does pci_scan_root_bus() learn what to assign to > > bus->msi? It currently only gets a "void *sysdata" so there's no > > obvious place to put it there. You could add a pcibios interface to > > retrieve it, I suppose, but I'm starting to get uncomfortable with > > adding more of those because we have such a mess of them already. > > > > [Suravee] Liviu and I had a talk during Linaro Connect, and we came up > with a new binding for the pcie controller called "msi-parent" which is > supposed to contain phandle to the corresponded msi-controller. Is this based on the property that we have in the pci-mvebu driver? I hope this is meant to be compatible so we can share the implementation. Arnd