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Thu, 21 May 2026 08:36:09 -0700 (PDT) Message-ID: <634c0951-dabb-4505-ad52-4101a8ec0bbd@linaro.org> Date: Thu, 21 May 2026 16:36:08 +0100 Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v6 1/2] dt-bindings: phy: qcom: Add CSI2 C-PHY/DPHY schema To: sashiko-reviews@lists.linux.dev Cc: vkoul@kernel.org, neil.armstrong@linaro.org, devicetree@vger.kernel.org, conor+dt@kernel.org, olteanv@gmail.com, linux-phy@lists.infradead.org, robh@kernel.org References: <20260521-x1e-csi2-phy-v6-1-9d73d9bd7d20@linaro.org> <20260521122645.3EF9B1F000E9@smtp.kernel.org> Content-Language: en-US From: Bryan O'Donoghue In-Reply-To: <20260521122645.3EF9B1F000E9@smtp.kernel.org> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit On 21/05/2026 13:26, sashiko-bot@kernel.org wrote: > Thank you for your contribution! Sashiko AI review found 2 potential issue(s) to consider: > - [Medium] The schema unconditionally requires `clock-lanes` for `port@0`, which incorrectly breaks C-PHY configurations. > - [Low] The example device tree node is missing required `data-lanes` and `clock-lanes` properties in the `port@0` endpoint. > -- > > commit bec75335fd5214a065f090cefeb28f9c895cfd3c > Author: Bryan O'Donoghue > > dt-bindings: phy: qcom: Add CSI2 C-PHY/DPHY schema > > This commit adds a new base devicetree schema for Qualcomm MIPI CSI2 PHY > devices, initially for the x1e80100. It supports CPHY, DPHY, and DPHY split > modes across three ports, allowing per-PHY voltage rails to be individually > defined and required. > >> diff --git a/Documentation/devicetree/bindings/phy/qcom,x1e80100-csi2-phy.yaml b/Documentation/devicetree/bindings/phy/qcom,x1e80100-csi2-phy.yaml >> new file mode 100644 >> index 0000000000000..c9116246c1e9e >> --- /dev/null >> +++ b/Documentation/devicetree/bindings/phy/qcom,x1e80100-csi2-phy.yaml > [ ... ] >> + properties: >> + port@0: >> + $ref: /schemas/graph.yaml#/$defs/port-base >> + description: Sensor input. Always present. >> + >> + properties: >> + endpoint: >> + $ref: /schemas/media/video-interfaces.yaml# >> + unevaluatedProperties: false >> + properties: >> + data-lanes: >> + minItems: 1 >> + maxItems: 4 >> + clock-lanes: >> + maxItems: 1 >> + remote-endpoint: true >> + required: >> + - data-lanes >> + - clock-lanes > > [Severity: Medium] > The commit description mentions the PHY supports both C-PHY and D-PHY modes. > Since C-PHY embeds the clock signal within the 3-phase data lanes, there isn't > a separate physical clock lane. Does requiring clock-lanes unconditionally > here break configurations that need to use C-PHY mode? Fair hadn't thought of that. > >> + - remote-endpoint > [ ... ] >> +examples: >> + - | > [ ... ] >> + ports { >> + #address-cells = <1>; >> + #size-cells = <0>; >> + >> + port@0 { >> + reg = <0>; >> + csiphy0_in_ep: endpoint { >> + remote-endpoint = <&sensor_out>; > > [Severity: Low] > The schema definition above explicitly requires data-lanes and clock-lanes to > be present in the port@0 endpoint. Will omitting them from this example cause > a validation failure when running dt_binding_check? Yes this is what happens when you ask the question "should I run the check one more time" and say no. >> + }; >> + }; >> + >> + port@2 { >> + reg = <2>; >> + csiphy0_out_ep: endpoint { >> + remote-endpoint = <&controller_in>; >> + }; >> + }; >> + }; >> + }; > [ ... ] >