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[93.34.92.88]) by smtp.gmail.com with ESMTPSA id x7-20020a05600c188700b003c701c12a17sm27788319wmp.12.2023.01.13.05.18.51 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 13 Jan 2023 05:18:52 -0800 (PST) Message-ID: <63c15a3c.050a0220.5f7c6.1db3@mx.google.com> X-Google-Original-Message-ID: Date: Fri, 13 Jan 2023 14:18:51 +0100 From: Christian Marangi To: Dmitry Baryshkov Cc: Rob Herring , Krzysztof Kozlowski , Andy Gross , Bjorn Andersson , Konrad Dybcio , Michael Turquette , Stephen Boyd , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org Subject: Re: [PATCH v6 2/6] dt-bindings: arm: msm: Convert and split kpss-acc driver Documentation to yaml References: <20230110183259.19142-1-ansuelsmth@gmail.com> <20230110183259.19142-3-ansuelsmth@gmail.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org On Thu, Jan 12, 2023 at 06:00:10AM +0200, Dmitry Baryshkov wrote: > On 10/01/2023 20:32, Christian Marangi wrote: > > Convert kpss-acc driver Documentation to yaml. > > The original Documentation was wrong all along. Fix it while we are > > converting it. > > The example was wrong as kpss-acc-v2 should only expose the regs but we > > don't have any driver that expose additional clocks. The kpss-acc driver > > is only specific to v1. For this exact reason, split the Documentation > > to 2 different schema, v1 as clock-controller and v2 for > > power-controller as per msm-3.10 specification, the exposed regs handle > > power domains. > > > > Signed-off-by: Christian Marangi > > --- > > .../bindings/arm/msm/qcom,kpss-acc.txt | 49 ------------- > > .../bindings/clock/qcom,kpss-acc-v1.yaml | 72 +++++++++++++++++++ > > .../bindings/power/qcom,kpss-acc-v2.yaml | 47 ++++++++++++ > > 3 files changed, 119 insertions(+), 49 deletions(-) > > delete mode 100644 Documentation/devicetree/bindings/arm/msm/qcom,kpss-acc.txt > > create mode 100644 Documentation/devicetree/bindings/clock/qcom,kpss-acc-v1.yaml > > create mode 100644 Documentation/devicetree/bindings/power/qcom,kpss-acc-v2.yaml > > > > diff --git a/Documentation/devicetree/bindings/arm/msm/qcom,kpss-acc.txt b/Documentation/devicetree/bindings/arm/msm/qcom,kpss-acc.txt > > deleted file mode 100644 > > index 7f696362a4a1..000000000000 > > --- a/Documentation/devicetree/bindings/arm/msm/qcom,kpss-acc.txt > > +++ /dev/null > > @@ -1,49 +0,0 @@ > > -Krait Processor Sub-system (KPSS) Application Clock Controller (ACC) > > - > > -The KPSS ACC provides clock, power domain, and reset control to a Krait CPU. > > -There is one ACC register region per CPU within the KPSS remapped region as > > -well as an alias register region that remaps accesses to the ACC associated > > -with the CPU accessing the region. > > - > > -PROPERTIES > > - > > -- compatible: > > - Usage: required > > - Value type: > > - Definition: should be one of: > > - "qcom,kpss-acc-v1" > > - "qcom,kpss-acc-v2" > > - > > -- reg: > > - Usage: required > > - Value type: > > - Definition: the first element specifies the base address and size of > > - the register region. An optional second element specifies > > - the base address and size of the alias register region. > > - > > -- clocks: > > - Usage: required > > - Value type: > > - Definition: reference to the pll parents. > > - > > -- clock-names: > > - Usage: required > > - Value type: > > - Definition: must be "pll8_vote", "pxo". > > - > > -- clock-output-names: > > - Usage: optional > > - Value type: > > - Definition: Name of the output clock. Typically acpuX_aux where X is a > > - CPU number starting at 0. > > - > > -Example: > > - > > - clock-controller@2088000 { > > - compatible = "qcom,kpss-acc-v2"; > > - reg = <0x02088000 0x1000>, > > - <0x02008000 0x1000>; > > - clocks = <&gcc PLL8_VOTE>, <&gcc PXO_SRC>; > > - clock-names = "pll8_vote", "pxo"; > > - clock-output-names = "acpu0_aux"; > > - }; > > diff --git a/Documentation/devicetree/bindings/clock/qcom,kpss-acc-v1.yaml b/Documentation/devicetree/bindings/clock/qcom,kpss-acc-v1.yaml > > new file mode 100644 > > index 000000000000..a466e4e8aacd > > --- /dev/null > > +++ b/Documentation/devicetree/bindings/clock/qcom,kpss-acc-v1.yaml > > @@ -0,0 +1,72 @@ > > +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause > > +%YAML 1.2 > > +--- > > +$id: http://devicetree.org/schemas/clock/qcom,kpss-acc-v1.yaml# > > +$schema: http://devicetree.org/meta-schemas/core.yaml# > > + > > +title: Krait Processor Sub-system (KPSS) Application Clock Controller (ACC) v1 > > + > > +maintainers: > > + - Christian Marangi > > + > > +description: > > + The KPSS ACC provides clock, power domain, and reset control to a Krait CPU. > > + There is one ACC register region per CPU within the KPSS remapped region as > > + well as an alias register region that remaps accesses to the ACC associated > > + with the CPU accessing the region. ACC v1 is currently used as a > > + clock-controller for enabling the cpu and hanling the aux clocks. > > + > > +properties: > > + compatible: > > + const: qcom,kpss-acc-v1 > > + > > + reg: > > + items: > > + - description: Base address and size of the register region > > + - description: Optional base address and size of the alias register region > > + minItems: 1 > > + > > + clocks: > > + minItems: 2 > > + maxItems: 2 > > + > > + clock-names: > > + items: > > + - const: pll8_vote > > + - const: pxo > > + > > + clock-output-names: > > + description: Name of the aux clock. Krait can have at most 4 cpu. > > + enum: > > + - acpu0_aux > > + - acpu1_aux > > + - acpu2_aux > > + - acpu3_aux > > + > > + '#clock-cells': > > + const: 0 > > + > > +required: > > + - compatible > > + - reg > > + - clocks > > + - clock-names > > + - clock-output-names > > + - '#clock-cells' > > + > > +additionalProperties: false > > + > > +examples: > > + - | > > + #include > > + > > + clock-controller@2088000 { > > + compatible = "qcom,kpss-acc-v1"; > > + reg = <0x02088000 0x1000>, <0x02008000 0x1000>; > > + clocks = <&gcc PLL8_VOTE>, <&pxo_board>; > > + clock-names = "pll8_vote", "pxo"; > > + clock-output-names = "acpu0_aux"; > > + #clock-cells = <0>; > > + }; > > + > > +... > > diff --git a/Documentation/devicetree/bindings/power/qcom,kpss-acc-v2.yaml b/Documentation/devicetree/bindings/power/qcom,kpss-acc-v2.yaml > > new file mode 100644 > > index 000000000000..91af95569ae6 > > --- /dev/null > > +++ b/Documentation/devicetree/bindings/power/qcom,kpss-acc-v2.yaml > > @@ -0,0 +1,47 @@ > > +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause > > +%YAML 1.2 > > +--- > > +$id: http://devicetree.org/schemas/power/qcom,kpss-acc-v2.yaml# > > +$schema: http://devicetree.org/meta-schemas/core.yaml# > > + > > +title: Krait Processor Sub-system (KPSS) Application Clock Controller (ACC) v2 > > + > > +maintainers: > > + - Christian Marangi > > + > > +description: > > + The KPSS ACC provides clock, power domain, and reset control to a Krait CPU. > > + There is one ACC register region per CPU within the KPSS remapped region as > > + well as an alias register region that remaps accesses to the ACC associated > > + with the CPU accessing the region. ACC v2 is currently used as a > > + power-controller for enabling the cpu. > > + > > +properties: > > + compatible: > > + const: qcom,kpss-acc-v2 > > + > > + reg: > > + items: > > + - description: Base address and size of the register region > > + - description: Optional base address and size of the alias register region > > + minItems: 1 > > + > > + '#power-domain-cells': > > + const: 0 > > + > > +required: > > + - compatible > > + - reg > > + - '#power-domain-cells' > > This dictates that if at some point we implement the kps-acc-v2 driver, it > will return a single power domain. I can not confirm that this would be the > case. I see that you want to migrate from the clock-controller as the acc-v2 > doesn't provide clocks. I'd suggest instead using the neutral > `power-manager@...` node name. It doesn't demand anything, so we can drop > the (unused and unsupported) #power-domain-cells property. > Thanks for the review of the series and thanks for the suggestion. Will do the change and send v7 hoping it's the final revision. > > + > > +additionalProperties: false > > + > > +examples: > > + - | > > + power-controller@f9088000 { > > + compatible = "qcom,kpss-acc-v2"; > > + reg = <0xf9088000 0x1000>, > > + <0xf9008000 0x1000>; > > + #power-domain-cells = <0>; > > + }; > > +... > > -- > With best wishes > Dmitry > -- Ansuel