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([2a01:e34:ed2f:f020:3590:b402:869a:11fc]) by smtp.googlemail.com with ESMTPSA id d14sm4547519wre.44.2020.07.21.04.02.45 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Tue, 21 Jul 2020 04:02:46 -0700 (PDT) Subject: Re: [PATCH v4 2/4] clocksource/drivers: Add CLINT timer driver To: Anup Patel , Palmer Dabbelt , Paul Walmsley , Albert Ou , Rob Herring , Thomas Gleixner Cc: Damien Le Moal , Atish Patra , Alistair Francis , Anup Patel , linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, Emil Renner Berhing References: <20200717075101.263332-1-anup.patel@wdc.com> <20200717075101.263332-3-anup.patel@wdc.com> From: Daniel Lezcano Message-ID: <63f65ddd-b7c4-b8fd-151c-a77e8c87efed@linaro.org> Date: Tue, 21 Jul 2020 13:02:45 +0200 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:68.0) Gecko/20100101 Thunderbird/68.10.0 MIME-Version: 1.0 In-Reply-To: <20200717075101.263332-3-anup.patel@wdc.com> Content-Type: text/plain; charset=utf-8 Content-Language: en-US Content-Transfer-Encoding: 8bit Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org On 17/07/2020 09:50, Anup Patel wrote: > We add a separate CLINT timer driver for Linux RISC-V M-mode (i.e. > RISC-V NoMMU kernel). > > The CLINT MMIO device provides three things: > 1. 64bit free running counter register > 2. 64bit per-CPU time compare registers > 3. 32bit per-CPU inter-processor interrupt registers > > Unlike other timer devices, CLINT provides IPI registers along with > timer registers. To use CLINT IPI registers, the CLINT timer driver > provides IPI related callbacks to arch/riscv. > > Signed-off-by: Anup Patel > Tested-by: Emil Renner Berhing > --- > drivers/clocksource/Kconfig | 9 ++ > drivers/clocksource/Makefile | 1 + > drivers/clocksource/timer-clint.c | 231 ++++++++++++++++++++++++++++++ > include/linux/cpuhotplug.h | 1 + > 4 files changed, 242 insertions(+) > create mode 100644 drivers/clocksource/timer-clint.c > > diff --git a/drivers/clocksource/Kconfig b/drivers/clocksource/Kconfig > index 91418381fcd4..e1ce0d510a03 100644 > --- a/drivers/clocksource/Kconfig > +++ b/drivers/clocksource/Kconfig > @@ -658,6 +658,15 @@ config RISCV_TIMER > is accessed via both the SBI and the rdcycle instruction. This is > required for all RISC-V systems. > > +config CLINT_TIMER > + bool "Timer for the RISC-V platform" > + depends on GENERIC_SCHED_CLOCK && RISCV_M_MODE > + select TIMER_PROBE > + select TIMER_OF > + help > + This option enables the CLINT timer for RISC-V systems. The CLINT > + driver is usually used for NoMMU RISC-V systems. V3 has a comment about fixing the Kconfig option. [ ... ] > +{ > + bool *registered = per_cpu_ptr(&clint_clock_event_registered, cpu); > + struct clock_event_device *ce = per_cpu_ptr(&clint_clock_event, cpu); > + > + if (!(*registered)) { > + ce->cpumask = cpumask_of(cpu); > + clockevents_config_and_register(ce, clint_timer_freq, 200, > + ULONG_MAX); > + *registered = true; > + } I was unsure about the clockevents_config_and_register() multiple calls when doing the comment. It seems like it is fine to call it several times and that is done in several places like riscv or arch_arm_timer. It is probably safe to drop the 'registered' code here, sorry for the confusion. > + enable_percpu_irq(clint_timer_irq, > + irq_get_trigger_type(clint_timer_irq)); > + return 0; > +} > + [ ... ] -- Linaro.org │ Open source software for ARM SoCs Follow Linaro: Facebook | Twitter | Blog