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[2003:f6:ef1c:c500:994e:fbde:478:1ce1]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-a8a6236d290sm111882666b.116.2024.09.05.02.46.37 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 05 Sep 2024 02:46:38 -0700 (PDT) Message-ID: <642d61b23c58d9b846e42badb2f2d97691c92144.camel@gmail.com> Subject: Re: [PATCH RFC 4/8] dt-bindings: iio: dac: add adi axi-dac bus property From: Nuno =?ISO-8859-1?Q?S=E1?= To: Conor Dooley , Angelo Dureghello Cc: Lars-Peter Clausen , Michael Hennerich , Nuno =?ISO-8859-1?Q?S=E1?= , Jonathan Cameron , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Olivier Moysan , linux-iio@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, dlechner@baylibre.com Date: Thu, 05 Sep 2024 11:50:45 +0200 In-Reply-To: <20240830-quilt-appointee-4a7947e84988@spud> References: <20240829-wip-bl-ad3552r-axi-v0-v1-0-b6da6015327a@baylibre.com> <20240829-wip-bl-ad3552r-axi-v0-v1-4-b6da6015327a@baylibre.com> <20240829-stopwatch-morality-a933abb4d688@spud> <20240830-quilt-appointee-4a7947e84988@spud> Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable User-Agent: Evolution 3.52.4 Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 On Fri, 2024-08-30 at 16:33 +0100, Conor Dooley wrote: > On Fri, Aug 30, 2024 at 10:19:49AM +0200, Angelo Dureghello wrote: > > Hi Conor, > >=20 > > On 29/08/24 5:46 PM, Conor Dooley wrote: > > > On Thu, Aug 29, 2024 at 02:32:02PM +0200, Angelo Dureghello wrote: > > > > From: Angelo Dureghello > > > >=20 > > > > Add bus property. > > > RFC it may be, but you do need to explain what this bus-type actually > > > describes for commenting on the suitability of the method to be > > > meaningful. > >=20 > > thanks for the feedbacks, > >=20 > > a "bus" is intended as a generic interface connected to the target, > > may be used from a custom IP (fpga) to communicate with the target > > device (by read/write(reg and value)) using a special custom interface. > >=20 > > The bus could also be physically the same of some well-known existing > > interfaces (as parallel, lvds or other uncommon interfaces), but using > > an uncommon/custom protocol over it. > >=20 > > In concrete, actually bus-type is added to the backend since the > > ad3552r DAC chip can be connected (for maximum speed) by a 5 lanes DDR > > parallel bus (interface that i named QSPI, but it's not exactly a QSPI > > as a protocol), so it's a device-specific interface. > >=20 > > With additions in this patchset, other frontends, of course not only > > DACs, will be able to add specific busses and read/wrtie to the bus > > as needed. > >=20 > > > > Signed-off-by: Angelo Dureghello > > > > --- > > > > =C2=A0 Documentation/devicetree/bindings/iio/dac/adi,axi-dac.yaml |= 9 > > > > +++++++++ > > > > =C2=A0 1 file changed, 9 insertions(+) > > > >=20 > > > > diff --git a/Documentation/devicetree/bindings/iio/dac/adi,axi-dac.= yaml > > > > b/Documentation/devicetree/bindings/iio/dac/adi,axi-dac.yaml > > > > index a55e9bfc66d7..a7ce72e1cd81 100644 > > > > --- a/Documentation/devicetree/bindings/iio/dac/adi,axi-dac.yaml > > > > +++ b/Documentation/devicetree/bindings/iio/dac/adi,axi-dac.yaml > > > > @@ -38,6 +38,15 @@ properties: > > > > =C2=A0=C2=A0=C2=A0 clocks: > > > > =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 maxItems: 1 > > > You mentioned about new compatible strings, does the one currently > > > listed in this binding support both bus types? >=20 > You didn't answer this, and there's insufficient explanation of the > "hardware" in this RFC, but I found this which is supposedly the > backend: > https://github.com/analogdevicesinc/hdl/tree/main/library/axi_ad3552r > adi,axi-dac.yaml has a single compatible, and that compatible has > nothing to do with "axi_ad3552r" as it is "adi,axi-dac-9.1.b". I would > expect either justification for reuse of the compatible, or a brand new > compatible for this backend, even if the driver can mostly be reused. >=20 Hi Conor, So most of these designs have some changes (even if minimal) in the registe= r map and the idea (mine actually) with this backend stuff was to keep the backen= d driver (axi-dac/adc) with the generic compatible since all the (different) functionality is basically defined by the frontend they connect too and tha= t functionality is modeled by IIO backend ops. For some more significant/fundamental differences in the IP like this bus controller kind= of thing, we would add have proper FW properties. The main idea was kind of us= ing the frontend + generic backend combo so no need for new compatibles for eve= ry new design. It's still early days (at least upstream) for these IP cores and the backen= d code so if you say that we should have new compatibles for every new design= that has some differences in the register map (even if minimal), I'm of course f= ine with it. I've done it like this because I was (am) kind of afraid for thing= s to get complicated fairly quickly both in the bindings and driver (well maybe = not in the driver). OTOH, it can simplify things a lot as it's way easier to identify different implementations of the IP directly in the driver so we h= ave way more flexibility. > Could you please link to whatever ADI wiki has detailed information on > how this stuff works so that I can look at it to better understand the > axes of configuration here? >=20 > > >=20 > > > Making the bus type decision based on compatible only really makes se= nse > > > if they're different versions of the IP, but not if they're different > > > configuration options for a given version. > > >=20 > > > > +=C2=A0 bus-type: > >=20 > > DAC IP on fpga actually respects same structure and register set, excep= t > > for a named "custom" register that may use specific bitfields depending > > on the application of the IP. >=20 > To paraphrase: > "The register map is the same, except for the bit that is different". > If ADI is shipping several different configurations of this IP for > different DACs, I'd be expecting different compatibles for each backend > to be honest. Yes, pretty much we have a generic core with most of the designs being base= d on it but with some slight differences. At least for the new ones, almost all = of them have slight deviations from the generic/base core. > If each DAC specific backend was to have a unique compatible, would the > type of bus used be determinable from it? Doesn't have to work for all > devices from now until the heath death of the universe, but at least for > the devices that you're currently aware of? >=20 My original idea was to have a bus controller boolean for this core at leas= t for now that we only have one bus type (so we could assume qspi in the driver).= If the time comes we need to add support for something else, then we would nee= d another property to identify the type. > > > If, as you mentioned, there are multiple bus types, a non-flag proper= ty > > > does make sense. However, I am really not keen on these "forced" nume= rical > > > properties at all, I'd much rather see strings used here. >=20 > > > > +=C2=A0=C2=A0=C2=A0 maxItems: 1 > > > > +=C2=A0=C2=A0=C2=A0 description: | > > > > +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 Configure bus type: > > > > +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 - 0: none > > > > +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 - 1: qspi >=20 > Also, re-reading the cover letter, it says "this platform driver uses a 4 > lanes parallel bus, plus a clock line, similar to a qspi." > I don't think we should call this "qspi" if it is not actually qspi, > that's just confusing. >=20 Just by looking at the datasheet it feels like typical qspi to be honest. A= nd, fwiw, even if not really qspi, this is how the datasheet names the interfac= e. - Nuno S=C3=A1 > >=20