[PATCH 00/13] Several fixes and supports for MediaTek MT8188 SoC

[PATCH 00/13] Several fixes and supports for MediaTek MT8188 SoC

[Fei Shao]

Hi all,

This series contains several fixes and patches to the MediaTek MT8188
SoC.
It aims to add more fundamental supports and lay the groundwork for
introducing MT8188-based boards in the future:
- Supports for CPUFreq, SPMI, IOMMU, PWM and audio.
- Fixes for CPU big core clusters, missing dma-ranges in soc node and
  power-off sequence issue in vcodec pipeline.
- MT8188 CHECK_DTBS fixes for dt-bindings and device tree.

Note that there are more changes for MT8188 SoC on the way - PCIe, MIPI
DSI panel, DRM, multimedia encoders and decoders etc. I'll keep working
on organizing those changes, and I believe the feedback here will also
help me improve those before posting. Thanks!

Regards,
Fei


Fei Shao (13):
  arm64: dts: mediatek: mt8188: Add CPU performance controller for
    CPUFreq
  arm64: dts: mediatek: mt8188: Specify CPU big core cluster
  arm64: dts: mediatek: mt8188: Add missing dma-ranges to soc node
  arm64: dts: mediatek: mt8188: Move vdec1 power domain under vdec0
  arm64: dts: mediatek: mt8188: Add missing GCE clock names
  arm64: dts: mediatek: mt8188: Update VPPSYS node name and compatible
  dt-bindings: power: mediatek: Add another nested power-domain layer
  arm64: dts: mediatek: mt8188: Add SMI/LARB/IOMMU support
  arm64: dts: mediatek: mt8188: Add PWM nodes for display backlight
  dt-bindings: spmi: spmi-mtk-pmif: Add compatible for MT8188
  arm64: dts: mediatek: mt8188: Add SPMI support for PMIC control
  dt-bindings: mailbox: mtk,adsp-mbox: Add compatible for MT8188
  arm64: dts: mediatek: mt8188: Add audio support

 .../bindings/mailbox/mtk,adsp-mbox.yaml       |  12 +-
 .../power/mediatek,power-controller.yaml      |   4 +
 .../bindings/spmi/mtk,spmi-mtk-pmif.yaml      |   1 +
 arch/arm64/boot/dts/mediatek/mt8188.dtsi      | 352 +++++++++++++++++-
 4 files changed, 350 insertions(+), 19 deletions(-)

-- 
2.46.0.469.g59c65b2a67-goog

[PATCH 01/13] arm64: dts: mediatek: mt8188: Add CPU performance controller for CPUFreq

[Fei Shao]

Add performance controller node and performance-domains properties for
CPUFreq support on MT8188 SoC.

Signed-off-by: Fei Shao <fshao@chromium.org>
---

 arch/arm64/boot/dts/mediatek/mt8188.dtsi | 14 ++++++++++++++
 1 file changed, 14 insertions(+)

diff --git a/arch/arm64/boot/dts/mediatek/mt8188.dtsi b/arch/arm64/boot/dts/mediatek/mt8188.dtsi
index cd27966d2e3c..cdd2fe14effa 100644
--- a/arch/arm64/boot/dts/mediatek/mt8188.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8188.dtsi
@@ -41,6 +41,7 @@ cpu0: cpu@0 {
 			d-cache-line-size = <64>;
 			d-cache-sets = <128>;
 			next-level-cache = <&l2_0>;
+			performance-domains = <&performance 0>;
 			#cooling-cells = <2>;
 		};
 
@@ -59,6 +60,7 @@ cpu1: cpu@100 {
 			d-cache-line-size = <64>;
 			d-cache-sets = <128>;
 			next-level-cache = <&l2_0>;
+			performance-domains = <&performance 0>;
 			#cooling-cells = <2>;
 		};
 
@@ -77,6 +79,7 @@ cpu2: cpu@200 {
 			d-cache-line-size = <64>;
 			d-cache-sets = <128>;
 			next-level-cache = <&l2_0>;
+			performance-domains = <&performance 0>;
 			#cooling-cells = <2>;
 		};
 
@@ -95,6 +98,7 @@ cpu3: cpu@300 {
 			d-cache-line-size = <64>;
 			d-cache-sets = <128>;
 			next-level-cache = <&l2_0>;
+			performance-domains = <&performance 0>;
 			#cooling-cells = <2>;
 		};
 
@@ -113,6 +117,7 @@ cpu4: cpu@400 {
 			d-cache-line-size = <64>;
 			d-cache-sets = <128>;
 			next-level-cache = <&l2_0>;
+			performance-domains = <&performance 0>;
 			#cooling-cells = <2>;
 		};
 
@@ -131,6 +136,7 @@ cpu5: cpu@500 {
 			d-cache-line-size = <64>;
 			d-cache-sets = <128>;
 			next-level-cache = <&l2_0>;
+			performance-domains = <&performance 0>;
 			#cooling-cells = <2>;
 		};
 
@@ -149,6 +155,7 @@ cpu6: cpu@600 {
 			d-cache-line-size = <64>;
 			d-cache-sets = <256>;
 			next-level-cache = <&l2_1>;
+			performance-domains = <&performance 1>;
 			#cooling-cells = <2>;
 		};
 
@@ -167,6 +174,7 @@ cpu7: cpu@700 {
 			d-cache-line-size = <64>;
 			d-cache-sets = <256>;
 			next-level-cache = <&l2_1>;
+			performance-domains = <&performance 1>;
 			#cooling-cells = <2>;
 		};
 
@@ -880,6 +888,12 @@ soc {
 		compatible = "simple-bus";
 		ranges;
 
+		performance: performance-controller@11bc10 {
+			compatible = "mediatek,cpufreq-hw";
+			reg = <0 0x0011bc10 0 0x120>, <0 0x0011bd30 0 0x120>;
+			#performance-domain-cells = <1>;
+		};
+
 		gic: interrupt-controller@c000000 {
 			compatible = "arm,gic-v3";
 			#interrupt-cells = <4>;
-- 
2.46.0.469.g59c65b2a67-goog

Re: [PATCH 01/13] arm64: dts: mediatek: mt8188: Add CPU performance controller for CPUFreq

[Krzysztof Kozlowski]

On 09/09/2024 13:14, Fei Shao wrote:
> Add performance controller node and performance-domains properties for
> CPUFreq support on MT8188 SoC.
> 
> Signed-off-by: Fei Shao <fshao@chromium.org>
> ---

Order of these patches is not helping. You mix new features with fixes
and bindings.

Please split fixes from the rest. Bindings are expected to be first in
the series.

Best regards,
Krzysztof

Re: [PATCH 01/13] arm64: dts: mediatek: mt8188: Add CPU performance controller for CPUFreq

[Fei Shao]

On Mon, Sep 9, 2024 at 7:42 PM Krzysztof Kozlowski <krzk@kernel.org> wrote:
>
> On 09/09/2024 13:14, Fei Shao wrote:
> > Add performance controller node and performance-domains properties for
> > CPUFreq support on MT8188 SoC.
> >
> > Signed-off-by: Fei Shao <fshao@chromium.org>
> > ---
>
> Order of these patches is not helping. You mix new features with fixes
> and bindings.
>
> Please split fixes from the rest. Bindings are expected to be first in
> the series.

Understood. I'll resend the fixes and features in separate series, and
group the binding changes in the beginning.
Thanks for the feedback.

Regards,
Fei

>
> Best regards,
> Krzysztof
>

[PATCH 02/13] arm64: dts: mediatek: mt8188: Specify CPU big core cluster

[Fei Shao]

The MT8188 SoC features two CPU clusters: one with 6 little A55 cores,
and the other with 2 big A78 cores.

Update the CPU topology to reflect the actual hardware configurations.

Signed-off-by: Fei Shao <fshao@chromium.org>
---

 arch/arm64/boot/dts/mediatek/mt8188.dtsi | 6 ++++--
 1 file changed, 4 insertions(+), 2 deletions(-)

diff --git a/arch/arm64/boot/dts/mediatek/mt8188.dtsi b/arch/arm64/boot/dts/mediatek/mt8188.dtsi
index cdd2fe14effa..788dfb5484bd 100644
--- a/arch/arm64/boot/dts/mediatek/mt8188.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8188.dtsi
@@ -203,12 +203,14 @@ core4 {
 				core5 {
 					cpu = <&cpu5>;
 				};
+			};
 
-				core6 {
+			cluster1 {
+				core0 {
 					cpu = <&cpu6>;
 				};
 
-				core7 {
+				core1 {
 					cpu = <&cpu7>;
 				};
 			};
-- 
2.46.0.469.g59c65b2a67-goog

[PATCH 03/13] arm64: dts: mediatek: mt8188: Add missing dma-ranges to soc node

[Fei Shao]

Add the missing dma-ranges property to the soc node, similar to how it
was done for MT8195 and MT8192.

This allows the entire 16GB of iova range to be used and enables
multimedia processing usages, like vcodec and MIPI camera.

Signed-off-by: Fei Shao <fshao@chromium.org>
---

 arch/arm64/boot/dts/mediatek/mt8188.dtsi | 1 +
 1 file changed, 1 insertion(+)

diff --git a/arch/arm64/boot/dts/mediatek/mt8188.dtsi b/arch/arm64/boot/dts/mediatek/mt8188.dtsi
index 788dfb5484bd..dfbc50c878c4 100644
--- a/arch/arm64/boot/dts/mediatek/mt8188.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8188.dtsi
@@ -888,6 +888,7 @@ soc {
 		#address-cells = <2>;
 		#size-cells = <2>;
 		compatible = "simple-bus";
+		dma-ranges = <0x0 0x0 0x0 0x0 0x4 0x0>;
 		ranges;
 
 		performance: performance-controller@11bc10 {
-- 
2.46.0.469.g59c65b2a67-goog

[PATCH 04/13] arm64: dts: mediatek: mt8188: Move vdec1 power domain under vdec0

[Fei Shao]

There are two hardware IP blocks in MT8188 video decoder pipeline:
vdec-lat and vdec-core, which are powered by vdec0 and vdec1 power
domains respectively.

We noticed that vdec-core needs to be powered down before vdec-lat
during suspend to prevent failures. It's unclear if it's an intended
hardware design or due to power isolation glitch. But in any case, we
observed a power-off sequence here, and it can be considered as an
indirect dependency implication between the vdec0 and vdec1 domains.

Given that, update vdec1 as a sub-domain of vdec0 to enforce the
sequence. Also, use more specific clock names for both power domains.

Signed-off-by: Fei Shao <fshao@chromium.org>
---

 arch/arm64/boot/dts/mediatek/mt8188.dtsi | 22 ++++++++++++----------
 1 file changed, 12 insertions(+), 10 deletions(-)

diff --git a/arch/arm64/boot/dts/mediatek/mt8188.dtsi b/arch/arm64/boot/dts/mediatek/mt8188.dtsi
index dfbc50c878c4..445d30eee2a1 100644
--- a/arch/arm64/boot/dts/mediatek/mt8188.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8188.dtsi
@@ -1078,20 +1078,22 @@ power-domain@MT8188_POWER_DOMAIN_VPPSYS1 {
 							#power-domain-cells = <0>;
 						};
 
-						power-domain@MT8188_POWER_DOMAIN_VDEC1 {
-							reg = <MT8188_POWER_DOMAIN_VDEC1>;
-							clocks = <&vdecsys CLK_VDEC2_LARB1>;
-							clock-names = "ss-vdec";
-							mediatek,infracfg = <&infracfg_ao>;
-							#power-domain-cells = <0>;
-						};
-
 						power-domain@MT8188_POWER_DOMAIN_VDEC0 {
 							reg = <MT8188_POWER_DOMAIN_VDEC0>;
 							clocks = <&vdecsys_soc CLK_VDEC1_SOC_LARB1>;
-							clock-names = "ss-vdec";
+							clock-names = "ss-vdec1-soc-l1";
 							mediatek,infracfg = <&infracfg_ao>;
-							#power-domain-cells = <0>;
+							#address-cells = <1>;
+							#size-cells = <0>;
+							#power-domain-cells = <1>;
+
+							power-domain@MT8188_POWER_DOMAIN_VDEC1 {
+								reg = <MT8188_POWER_DOMAIN_VDEC1>;
+								clocks = <&vdecsys CLK_VDEC2_LARB1>;
+								clock-names = "ss-vdec2-l1";
+								mediatek,infracfg = <&infracfg_ao>;
+								#power-domain-cells = <0>;
+							};
 						};
 
 						cam_vcore: power-domain@MT8188_POWER_DOMAIN_CAM_VCORE {
-- 
2.46.0.469.g59c65b2a67-goog

[PATCH 05/13] arm64: dts: mediatek: mt8188: Add missing GCE clock names

[Fei Shao]

Add the missing clock-names property for GCE nodes to fix errors from
`make CHECK_DTBS=y mediatek/mt8188-evb.dtb`.

Signed-off-by: Fei Shao <fshao@chromium.org>
---

 arch/arm64/boot/dts/mediatek/mt8188.dtsi | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/arch/arm64/boot/dts/mediatek/mt8188.dtsi b/arch/arm64/boot/dts/mediatek/mt8188.dtsi
index 445d30eee2a1..2900d78b7ceb 100644
--- a/arch/arm64/boot/dts/mediatek/mt8188.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8188.dtsi
@@ -1316,6 +1316,7 @@ gce0: mailbox@10320000 {
 			interrupts = <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH 0>;
 			#mbox-cells = <2>;
 			clocks = <&infracfg_ao CLK_INFRA_AO_GCE>;
+			clock-names = "gce";
 		};
 
 		gce1: mailbox@10330000 {
@@ -1324,6 +1325,7 @@ gce1: mailbox@10330000 {
 			interrupts = <GIC_SPI 228 IRQ_TYPE_LEVEL_HIGH 0>;
 			#mbox-cells = <2>;
 			clocks = <&infracfg_ao CLK_INFRA_AO_GCE2>;
+			clock-names = "gce";
 		};
 
 		scp: scp@10500000 {
-- 
2.46.0.469.g59c65b2a67-goog

Re: [PATCH 05/13] arm64: dts: mediatek: mt8188: Add missing GCE clock names

[AngeloGioacchino Del Regno]

Il 09/09/24 13:14, Fei Shao ha scritto:
> Add the missing clock-names property for GCE nodes to fix errors from
> `make CHECK_DTBS=y mediatek/mt8188-evb.dtb`.

I've sent a patch [1] relaxing the requirement for clock-names in the binding.
There's no reason to make clock-names mandatory, as there is and there always
will be one single clock for each GCE mailbox - and also the driver is not
trying to get the clock by name, but rather gets the clock at index 0 anyway.

Please drop this patch.

Cheers,
Angelo

[1]: 
https://lore.kernel.org/all/20240911104327.123602-1-angelogioacchino.delregno@collabora.com/

> 
> Signed-off-by: Fei Shao <fshao@chromium.org>
> ---
> 
>   arch/arm64/boot/dts/mediatek/mt8188.dtsi | 2 ++
>   1 file changed, 2 insertions(+)
> 
> diff --git a/arch/arm64/boot/dts/mediatek/mt8188.dtsi b/arch/arm64/boot/dts/mediatek/mt8188.dtsi
> index 445d30eee2a1..2900d78b7ceb 100644
> --- a/arch/arm64/boot/dts/mediatek/mt8188.dtsi
> +++ b/arch/arm64/boot/dts/mediatek/mt8188.dtsi
> @@ -1316,6 +1316,7 @@ gce0: mailbox@10320000 {
>   			interrupts = <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH 0>;
>   			#mbox-cells = <2>;
>   			clocks = <&infracfg_ao CLK_INFRA_AO_GCE>;
> +			clock-names = "gce";
>   		};
>   
>   		gce1: mailbox@10330000 {
> @@ -1324,6 +1325,7 @@ gce1: mailbox@10330000 {
>   			interrupts = <GIC_SPI 228 IRQ_TYPE_LEVEL_HIGH 0>;
>   			#mbox-cells = <2>;
>   			clocks = <&infracfg_ao CLK_INFRA_AO_GCE2>;
> +			clock-names = "gce";
>   		};
>   
>   		scp: scp@10500000 {

Re: [PATCH 05/13] arm64: dts: mediatek: mt8188: Add missing GCE clock names

[Fei Shao]

On Wed, Sep 11, 2024 at 6:46 PM AngeloGioacchino Del Regno
<angelogioacchino.delregno@collabora.com> wrote:
>
> Il 09/09/24 13:14, Fei Shao ha scritto:
> > Add the missing clock-names property for GCE nodes to fix errors from
> > `make CHECK_DTBS=y mediatek/mt8188-evb.dtb`.
>
> I've sent a patch [1] relaxing the requirement for clock-names in the binding.
> There's no reason to make clock-names mandatory, as there is and there always
> will be one single clock for each GCE mailbox - and also the driver is not
> trying to get the clock by name, but rather gets the clock at index 0 anyway.
>
> Please drop this patch.

Acknowledged. I'll drop this in the next revision.

Thanks,
Fei

[PATCH 06/13] arm64: dts: mediatek: mt8188: Update VPPSYS node name and compatible

[Fei Shao]

Use and add "syscon" in VPPSYS node names and compatible to fix errors
from `make CHECK_DTBS=y mediatek/mt8188-evb.dtb`.

Signed-off-by: Fei Shao <fshao@chromium.org>
---

 arch/arm64/boot/dts/mediatek/mt8188.dtsi | 8 ++++----
 1 file changed, 4 insertions(+), 4 deletions(-)

diff --git a/arch/arm64/boot/dts/mediatek/mt8188.dtsi b/arch/arm64/boot/dts/mediatek/mt8188.dtsi
index 2900d78b7ceb..14e51a11f688 100644
--- a/arch/arm64/boot/dts/mediatek/mt8188.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8188.dtsi
@@ -1799,8 +1799,8 @@ mfgcfg: clock-controller@13fbf000 {
 			#clock-cells = <1>;
 		};
 
-		vppsys0: clock-controller@14000000 {
-			compatible = "mediatek,mt8188-vppsys0";
+		vppsys0: syscon@14000000 {
+			compatible = "mediatek,mt8188-vppsys0", "syscon";
 			reg = <0 0x14000000 0 0x1000>;
 			#clock-cells = <1>;
 		};
@@ -1817,8 +1817,8 @@ wpesys_vpp0: clock-controller@14e02000 {
 			#clock-cells = <1>;
 		};
 
-		vppsys1: clock-controller@14f00000 {
-			compatible = "mediatek,mt8188-vppsys1";
+		vppsys1: syscon@14f00000 {
+			compatible = "mediatek,mt8188-vppsys1", "syscon";
 			reg = <0 0x14f00000 0 0x1000>;
 			#clock-cells = <1>;
 		};
-- 
2.46.0.469.g59c65b2a67-goog

Re: [PATCH 06/13] arm64: dts: mediatek: mt8188: Update VPPSYS node name and compatible

[Krzysztof Kozlowski]

On 09/09/2024 13:14, Fei Shao wrote:
> Use and add "syscon" in VPPSYS node names and compatible to fix errors
> from `make CHECK_DTBS=y mediatek/mt8188-evb.dtb`.
> 
> Signed-off-by: Fei Shao <fshao@chromium.org>
> ---
> 
>  arch/arm64/boot/dts/mediatek/mt8188.dtsi | 8 ++++----
>  1 file changed, 4 insertions(+), 4 deletions(-)
> 
> diff --git a/arch/arm64/boot/dts/mediatek/mt8188.dtsi b/arch/arm64/boot/dts/mediatek/mt8188.dtsi
> index 2900d78b7ceb..14e51a11f688 100644
> --- a/arch/arm64/boot/dts/mediatek/mt8188.dtsi
> +++ b/arch/arm64/boot/dts/mediatek/mt8188.dtsi
> @@ -1799,8 +1799,8 @@ mfgcfg: clock-controller@13fbf000 {
>  			#clock-cells = <1>;
>  		};
>  
> -		vppsys0: clock-controller@14000000 {
> -			compatible = "mediatek,mt8188-vppsys0";
> +		vppsys0: syscon@14000000 {
> +			compatible = "mediatek,mt8188-vppsys0", "syscon";

If this was working before, it looks like this is not a syscon and
bindings need to be fixed.

Best regards,
Krzysztof

Re: [PATCH 06/13] arm64: dts: mediatek: mt8188: Update VPPSYS node name and compatible

[Fei Shao]

On Mon, Sep 9, 2024 at 7:41 PM Krzysztof Kozlowski <krzk@kernel.org> wrote:
>
> On 09/09/2024 13:14, Fei Shao wrote:
> > Use and add "syscon" in VPPSYS node names and compatible to fix errors
> > from `make CHECK_DTBS=y mediatek/mt8188-evb.dtb`.
> >
> > Signed-off-by: Fei Shao <fshao@chromium.org>
> > ---
> >
> >  arch/arm64/boot/dts/mediatek/mt8188.dtsi | 8 ++++----
> >  1 file changed, 4 insertions(+), 4 deletions(-)
> >
> > diff --git a/arch/arm64/boot/dts/mediatek/mt8188.dtsi b/arch/arm64/boot/dts/mediatek/mt8188.dtsi
> > index 2900d78b7ceb..14e51a11f688 100644
> > --- a/arch/arm64/boot/dts/mediatek/mt8188.dtsi
> > +++ b/arch/arm64/boot/dts/mediatek/mt8188.dtsi
> > @@ -1799,8 +1799,8 @@ mfgcfg: clock-controller@13fbf000 {
> >                       #clock-cells = <1>;
> >               };
> >
> > -             vppsys0: clock-controller@14000000 {
> > -                     compatible = "mediatek,mt8188-vppsys0";
> > +             vppsys0: syscon@14000000 {
> > +                     compatible = "mediatek,mt8188-vppsys0", "syscon";
>
> If this was working before, it looks like this is not a syscon and
> bindings need to be fixed.

I guess it's because the binding was later updated in commit
26bcd8a53098 ("dt-bindings: arm: mediatek: mmsys: Add VPPSYS
compatible for MT8188"), and the corresponding DT update was unnoticed
at the time.
If that makes sense then this should be a valid fix.

Regards,
Fei

>
> Best regards,
> Krzysztof
>

Re: [PATCH 06/13] arm64: dts: mediatek: mt8188: Update VPPSYS node name and compatible

[Krzysztof Kozlowski]

On 10/09/2024 07:12, Fei Shao wrote:
> On Mon, Sep 9, 2024 at 7:41 PM Krzysztof Kozlowski <krzk@kernel.org> wrote:
>>
>> On 09/09/2024 13:14, Fei Shao wrote:
>>> Use and add "syscon" in VPPSYS node names and compatible to fix errors
>>> from `make CHECK_DTBS=y mediatek/mt8188-evb.dtb`.
>>>
>>> Signed-off-by: Fei Shao <fshao@chromium.org>
>>> ---
>>>
>>>  arch/arm64/boot/dts/mediatek/mt8188.dtsi | 8 ++++----
>>>  1 file changed, 4 insertions(+), 4 deletions(-)
>>>
>>> diff --git a/arch/arm64/boot/dts/mediatek/mt8188.dtsi b/arch/arm64/boot/dts/mediatek/mt8188.dtsi
>>> index 2900d78b7ceb..14e51a11f688 100644
>>> --- a/arch/arm64/boot/dts/mediatek/mt8188.dtsi
>>> +++ b/arch/arm64/boot/dts/mediatek/mt8188.dtsi
>>> @@ -1799,8 +1799,8 @@ mfgcfg: clock-controller@13fbf000 {
>>>                       #clock-cells = <1>;
>>>               };
>>>
>>> -             vppsys0: clock-controller@14000000 {
>>> -                     compatible = "mediatek,mt8188-vppsys0";
>>> +             vppsys0: syscon@14000000 {
>>> +                     compatible = "mediatek,mt8188-vppsys0", "syscon";
>>
>> If this was working before, it looks like this is not a syscon and
>> bindings need to be fixed.
> 
> I guess it's because the binding was later updated in commit
> 26bcd8a53098 ("dt-bindings: arm: mediatek: mmsys: Add VPPSYS
> compatible for MT8188"), and the corresponding DT update was unnoticed
> at the time.
> If that makes sense then this should be a valid fix.

Not necessarily. Why not fixing bindings? Prove that bindings are
correct, not DTS, first.

Best regards,
Krzysztof

Re: [PATCH 06/13] arm64: dts: mediatek: mt8188: Update VPPSYS node name and compatible

[Fei Shao]

On Tue, Sep 10, 2024 at 3:19 PM Krzysztof Kozlowski <krzk@kernel.org> wrote:
>
> On 10/09/2024 07:12, Fei Shao wrote:
> > On Mon, Sep 9, 2024 at 7:41 PM Krzysztof Kozlowski <krzk@kernel.org> wrote:
> >>
> >> On 09/09/2024 13:14, Fei Shao wrote:
> >>> Use and add "syscon" in VPPSYS node names and compatible to fix errors
> >>> from `make CHECK_DTBS=y mediatek/mt8188-evb.dtb`.
> >>>
> >>> Signed-off-by: Fei Shao <fshao@chromium.org>
> >>> ---
> >>>
> >>>  arch/arm64/boot/dts/mediatek/mt8188.dtsi | 8 ++++----
> >>>  1 file changed, 4 insertions(+), 4 deletions(-)
> >>>
> >>> diff --git a/arch/arm64/boot/dts/mediatek/mt8188.dtsi b/arch/arm64/boot/dts/mediatek/mt8188.dtsi
> >>> index 2900d78b7ceb..14e51a11f688 100644
> >>> --- a/arch/arm64/boot/dts/mediatek/mt8188.dtsi
> >>> +++ b/arch/arm64/boot/dts/mediatek/mt8188.dtsi
> >>> @@ -1799,8 +1799,8 @@ mfgcfg: clock-controller@13fbf000 {
> >>>                       #clock-cells = <1>;
> >>>               };
> >>>
> >>> -             vppsys0: clock-controller@14000000 {
> >>> -                     compatible = "mediatek,mt8188-vppsys0";
> >>> +             vppsys0: syscon@14000000 {
> >>> +                     compatible = "mediatek,mt8188-vppsys0", "syscon";
> >>
> >> If this was working before, it looks like this is not a syscon and
> >> bindings need to be fixed.
> >
> > I guess it's because the binding was later updated in commit
> > 26bcd8a53098 ("dt-bindings: arm: mediatek: mmsys: Add VPPSYS
> > compatible for MT8188"), and the corresponding DT update was unnoticed
> > at the time.
> > If that makes sense then this should be a valid fix.
>
> Not necessarily. Why not fixing bindings? Prove that bindings are
> correct, not DTS, first.

MediaTek's mmsys doesn't merely control clocks, it also provides
display pipeline routing control and other misc control registers, so
it's appropriate to categorize it as a system controller over a clock
controller.
As for vdosys and vppsys, they are likely variants or aliases of mmsys
introduced in their newer SoCs.

That description was updated in commit 1a680aa888d6 ("dt-bindings:
mediatek: Update mmsys binding to reflect it is a system controller"),
so I just assumed it's correct without thinking much...

Regards,
Fei

Re: [PATCH 06/13] arm64: dts: mediatek: mt8188: Update VPPSYS node name and compatible

[Krzysztof Kozlowski]

On 10/09/2024 13:06, Fei Shao wrote:
> On Tue, Sep 10, 2024 at 3:19 PM Krzysztof Kozlowski <krzk@kernel.org> wrote:
>>
>> On 10/09/2024 07:12, Fei Shao wrote:
>>> On Mon, Sep 9, 2024 at 7:41 PM Krzysztof Kozlowski <krzk@kernel.org> wrote:
>>>>
>>>> On 09/09/2024 13:14, Fei Shao wrote:
>>>>> Use and add "syscon" in VPPSYS node names and compatible to fix errors
>>>>> from `make CHECK_DTBS=y mediatek/mt8188-evb.dtb`.
>>>>>
>>>>> Signed-off-by: Fei Shao <fshao@chromium.org>
>>>>> ---
>>>>>
>>>>>  arch/arm64/boot/dts/mediatek/mt8188.dtsi | 8 ++++----
>>>>>  1 file changed, 4 insertions(+), 4 deletions(-)
>>>>>
>>>>> diff --git a/arch/arm64/boot/dts/mediatek/mt8188.dtsi b/arch/arm64/boot/dts/mediatek/mt8188.dtsi
>>>>> index 2900d78b7ceb..14e51a11f688 100644
>>>>> --- a/arch/arm64/boot/dts/mediatek/mt8188.dtsi
>>>>> +++ b/arch/arm64/boot/dts/mediatek/mt8188.dtsi
>>>>> @@ -1799,8 +1799,8 @@ mfgcfg: clock-controller@13fbf000 {
>>>>>                       #clock-cells = <1>;
>>>>>               };
>>>>>
>>>>> -             vppsys0: clock-controller@14000000 {
>>>>> -                     compatible = "mediatek,mt8188-vppsys0";
>>>>> +             vppsys0: syscon@14000000 {
>>>>> +                     compatible = "mediatek,mt8188-vppsys0", "syscon";
>>>>
>>>> If this was working before, it looks like this is not a syscon and
>>>> bindings need to be fixed.
>>>
>>> I guess it's because the binding was later updated in commit
>>> 26bcd8a53098 ("dt-bindings: arm: mediatek: mmsys: Add VPPSYS
>>> compatible for MT8188"), and the corresponding DT update was unnoticed
>>> at the time.
>>> If that makes sense then this should be a valid fix.
>>
>> Not necessarily. Why not fixing bindings? Prove that bindings are
>> correct, not DTS, first.
> 
> MediaTek's mmsys doesn't merely control clocks, it also provides
> display pipeline routing control and other misc control registers, so
> it's appropriate to categorize it as a system controller over a clock
> controller.
> As for vdosys and vppsys, they are likely variants or aliases of mmsys
> introduced in their newer SoCs.

Nothing like that was in the commit msg...

> 
> That description was updated in commit 1a680aa888d6 ("dt-bindings:
> mediatek: Update mmsys binding to reflect it is a system controller"),
> so I just assumed it's correct without thinking much...


Best regards,
Krzysztof

Re: [PATCH 06/13] arm64: dts: mediatek: mt8188: Update VPPSYS node name and compatible

[Fei Shao]

On Mon, Sep 16, 2024 at 6:02 PM Krzysztof Kozlowski <krzk@kernel.org> wrote:
>
> On 10/09/2024 13:06, Fei Shao wrote:
> > On Tue, Sep 10, 2024 at 3:19 PM Krzysztof Kozlowski <krzk@kernel.org> wrote:
> >>
> >> On 10/09/2024 07:12, Fei Shao wrote:
> >>> On Mon, Sep 9, 2024 at 7:41 PM Krzysztof Kozlowski <krzk@kernel.org> wrote:
> >>>>
> >>>> On 09/09/2024 13:14, Fei Shao wrote:
> >>>>> Use and add "syscon" in VPPSYS node names and compatible to fix errors
> >>>>> from `make CHECK_DTBS=y mediatek/mt8188-evb.dtb`.
> >>>>>
> >>>>> Signed-off-by: Fei Shao <fshao@chromium.org>
> >>>>> ---
> >>>>>
> >>>>>  arch/arm64/boot/dts/mediatek/mt8188.dtsi | 8 ++++----
> >>>>>  1 file changed, 4 insertions(+), 4 deletions(-)
> >>>>>
> >>>>> diff --git a/arch/arm64/boot/dts/mediatek/mt8188.dtsi b/arch/arm64/boot/dts/mediatek/mt8188.dtsi
> >>>>> index 2900d78b7ceb..14e51a11f688 100644
> >>>>> --- a/arch/arm64/boot/dts/mediatek/mt8188.dtsi
> >>>>> +++ b/arch/arm64/boot/dts/mediatek/mt8188.dtsi
> >>>>> @@ -1799,8 +1799,8 @@ mfgcfg: clock-controller@13fbf000 {
> >>>>>                       #clock-cells = <1>;
> >>>>>               };
> >>>>>
> >>>>> -             vppsys0: clock-controller@14000000 {
> >>>>> -                     compatible = "mediatek,mt8188-vppsys0";
> >>>>> +             vppsys0: syscon@14000000 {
> >>>>> +                     compatible = "mediatek,mt8188-vppsys0", "syscon";
> >>>>
> >>>> If this was working before, it looks like this is not a syscon and
> >>>> bindings need to be fixed.
> >>>
> >>> I guess it's because the binding was later updated in commit
> >>> 26bcd8a53098 ("dt-bindings: arm: mediatek: mmsys: Add VPPSYS
> >>> compatible for MT8188"), and the corresponding DT update was unnoticed
> >>> at the time.
> >>> If that makes sense then this should be a valid fix.
> >>
> >> Not necessarily. Why not fixing bindings? Prove that bindings are
> >> correct, not DTS, first.
> >
> > MediaTek's mmsys doesn't merely control clocks, it also provides
> > display pipeline routing control and other misc control registers, so
> > it's appropriate to categorize it as a system controller over a clock
> > controller.
> > As for vdosys and vppsys, they are likely variants or aliases of mmsys
> > introduced in their newer SoCs.
>
> Nothing like that was in the commit msg...

Just for a record, I've revised the commit message in the newer series:
https://lore.kernel.org/all/20240925110044.3678055-7-fshao@chromium.org/

Thanks,
Fei

[PATCH 07/13] dt-bindings: power: mediatek: Add another nested power-domain layer

[Fei Shao]

The MT8188 SoC has a more in-depth power-domain tree, and the
CHECK_DTBS=y check could fail because the current MediaTek power
dt-binding is insufficient to cover its CAM_SUBA and CAM_SUBB
sub-domains.

Add one more nested power-domain layer to pass the check.

Signed-off-by: Fei Shao <fshao@chromium.org>
---

 .../devicetree/bindings/power/mediatek,power-controller.yaml  | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/Documentation/devicetree/bindings/power/mediatek,power-controller.yaml b/Documentation/devicetree/bindings/power/mediatek,power-controller.yaml
index 8985e2df8a56..a7df4041b745 100644
--- a/Documentation/devicetree/bindings/power/mediatek,power-controller.yaml
+++ b/Documentation/devicetree/bindings/power/mediatek,power-controller.yaml
@@ -54,6 +54,10 @@ patternProperties:
             patternProperties:
               "^power-domain@[0-9a-f]+$":
                 $ref: "#/$defs/power-domain-node"
+                patternProperties:
+                  "^power-domain@[0-9a-f]+$":
+                    $ref: "#/$defs/power-domain-node"
+                    unevaluatedProperties: false
                 unevaluatedProperties: false
             unevaluatedProperties: false
         unevaluatedProperties: false
-- 
2.46.0.469.g59c65b2a67-goog

Re: [PATCH 07/13] dt-bindings: power: mediatek: Add another nested power-domain layer

[Rob Herring (Arm)]

On Mon, 09 Sep 2024 19:14:20 +0800, Fei Shao wrote:
> The MT8188 SoC has a more in-depth power-domain tree, and the
> CHECK_DTBS=y check could fail because the current MediaTek power
> dt-binding is insufficient to cover its CAM_SUBA and CAM_SUBB
> sub-domains.
> 
> Add one more nested power-domain layer to pass the check.
> 
> Signed-off-by: Fei Shao <fshao@chromium.org>
> ---
> 
>  .../devicetree/bindings/power/mediatek,power-controller.yaml  | 4 ++++
>  1 file changed, 4 insertions(+)
> 

Acked-by: Rob Herring (Arm) <robh@kernel.org>

[PATCH 08/13] arm64: dts: mediatek: mt8188: Add SMI/LARB/IOMMU support

[Fei Shao]

Local Arbiter (LARB) is a component of Smart Multimedia Interface (SMI)
that supports IOMMU on the MediaTek SoCs.

Add the following nodes for memory management support on MT8188 SoC:
- one Infra IOMMU
- two Multimedia (MM) IOMMUs of VDO and VPP
- corresponding SMI common and LARB nodes of the MM IOMMUs

Signed-off-by: Fei Shao <fshao@chromium.org>
---

 arch/arm64/boot/dts/mediatek/mt8188.dtsi | 169 +++++++++++++++++++++++
 1 file changed, 169 insertions(+)

diff --git a/arch/arm64/boot/dts/mediatek/mt8188.dtsi b/arch/arm64/boot/dts/mediatek/mt8188.dtsi
index 14e51a11f688..7e3a90c1a173 100644
--- a/arch/arm64/boot/dts/mediatek/mt8188.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8188.dtsi
@@ -9,6 +9,7 @@
 #include <dt-bindings/interrupt-controller/arm-gic.h>
 #include <dt-bindings/interrupt-controller/irq.h>
 #include <dt-bindings/mailbox/mediatek,mt8188-gce.h>
+#include <dt-bindings/memory/mediatek,mt8188-memory-port.h>
 #include <dt-bindings/phy/phy.h>
 #include <dt-bindings/pinctrl/mediatek,mt8188-pinfunc.h>
 #include <dt-bindings/power/mediatek,mt8188-power.h>
@@ -1310,6 +1311,13 @@ pwrap: pwrap@10024000 {
 			clock-names = "spi", "wrap";
 		};
 
+		infra_iommu: iommu@10315000 {
+			compatible = "mediatek,mt8188-iommu-infra";
+			reg = <0 0x10315000 0 0x1000>;
+			interrupts = <GIC_SPI 795 IRQ_TYPE_LEVEL_HIGH 0>;
+			#iommu-cells = <1>;
+		};
+
 		gce0: mailbox@10320000 {
 			compatible = "mediatek,mt8188-gce";
 			reg = <0 0x10320000 0 0x4000>;
@@ -1805,6 +1813,37 @@ vppsys0: syscon@14000000 {
 			#clock-cells = <1>;
 		};
 
+		vpp_smi_common: smi@14012000 {
+			compatible = "mediatek,mt8188-smi-common-vpp";
+			reg = <0 0x14012000 0 0x1000>;
+			clocks = <&vppsys0 CLK_VPP0_SMI_COMMON_LARB4>,
+				 <&vppsys0 CLK_VPP0_SMI_SUB_COMMON_REORDER>;
+			clock-names = "apb", "smi";
+			power-domains = <&spm MT8188_POWER_DOMAIN_VPPSYS0>;
+		};
+
+		larb4: smi@14013000 {
+			compatible = "mediatek,mt8188-smi-larb";
+			reg = <0 0x14013000 0 0x1000>;
+			clocks = <&vppsys0 CLK_VPP0_SMI_COMMON_LARB4>,
+				 <&vppsys0 CLK_VPP0_SMI_COMMON_LARB4>;
+			clock-names = "apb", "smi";
+			power-domains = <&spm MT8188_POWER_DOMAIN_VPPSYS0>;
+			mediatek,larb-id = <SMI_L4_ID>;
+			mediatek,smi = <&vpp_smi_common>;
+		};
+
+		vpp_iommu: iommu@14018000 {
+			compatible = "mediatek,mt8188-iommu-vpp";
+			reg = <0 0x14018000 0 0x5000>;
+			clocks = <&vppsys0 CLK_VPP0_SMI_IOMMU>;
+			clock-names = "bclk";
+			interrupts = <GIC_SPI 594 IRQ_TYPE_LEVEL_HIGH 0>;
+			power-domains = <&spm MT8188_POWER_DOMAIN_VPPSYS0>;
+			#iommu-cells = <1>;
+			mediatek,larbs = <&larb1 &larb3 &larb4 &larb6 &larb7 &larb23>;
+		};
+
 		wpesys: clock-controller@14e00000 {
 			compatible = "mediatek,mt8188-wpesys";
 			reg = <0 0x14e00000 0 0x1000>;
@@ -1817,12 +1856,45 @@ wpesys_vpp0: clock-controller@14e02000 {
 			#clock-cells = <1>;
 		};
 
+		larb7: smi@14e04000 {
+			compatible = "mediatek,mt8188-smi-larb";
+			reg = <0 0x14e04000 0 0x1000>;
+			clocks = <&wpesys CLK_WPE_TOP_SMI_LARB7>,
+				 <&wpesys CLK_WPE_TOP_SMI_LARB7>;
+			clock-names = "apb", "smi";
+			power-domains = <&spm MT8188_POWER_DOMAIN_WPE>;
+			mediatek,larb-id = <SMI_L7_ID>;
+			mediatek,smi = <&vpp_smi_common>;
+		};
+
 		vppsys1: syscon@14f00000 {
 			compatible = "mediatek,mt8188-vppsys1", "syscon";
 			reg = <0 0x14f00000 0 0x1000>;
 			#clock-cells = <1>;
 		};
 
+		larb5: smi@14f02000 {
+			compatible = "mediatek,mt8188-smi-larb";
+			reg = <0 0x14f02000 0 0x1000>;
+			clocks = <&vppsys1 CLK_VPP1_GALS5>,
+				 <&vppsys1 CLK_VPP1_LARB5>;
+			clock-names = "apb", "smi";
+			power-domains = <&spm MT8188_POWER_DOMAIN_VPPSYS1>;
+			mediatek,larb-id = <SMI_L5_ID>;
+			mediatek,smi = <&vdo_smi_common>;
+		};
+
+		larb6: smi@14f03000 {
+			compatible = "mediatek,mt8188-smi-larb";
+			reg = <0 0x14f03000 0 0x1000>;
+			clocks = <&vppsys1 CLK_VPP1_GALS6>,
+				 <&vppsys1 CLK_VPP1_LARB6>;
+			clock-names = "apb", "smi";
+			power-domains = <&spm MT8188_POWER_DOMAIN_VPPSYS1>;
+			mediatek,larb-id = <SMI_L6_ID>;
+			mediatek,smi = <&vpp_smi_common>;
+		};
+
 		imgsys: clock-controller@15000000 {
 			compatible = "mediatek,mt8188-imgsys";
 			reg = <0 0x15000000 0 0x1000>;
@@ -1901,12 +1973,34 @@ ccusys: clock-controller@17200000 {
 			#clock-cells = <1>;
 		};
 
+		larb23: smi@1800d000 {
+			compatible = "mediatek,mt8188-smi-larb";
+			reg = <0 0x1800d000 0 0x1000>;
+			clocks = <&vdecsys_soc CLK_VDEC1_SOC_LARB1>,
+				 <&vdecsys_soc CLK_VDEC1_SOC_LARB1>;
+			clock-names = "apb", "smi";
+			power-domains = <&spm MT8188_POWER_DOMAIN_VDEC0>;
+			mediatek,larb-id = <SMI_L23_ID>;
+			mediatek,smi = <&vpp_smi_common>;
+		};
+
 		vdecsys_soc: clock-controller@1800f000 {
 			compatible = "mediatek,mt8188-vdecsys-soc";
 			reg = <0 0x1800f000 0 0x1000>;
 			#clock-cells = <1>;
 		};
 
+		larb21: smi@1802e000 {
+			compatible = "mediatek,mt8188-smi-larb";
+			reg = <0 0x1802e000 0 0x1000>;
+			clocks = <&vdecsys CLK_VDEC2_LARB1>,
+				 <&vdecsys CLK_VDEC2_LARB1>;
+			clock-names = "apb", "smi";
+			power-domains = <&spm MT8188_POWER_DOMAIN_VDEC1>;
+			mediatek,larb-id = <SMI_L21_ID>;
+			mediatek,smi = <&vdo_smi_common>;
+		};
+
 		vdecsys: clock-controller@1802f000 {
 			compatible = "mediatek,mt8188-vdecsys";
 			reg = <0 0x1802f000 0 0x1000>;
@@ -1919,6 +2013,17 @@ vencsys: clock-controller@1a000000 {
 			#clock-cells = <1>;
 		};
 
+		larb19: smi@1a010000 {
+			compatible = "mediatek,mt8188-smi-larb";
+			reg = <0 0x1a010000 0 0x1000>;
+			clocks = <&vencsys CLK_VENC1_VENC>,
+				 <&vencsys CLK_VENC1_VENC>;
+			clock-names = "apb", "smi";
+			power-domains = <&spm MT8188_POWER_DOMAIN_VENC>;
+			mediatek,larb-id = <SMI_L19_ID>;
+			mediatek,smi = <&vdo_smi_common>;
+		};
+
 		vdosys0: syscon@1c01d000 {
 			compatible = "mediatek,mt8188-vdosys0", "syscon";
 			reg = <0 0x1c01d000 0 0x1000>;
@@ -1927,6 +2032,48 @@ vdosys0: syscon@1c01d000 {
 			mediatek,gce-client-reg = <&gce0 SUBSYS_1c01XXXX 0xd000 0x1000>;
 		};
 
+		larb0: smi@1c022000 {
+			compatible = "mediatek,mt8188-smi-larb";
+			reg = <0 0x1c022000 0 0x1000>;
+			clocks = <&vdosys0 CLK_VDO0_SMI_LARB>,
+				 <&vdosys0 CLK_VDO0_SMI_LARB>;
+			clock-names = "apb", "smi";
+			power-domains = <&spm MT8188_POWER_DOMAIN_VDOSYS0>;
+			mediatek,larb-id = <SMI_L0_ID>;
+			mediatek,smi = <&vdo_smi_common>;
+		};
+
+		larb1: smi@1c023000 {
+			compatible = "mediatek,mt8188-smi-larb";
+			reg = <0 0x1c023000 0 0x1000>;
+			clocks = <&vdosys0 CLK_VDO0_SMI_LARB>,
+				 <&vdosys0 CLK_VDO0_SMI_LARB>;
+			clock-names = "apb", "smi";
+			power-domains = <&spm MT8188_POWER_DOMAIN_VDOSYS0>;
+			mediatek,larb-id = <SMI_L1_ID>;
+			mediatek,smi = <&vpp_smi_common>;
+		};
+
+		vdo_smi_common: smi@1c024000 {
+			compatible = "mediatek,mt8188-smi-common-vdo";
+			reg = <0 0x1c024000 0 0x1000>;
+			clocks = <&vdosys0 CLK_VDO0_SMI_COMMON>,
+				 <&vdosys0 CLK_VDO0_SMI_GALS>;
+			clock-names = "apb", "smi";
+			power-domains = <&spm MT8188_POWER_DOMAIN_VDOSYS0>;
+		};
+
+		vdo_iommu: iommu@1c028000 {
+			compatible = "mediatek,mt8188-iommu-vdo";
+			reg = <0 0x1c028000 0 0x5000>;
+			clocks = <&vdosys0 CLK_VDO0_SMI_IOMMU>;
+			clock-names = "bclk";
+			interrupts = <GIC_SPI 673 IRQ_TYPE_LEVEL_HIGH 0>;
+			power-domains = <&spm MT8188_POWER_DOMAIN_VDOSYS0>;
+			#iommu-cells = <1>;
+			mediatek,larbs = <&larb0 &larb2 &larb5 &larb19 &larb21>;
+		};
+
 		vdosys1: syscon@1c100000 {
 			compatible = "mediatek,mt8188-vdosys1", "syscon";
 			reg = <0 0x1c100000 0 0x1000>;
@@ -1935,5 +2082,27 @@ vdosys1: syscon@1c100000 {
 			mboxes = <&gce0 1 CMDQ_THR_PRIO_4>;
 			mediatek,gce-client-reg = <&gce0 SUBSYS_1c10XXXX 0 0x1000>;
 		};
+
+		larb2: smi@1c102000 {
+			compatible = "mediatek,mt8188-smi-larb";
+			reg = <0 0x1c102000 0 0x1000>;
+			clocks = <&vdosys1 CLK_VDO1_SMI_LARB2>,
+				 <&vdosys1 CLK_VDO1_SMI_LARB2>;
+			clock-names = "apb", "smi";
+			power-domains = <&spm MT8188_POWER_DOMAIN_VDOSYS1>;
+			mediatek,larb-id = <SMI_L2_ID>;
+			mediatek,smi = <&vdo_smi_common>;
+		};
+
+		larb3: smi@1c103000 {
+			compatible = "mediatek,mt8188-smi-larb";
+			reg = <0 0x1c103000 0 0x1000>;
+			clocks = <&vdosys1 CLK_VDO1_SMI_LARB3>,
+				 <&vdosys1 CLK_VDO1_SMI_LARB3>;
+			clock-names = "apb", "smi";
+			power-domains = <&spm MT8188_POWER_DOMAIN_VDOSYS1>;
+			mediatek,larb-id = <SMI_L3_ID>;
+			mediatek,smi = <&vpp_smi_common>;
+		};
 	};
 };
-- 
2.46.0.469.g59c65b2a67-goog

[PATCH 09/13] arm64: dts: mediatek: mt8188: Add PWM nodes for display backlight

[Fei Shao]

Add two hardware PWM nodes for display backlight usage on MT8188 SoC,
and mark them as disabled by default.
Boards can enable the necessary PWM node as needed.

Signed-off-by: Fei Shao <fshao@chromium.org>
---

 arch/arm64/boot/dts/mediatek/mt8188.dtsi | 22 ++++++++++++++++++++++
 1 file changed, 22 insertions(+)

diff --git a/arch/arm64/boot/dts/mediatek/mt8188.dtsi b/arch/arm64/boot/dts/mediatek/mt8188.dtsi
index 7e3a90c1a173..4593bc1fb5b7 100644
--- a/arch/arm64/boot/dts/mediatek/mt8188.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8188.dtsi
@@ -1425,6 +1425,28 @@ lvts_ap: thermal-sensor@1100b000 {
 			#thermal-sensor-cells = <1>;
 		};
 
+		disp_pwm0: pwm@1100e000 {
+			compatible = "mediatek,mt8188-disp-pwm", "mediatek,mt8183-disp-pwm";
+			reg = <0 0x1100e000 0 0x1000>;
+			clocks = <&topckgen CLK_TOP_DISP_PWM0>,
+				 <&infracfg_ao CLK_INFRA_AO_DISP_PWM>;
+			clock-names = "main", "mm";
+			interrupts = <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH 0>;
+			#pwm-cells = <2>;
+			status = "disabled";
+		};
+
+		disp_pwm1: pwm@1100f000 {
+			compatible = "mediatek,mt8188-disp-pwm", "mediatek,mt8183-disp-pwm";
+			reg = <0 0x1100f000 0 0x1000>;
+			clocks = <&topckgen CLK_TOP_DISP_PWM1>,
+				 <&infracfg_ao CLK_INFRA_AO_DISP_PWM1>;
+			clock-names = "main", "mm";
+			interrupts = <GIC_SPI 793 IRQ_TYPE_LEVEL_HIGH 0>;
+			#pwm-cells = <2>;
+			status = "disabled";
+		};
+
 		spi1: spi@11010000 {
 			compatible = "mediatek,mt8188-spi-ipm", "mediatek,spi-ipm";
 			#address-cells = <1>;
-- 
2.46.0.469.g59c65b2a67-goog

[PATCH 10/13] dt-bindings: spmi: spmi-mtk-pmif: Add compatible for MT8188

[Fei Shao]

Add compatible string for the SPMI block on MT8188 SoC, which is
compatible with the one used on MT8195.

Signed-off-by: Fei Shao <fshao@chromium.org>
---

 Documentation/devicetree/bindings/spmi/mtk,spmi-mtk-pmif.yaml | 1 +
 1 file changed, 1 insertion(+)

diff --git a/Documentation/devicetree/bindings/spmi/mtk,spmi-mtk-pmif.yaml b/Documentation/devicetree/bindings/spmi/mtk,spmi-mtk-pmif.yaml
index ac99883a3f29..7f0be0ac644a 100644
--- a/Documentation/devicetree/bindings/spmi/mtk,spmi-mtk-pmif.yaml
+++ b/Documentation/devicetree/bindings/spmi/mtk,spmi-mtk-pmif.yaml
@@ -25,6 +25,7 @@ properties:
       - items:
           - enum:
               - mediatek,mt8186-spmi
+              - mediatek,mt8188-spmi
           - const: mediatek,mt8195-spmi
 
   reg:
-- 
2.46.0.469.g59c65b2a67-goog

Re: [PATCH 10/13] dt-bindings: spmi: spmi-mtk-pmif: Add compatible for MT8188

[Rob Herring (Arm)]

On Mon, 09 Sep 2024 19:14:23 +0800, Fei Shao wrote:
> Add compatible string for the SPMI block on MT8188 SoC, which is
> compatible with the one used on MT8195.
> 
> Signed-off-by: Fei Shao <fshao@chromium.org>
> ---
> 
>  Documentation/devicetree/bindings/spmi/mtk,spmi-mtk-pmif.yaml | 1 +
>  1 file changed, 1 insertion(+)
> 

Acked-by: Rob Herring (Arm) <robh@kernel.org>

Re: [PATCH 10/13] dt-bindings: spmi: spmi-mtk-pmif: Add compatible for MT8188

[Stephen Boyd]

Quoting Fei Shao (2024-09-09 04:14:23)
> Add compatible string for the SPMI block on MT8188 SoC, which is
> compatible with the one used on MT8195.
> 
> Signed-off-by: Fei Shao <fshao@chromium.org>
> ---

Acked-by: Stephen Boyd <sboyd@kernel.org>

[PATCH 11/13] arm64: dts: mediatek: mt8188: Add SPMI support for PMIC control

[Fei Shao]

Add SPMI node for PMIC control on MT8188 SoC.

Signed-off-by: Fei Shao <fshao@chromium.org>
---

 arch/arm64/boot/dts/mediatek/mt8188.dtsi | 12 ++++++++++++
 1 file changed, 12 insertions(+)

diff --git a/arch/arm64/boot/dts/mediatek/mt8188.dtsi b/arch/arm64/boot/dts/mediatek/mt8188.dtsi
index 4593bc1fb5b7..08f13ccefcfc 100644
--- a/arch/arm64/boot/dts/mediatek/mt8188.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8188.dtsi
@@ -1311,6 +1311,18 @@ pwrap: pwrap@10024000 {
 			clock-names = "spi", "wrap";
 		};
 
+		spmi: spmi@10027000 {
+			compatible = "mediatek,mt8188-spmi", "mediatek,mt8195-spmi";
+			reg = <0 0x10027000 0 0x000e00>, <0 0x10029000 0 0x000100>;
+			reg-names = "pmif", "spmimst";
+			assigned-clocks = <&topckgen CLK_TOP_SPMI_M_MST>;
+			assigned-clock-parents = <&topckgen CLK_TOP_ULPOSC1_D10>;
+			clocks = <&infracfg_ao CLK_INFRA_AO_PMIC_AP>,
+				 <&infracfg_ao CLK_INFRA_AO_PMIC_TMR>,
+				 <&topckgen CLK_TOP_SPMI_M_MST>;
+			clock-names = "pmif_sys_ck", "pmif_tmr_ck", "spmimst_clk_mux";
+		};
+
 		infra_iommu: iommu@10315000 {
 			compatible = "mediatek,mt8188-iommu-infra";
 			reg = <0 0x10315000 0 0x1000>;
-- 
2.46.0.469.g59c65b2a67-goog

[PATCH 12/13] dt-bindings: mailbox: mtk,adsp-mbox: Add compatible for MT8188

[Fei Shao]

Add compatible string for ADSP mailbox on MT8188 SoC, which is
compatible with the one used on MT8186.

Signed-off-by: Fei Shao <fshao@chromium.org>
---

 .../devicetree/bindings/mailbox/mtk,adsp-mbox.yaml   | 12 +++++++++---
 1 file changed, 9 insertions(+), 3 deletions(-)

diff --git a/Documentation/devicetree/bindings/mailbox/mtk,adsp-mbox.yaml b/Documentation/devicetree/bindings/mailbox/mtk,adsp-mbox.yaml
index 72c1d9e82c89..8a1369df4ecb 100644
--- a/Documentation/devicetree/bindings/mailbox/mtk,adsp-mbox.yaml
+++ b/Documentation/devicetree/bindings/mailbox/mtk,adsp-mbox.yaml
@@ -17,9 +17,15 @@ description: |
 
 properties:
   compatible:
-    enum:
-      - mediatek,mt8195-adsp-mbox
-      - mediatek,mt8186-adsp-mbox
+    oneOf:
+      - enum:
+          - mediatek,mt8186-adsp-mbox
+          - mediatek,mt8195-adsp-mbox
+      - items:
+          - enum:
+              - mediatek,mt8188-adsp-mbox
+          - const: mediatek,mt8186-adsp-mbox
+
 
   "#mbox-cells":
     const: 0
-- 
2.46.0.469.g59c65b2a67-goog

Re: [PATCH 12/13] dt-bindings: mailbox: mtk,adsp-mbox: Add compatible for MT8188

[Rob Herring (Arm)]

On Mon, 09 Sep 2024 19:14:25 +0800, Fei Shao wrote:
> Add compatible string for ADSP mailbox on MT8188 SoC, which is
> compatible with the one used on MT8186.
> 
> Signed-off-by: Fei Shao <fshao@chromium.org>
> ---
> 
>  .../devicetree/bindings/mailbox/mtk,adsp-mbox.yaml   | 12 +++++++++---
>  1 file changed, 9 insertions(+), 3 deletions(-)
> 

Acked-by: Rob Herring (Arm) <robh@kernel.org>

[PATCH 13/13] arm64: dts: mediatek: mt8188: Add audio support

[Fei Shao]

Add following nodes to support audio enablement on MT8188 SoC:
- sound card
- audio controller (AFE)
- audio DSP and its associated mailboxes

Signed-off-by: Fei Shao <fshao@chromium.org>
---

 arch/arm64/boot/dts/mediatek/mt8188.dtsi | 96 ++++++++++++++++++++++++
 1 file changed, 96 insertions(+)

diff --git a/arch/arm64/boot/dts/mediatek/mt8188.dtsi b/arch/arm64/boot/dts/mediatek/mt8188.dtsi
index 08f13ccefcfc..d99447a01a60 100644
--- a/arch/arm64/boot/dts/mediatek/mt8188.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8188.dtsi
@@ -431,6 +431,11 @@ psci {
 		method = "smc";
 	};
 
+	sound: sound {
+		mediatek,platform = <&afe>;
+		status = "disabled";
+	};
+
 	thermal_zones: thermal-zones {
 		cpu-little0-thermal {
 			polling-delay = <1000>;
@@ -1356,6 +1361,97 @@ scp: scp@10500000 {
 			interrupts = <GIC_SPI 462 IRQ_TYPE_LEVEL_HIGH 0>;
 		};
 
+		afe: audio-controller@10b10000 {
+			compatible = "mediatek,mt8188-afe";
+			reg = <0 0x10b10000 0 0x10000>;
+			assigned-clocks = <&topckgen CLK_TOP_A1SYS_HP>;
+			assigned-clock-parents =  <&clk26m>;
+			clocks = <&clk26m>,
+				 <&apmixedsys CLK_APMIXED_APLL1>,
+				 <&apmixedsys CLK_APMIXED_APLL2>,
+				 <&topckgen CLK_TOP_APLL12_CK_DIV0>,
+				 <&topckgen CLK_TOP_APLL12_CK_DIV1>,
+				 <&topckgen CLK_TOP_APLL12_CK_DIV2>,
+				 <&topckgen CLK_TOP_APLL12_CK_DIV3>,
+				 <&topckgen CLK_TOP_APLL12_CK_DIV9>,
+				 <&topckgen CLK_TOP_A1SYS_HP>,
+				 <&topckgen CLK_TOP_AUD_INTBUS>,
+				 <&topckgen CLK_TOP_AUDIO_H>,
+				 <&topckgen CLK_TOP_AUDIO_LOCAL_BUS>,
+				 <&topckgen CLK_TOP_DPTX>,
+				 <&topckgen CLK_TOP_I2SO1>,
+				 <&topckgen CLK_TOP_I2SO2>,
+				 <&topckgen CLK_TOP_I2SI1>,
+				 <&topckgen CLK_TOP_I2SI2>,
+				 <&adsp_audio26m CLK_AUDIODSP_AUDIO26M>,
+				 <&topckgen CLK_TOP_APLL1_D4>,
+				 <&topckgen CLK_TOP_APLL2_D4>,
+				 <&topckgen CLK_TOP_APLL12_CK_DIV4>,
+				 <&topckgen CLK_TOP_A2SYS>,
+				 <&topckgen CLK_TOP_AUD_IEC>;
+			clock-names = "clk26m",
+				      "apll1",
+				      "apll2",
+				      "apll12_div0",
+				      "apll12_div1",
+				      "apll12_div2",
+				      "apll12_div3",
+				      "apll12_div9",
+				      "top_a1sys_hp",
+				      "top_aud_intbus",
+				      "top_audio_h",
+				      "top_audio_local_bus",
+				      "top_dptx",
+				      "top_i2so1",
+				      "top_i2so2",
+				      "top_i2si1",
+				      "top_i2si2",
+				      "adsp_audio_26m",
+				      "apll1_d4",
+				      "apll2_d4",
+				      "apll12_div4",
+				      "top_a2sys",
+				      "top_aud_iec";
+			interrupts = <GIC_SPI 822 IRQ_TYPE_LEVEL_HIGH 0>;
+			power-domains = <&spm MT8188_POWER_DOMAIN_AUDIO>;
+			resets = <&watchdog 14>;
+			reset-names = "audiosys";
+			mediatek,infracfg = <&infracfg_ao>;
+			mediatek,topckgen = <&topckgen>;
+			status = "disabled";
+		};
+
+		adsp: adsp@10b80000 {
+			compatible = "mediatek,mt8188-dsp";
+			reg = <0 0x10b80000 0 0x2000>,
+			      <0 0x10d00000 0 0x80000>,
+			      <0 0x10b8b000 0 0x100>,
+			      <0 0x10b8f000 0 0x1000>;
+			reg-names = "cfg", "sram", "sec", "bus";
+			assigned-clocks = <&topckgen CLK_TOP_ADSP>;
+			clocks = <&topckgen CLK_TOP_ADSP>,
+				 <&topckgen CLK_TOP_AUDIO_LOCAL_BUS>;
+			clock-names = "audiodsp", "adsp_bus";
+			mboxes = <&adsp_mailbox0>, <&adsp_mailbox1>;
+			mbox-names = "rx", "tx";
+			power-domains = <&spm MT8188_POWER_DOMAIN_ADSP>;
+			status = "disabled";
+		};
+
+		adsp_mailbox0: mailbox@10b86000 {
+			compatible = "mediatek,mt8188-adsp-mbox", "mediatek,mt8186-adsp-mbox";
+			reg = <0 0x10b86100 0 0x1000>;
+			interrupts = <GIC_SPI 478 IRQ_TYPE_LEVEL_HIGH 0>;
+			#mbox-cells = <0>;
+		};
+
+		adsp_mailbox1: mailbox@10b87000 {
+			compatible = "mediatek,mt8188-adsp-mbox", "mediatek,mt8186-adsp-mbox";
+			reg = <0 0x10b87100 0 0x1000>;
+			interrupts = <GIC_SPI 479 IRQ_TYPE_LEVEL_HIGH 0>;
+			#mbox-cells = <0>;
+		};
+
 		adsp_audio26m: clock-controller@10b91100 {
 			compatible = "mediatek,mt8188-adsp-audio26m";
 			reg = <0 0x10b91100 0 0x100>;
-- 
2.46.0.469.g59c65b2a67-goog