From: claudiu beznea <claudiu.beznea@tuxon.dev>
To: Geert Uytterhoeven <geert@linux-m68k.org>
Cc: mturquette@baylibre.com, sboyd@kernel.org, robh+dt@kernel.org,
krzysztof.kozlowski+dt@linaro.org, conor+dt@kernel.org,
ulf.hansson@linaro.org, linus.walleij@linaro.org,
gregkh@linuxfoundation.org, jirislaby@kernel.org,
magnus.damm@gmail.com, catalin.marinas@arm.com, will@kernel.org,
prabhakar.mahadev-lad.rj@bp.renesas.com,
biju.das.jz@bp.renesas.com, quic_bjorande@quicinc.com,
arnd@arndb.de, konrad.dybcio@linaro.org,
neil.armstrong@linaro.org, nfraprado@collabora.com,
rafal@milecki.pl, wsa+renesas@sang-engineering.com,
linux-renesas-soc@vger.kernel.org, linux-clk@vger.kernel.org,
devicetree@vger.kernel.org, linux-kernel@vger.kernel.org,
linux-mmc@vger.kernel.org, linux-gpio@vger.kernel.org,
linux-serial@vger.kernel.org,
linux-arm-kernel@lists.infradead.org,
Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
Subject: Re: [PATCH 30/37] pinctrl: renesas: rzg2l: add support for RZ/G3S SoC
Date: Tue, 26 Sep 2023 13:58:44 +0300 [thread overview]
Message-ID: <64e91f8d-a94e-c835-75ef-ce9ab557dc54@tuxon.dev> (raw)
In-Reply-To: <CAMuHMdV2GEKF0QjKudz529_tmUksTNMJtZu9NwC18KX-AXwaeg@mail.gmail.com>
Hi, Geert,
On 21.09.2023 17:58, Geert Uytterhoeven wrote:
> Hi Claudiu,
>
> On Tue, Sep 12, 2023 at 6:53 AM Claudiu <claudiu.beznea@tuxon.dev> wrote:
>> From: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
>>
>> Add basic support for RZ/G3S to be able to boot from SD card, have a
>> running console port and use GPIOs. RZ/G3S has 82 general-purpose IO
>> ports. Support for the remaining pin functions (e.g. Ethernet, XSPI)
>> will be added along with controller specific support.
>>
>> Signed-off-by: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
>
> Thanks for your patch!
>
>> --- a/drivers/pinctrl/renesas/pinctrl-rzg2l.c
>> +++ b/drivers/pinctrl/renesas/pinctrl-rzg2l.c
>> @@ -1330,6 +1336,36 @@ static const u32 r9a07g043_gpio_configs[] = {
>> RZG2L_GPIO_PORT_PACK(6, 0x22, RZG2L_MPXED_PIN_FUNCS),
>> };
>>
>> +static const u32 r9a08g045_gpio_configs[] = {
>> + RZG2L_GPIO_PORT_PACK(4, 0x20, RZG3S_MPXED_PIN_FUNCS(A)), /* P0 */
>> + RZG2L_GPIO_PORT_PACK(5, 0x30, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IOLH_C |
>> + PIN_CFG_IO_VMC_ETH0)), /* P1 */
>
> P1_0 and P7_0 have IEN functionality.
> I don't know how to represent that...
I think Prabhakar's series at [1] may help (or make a step forward) in
supporting this. I have in mind to wait for it and adapt RZ/G3S afterwards.
[1]
https://lore.kernel.org/all/20230630120433.49529-2-prabhakar.mahadev-lad.rj@bp.renesas.com/
>
>> + RZG2L_GPIO_PORT_PACK(4, 0x31, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IOLH_C |
>> + PIN_CFG_IO_VMC_ETH0)), /* P2 */
>> + RZG2L_GPIO_PORT_PACK(4, 0x32, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IOLH_C |
>> + PIN_CFG_IO_VMC_ETH0)), /* P3 */
>> + RZG2L_GPIO_PORT_PACK(6, 0x33, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IOLH_C |
>> + PIN_CFG_IO_VMC_ETH0)), /* P4 */
>> + RZG2L_GPIO_PORT_PACK(5, 0x21, RZG3S_MPXED_PIN_FUNCS(A)), /* P5 */
>> + RZG2L_GPIO_PORT_PACK(5, 0x22, RZG3S_MPXED_PIN_FUNCS(A)), /* P6 */
>> + RZG2L_GPIO_PORT_PACK(5, 0x34, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IOLH_C |
>> + PIN_CFG_IO_VMC_ETH1)), /* P7 */
>> + RZG2L_GPIO_PORT_PACK(5, 0x35, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IOLH_C |
>> + PIN_CFG_IO_VMC_ETH1)), /* P8 */
>> + RZG2L_GPIO_PORT_PACK(4, 0x36, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IOLH_C |
>> + PIN_CFG_IO_VMC_ETH1)), /* P9 */
>> + RZG2L_GPIO_PORT_PACK(5, 0x37, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IOLH_C |
>> + PIN_CFG_IO_VMC_ETH1)), /* P10 */
>> + RZG2L_GPIO_PORT_PACK(4, 0x23, RZG3S_MPXED_PIN_FUNCS(B) | PIN_CFG_IEN), /* P11 */
>
> P11_0 does not have IEN functionality.
> I don't know how to represent that...
Same here.
>
>> + RZG2L_GPIO_PORT_PACK(2, 0x24, RZG3S_MPXED_PIN_FUNCS(B) | PIN_CFG_IEN), /* P12 */
>> + RZG2L_GPIO_PORT_PACK(5, 0x25, RZG3S_MPXED_PIN_FUNCS(A)), /* P13 */
>> + RZG2L_GPIO_PORT_PACK(3, 0x26, RZG3S_MPXED_PIN_FUNCS(A)), /* P14 */
>> + RZG2L_GPIO_PORT_PACK(4, 0x27, RZG3S_MPXED_PIN_FUNCS(A)), /* P15 */
>> + RZG2L_GPIO_PORT_PACK(2, 0x28, RZG3S_MPXED_PIN_FUNCS(A)), /* P16 */
>> + RZG2L_GPIO_PORT_PACK(4, 0x29, RZG3S_MPXED_PIN_FUNCS(A)), /* P17 */
>> + RZG2L_GPIO_PORT_PACK(6, 0x2a, RZG3S_MPXED_PIN_FUNCS(A)), /* P18 */
>> +};
>> +
>> static const struct {
>> struct rzg2l_dedicated_configs common[35];
>> struct rzg2l_dedicated_configs rzg2l_pins[7];
>> @@ -1416,6 +1452,46 @@ static const struct {
>> }
>> };
>>
>> +static const struct rzg2l_dedicated_configs rzg3s_dedicated_pins[] = {
>> + { "NMI", RZG2L_SINGLE_PIN_PACK(0x0, 0, (PIN_CFG_FILONOFF | PIN_CFG_FILNUM |
>> + PIN_CFG_FILCLKSEL)) },
>> + { "TMS/SWDIO", RZG2L_SINGLE_PIN_PACK(0x1, 0, (PIN_CFG_IOLH_A | PIN_CFG_IEN |
>> + PIN_CFG_SOFT_PS)) },
>> + { "TDO", RZG2L_SINGLE_PIN_PACK(0x1, 1, (PIN_CFG_IOLH_A | PIN_CFG_SOFT_PS)) },
>> + { "WDTOVF_PERROUT#", RZG2L_SINGLE_PIN_PACK(0x6, 0, PIN_CFG_IOLH_A | PIN_CFG_SOFT_PS) },
>> + { "SD0_CLK", RZG2L_SINGLE_PIN_PACK(0x10, 0, (PIN_CFG_IOLH_B | PIN_CFG_IO_VMC_SD0)) },
>> + { "SD0_CMD", RZG2L_SINGLE_PIN_PACK(0x10, 1, (PIN_CFG_IOLH_B | PIN_CFG_IEN |
>> + PIN_CFG_IO_VMC_SD0)) },
>> + { "SD0_RST#", RZG2L_SINGLE_PIN_PACK(0x10, 2, (PIN_CFG_IOLH_B | PIN_CFG_IO_VMC_SD0)) },
>> + { "SD0_DATA0", RZG2L_SINGLE_PIN_PACK(0x11, 0, (PIN_CFG_IOLH_B | PIN_CFG_IEN |
>> + PIN_CFG_IO_VMC_SD0)) },
>> + { "SD0_DATA1", RZG2L_SINGLE_PIN_PACK(0x11, 1, (PIN_CFG_IOLH_B | PIN_CFG_IEN |
>> + PIN_CFG_IO_VMC_SD0)) },
>> + { "SD0_DATA2", RZG2L_SINGLE_PIN_PACK(0x11, 2, (PIN_CFG_IOLH_B | PIN_CFG_IEN |
>> + PIN_CFG_IO_VMC_SD0)) },
>> + { "SD0_DATA3", RZG2L_SINGLE_PIN_PACK(0x11, 3, (PIN_CFG_IOLH_B | PIN_CFG_IEN |
>> + PIN_CFG_IO_VMC_SD0)) },
>> + { "SD0_DATA4", RZG2L_SINGLE_PIN_PACK(0x11, 4, (PIN_CFG_IOLH_B | PIN_CFG_IEN |
>> + PIN_CFG_IO_VMC_SD0)) },
>> + { "SD0_DATA5", RZG2L_SINGLE_PIN_PACK(0x11, 5, (PIN_CFG_IOLH_B | PIN_CFG_IEN |
>> + PIN_CFG_IO_VMC_SD0)) },
>> + { "SD0_DATA6", RZG2L_SINGLE_PIN_PACK(0x11, 6, (PIN_CFG_IOLH_B | PIN_CFG_IEN |
>> + PIN_CFG_IO_VMC_SD0)) },
>> + { "SD0_DATA7", RZG2L_SINGLE_PIN_PACK(0x11, 7, (PIN_CFG_IOLH_B | PIN_CFG_IEN |
>> + PIN_CFG_IO_VMC_SD0)) },
>> + { "SD1_CLK", RZG2L_SINGLE_PIN_PACK(0x12, 0, (PIN_CFG_IOLH_B | PIN_CFG_IO_VMC_SD1)) },
>> + { "SD1_CMD", RZG2L_SINGLE_PIN_PACK(0x12, 1, (PIN_CFG_IOLH_B | PIN_CFG_IEN |
>> + PIN_CFG_IO_VMC_SD1)) },
>> + { "SD1_DATA0", RZG2L_SINGLE_PIN_PACK(0x13, 0, (PIN_CFG_IOLH_B | PIN_CFG_IEN |
>> + PIN_CFG_IO_VMC_SD1)) },
>> + { "SD1_DATA1", RZG2L_SINGLE_PIN_PACK(0x13, 1, (PIN_CFG_IOLH_B | PIN_CFG_IEN |
>> + PIN_CFG_IO_VMC_SD1)) },
>> + { "SD1_DATA2", RZG2L_SINGLE_PIN_PACK(0x13, 2, (PIN_CFG_IOLH_B | PIN_CFG_IEN |
>> + PIN_CFG_IO_VMC_SD1)) },
>> + { "SD1_DATA3", RZG2L_SINGLE_PIN_PACK(0x13, 3, (PIN_CFG_IOLH_B | PIN_CFG_IEN |
>> + PIN_CFG_IO_VMC_SD1)) },
>
> Is there any specific reason you left out the XSPI, Audio clock, and I3C pins?
I kept only the necessary support for booting and having SDs, GPIO
functional as a way of proving that all that has been added has been tested
(similar to clock support). Thus, with e.g. XSPI support I will add at the
same time clocks and pinctrl.
>
>> +};
>> +
>> static int rzg2l_gpio_get_gpioint(unsigned int virq, const struct rzg2l_pinctrl_data *data)
>> {
>> unsigned int gpioint;
>> @@ -1823,6 +1899,40 @@ static const struct rzg2l_hwcfg rzg2l_hwcfg = {
>> .iolh_groupb_oi = { 100, 66, 50, 33, },
>> };
>>
>> +static const struct rzg2l_hwcfg rzg3s_hwcfg = {
>> + .regs = {
>> + .pwpr = 0x3000,
>> + .sd_ch = 0x3004,
>> + },
>> + .iolh_groupa_ua = {
>> + /* 1v8 power source */
>> + [RZG2L_IOLH_IDX_1V8] = 2200, 4400, 9000, 10000,
>> + /* 2v5 power source */
>> + [RZG2L_IOLH_IDX_2V5 ... RZG2L_IOLH_IDX_3V3 - 1] = RZG2L_INVALID_IOLH_VAL,
>
> Can be dropped once zero means invalid.
>
>> + /* 3v3 power source */
>> + [RZG2L_IOLH_IDX_3V3] = 1900, 4000, 8000, 9000,
>> + },
>> + .iolh_groupb_ua = {
>> + /* 1v8 power source */
>> + [RZG2L_IOLH_IDX_1V8] = 7000, 8000, 9000, 10000,
>> + /* 2v5 power source */
>> + [RZG2L_IOLH_IDX_2V5 ... RZG2L_IOLH_IDX_3V3 - 1] = RZG2L_INVALID_IOLH_VAL,
>
> Can be dropped once zero means invalid.
>
>> + /* 3v3 power source */
>> + [RZG2L_IOLH_IDX_3V3] = 4000, 6000, 8000, 9000,
>> + },
>> + .iolh_groupc_ua = {
>> + /* 1v8 power source */
>> + [RZG2L_IOLH_IDX_1V8] = 5200, 6000, 6550, 6800,
>> + /* 2v5 source */
>> + [RZG2L_IOLH_IDX_2V5] = 4700, 5300, 5800, 6100,
>> + /* 3v3 power source */
>> + [RZG2L_IOLH_IDX_3V3] = 4500, 5200, 5700, 6050,
>> + },
>> + .drive_strength_ua = true,
>> + .iolh_groupb_oi = { [0 ... 3] = RZG2L_INVALID_IOLH_VAL, },
>> + .func_base = 1,
>> +};
>> +
>> static struct rzg2l_pinctrl_data r9a07g043_data = {
>> .port_pins = rzg2l_gpio_names,
>> .port_pin_configs = r9a07g043_gpio_configs,
>> @@ -1844,6 +1954,16 @@ static struct rzg2l_pinctrl_data r9a07g044_data = {
>> .hwcfg = &rzg2l_hwcfg,
>> };
>>
>> +static struct rzg2l_pinctrl_data r9a08g045_data = {
>> + .port_pins = rzg2l_gpio_names,
>> + .port_pin_configs = r9a08g045_gpio_configs,
>> + .n_ports = ARRAY_SIZE(r9a08g045_gpio_configs),
>> + .dedicated_pins = rzg3s_dedicated_pins,
>> + .n_port_pins = ARRAY_SIZE(r9a08g045_gpio_configs) * RZG2L_PINS_PER_PORT,
>> + .n_dedicated_pins = ARRAY_SIZE(rzg3s_dedicated_pins),
>> + .hwcfg = &rzg3s_hwcfg,
>> +};
>> +
>> static const struct of_device_id rzg2l_pinctrl_of_table[] = {
>> {
>> .compatible = "renesas,r9a07g043-pinctrl",
>
> Please add a BUILD_BUG_ON() check for RZ/G3S to the
> rzg2l_pinctrl_probe() function, as is done for the other SoCs in
> the family.
Ok.
>
> The rest LGTM.
>
> Gr{oetje,eeting}s,
>
> Geert
>
next prev parent reply other threads:[~2023-09-26 10:58 UTC|newest]
Thread overview: 118+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-09-12 4:51 [PATCH 00/37] Add new Renesas RZ/G3S SoC and RZ/G3S SMARC EVK Claudiu
2023-09-12 4:51 ` [PATCH 01/37] dt-bindings: serial: renesas,scif: document r9a08g045 support Claudiu
2023-09-12 16:00 ` Rob Herring
2023-09-14 9:35 ` Geert Uytterhoeven
2023-09-12 4:51 ` [PATCH 02/37] dt-bindings: soc: renesas: document Renesas RZ/G3S SoC variants Claudiu
2023-09-12 16:01 ` Rob Herring
2023-09-14 9:49 ` Geert Uytterhoeven
2023-09-12 4:51 ` [PATCH 03/37] dt-bindings: soc: renesas: renesas,rzg2l-sysc: document RZ/G3S SoC Claudiu
2023-09-12 16:01 ` Rob Herring
2023-09-14 9:49 ` Geert Uytterhoeven
2023-09-12 4:51 ` [PATCH 04/37] soc: renesas: identify " Claudiu
2023-09-14 9:49 ` Geert Uytterhoeven
2023-09-12 4:51 ` [PATCH 05/37] soc: renesas: remove blank lines Claudiu
2023-09-14 9:49 ` Geert Uytterhoeven
2023-09-12 4:51 ` [PATCH 06/37] clk: renesas: rzg2l: wait for status bit of SD mux before continuing Claudiu
2023-09-14 11:42 ` Geert Uytterhoeven
2023-09-15 5:35 ` claudiu beznea
2023-09-12 4:51 ` [PATCH 07/37] clk: renesas: rzg2l: lock around writes to mux register Claudiu
2023-09-14 12:13 ` Geert Uytterhoeven
2023-09-15 5:46 ` claudiu beznea
2023-09-12 4:51 ` [PATCH 08/37] clk: renesas: rzg2l: trust value returned by hardware Claudiu
2023-09-12 16:43 ` Sergey Shtylyov
2023-09-14 12:18 ` Geert Uytterhoeven
2023-09-12 4:51 ` [PATCH 09/37] clk: renesas: rzg2l: fix computation formula Claudiu
2023-09-14 12:55 ` Geert Uytterhoeven
2023-09-26 11:47 ` claudiu beznea
2023-09-26 14:44 ` Geert Uytterhoeven
2023-09-27 8:00 ` Geert Uytterhoeven
2023-09-28 4:55 ` claudiu beznea
2023-09-12 4:51 ` [PATCH 10/37] clk: renesas: rzg2l: use core->name for clock name Claudiu
2023-09-14 13:04 ` Geert Uytterhoeven
2023-09-15 5:47 ` claudiu beznea
2023-09-18 8:03 ` Geert Uytterhoeven
2023-09-12 4:51 ` [PATCH 11/37] clk: renesas: rzg2l: simplify a bit the logic in rzg2l_mod_clock_endisable() Claudiu
2023-09-14 13:06 ` Geert Uytterhoeven
2023-09-12 4:51 ` [PATCH 12/37] clk: renesas: rzg2l: reduce the critical area Claudiu
2023-09-14 13:12 ` Geert Uytterhoeven
2023-09-15 5:51 ` claudiu beznea
2023-09-15 7:05 ` Geert Uytterhoeven
2023-09-12 4:51 ` [PATCH 13/37] clk: renesas: rzg2l: use FIELD_GET() for PLL register fields Claudiu
2023-09-14 13:19 ` Geert Uytterhoeven
2023-09-12 4:51 ` [PATCH 14/37] clk: renesas: rzg2l: use u32 for flag and mux_flags Claudiu
2023-09-14 13:29 ` Geert Uytterhoeven
2023-09-18 8:03 ` Geert Uytterhoeven
2023-09-12 4:51 ` [PATCH 15/37] clk: renesas: rzg2l: add support for RZ/G3S PLL Claudiu
2023-09-14 13:58 ` Geert Uytterhoeven
2023-09-12 4:51 ` [PATCH 16/37] clk: renesas: rzg2l: add struct clk_hw_data Claudiu
2023-09-14 15:17 ` Geert Uytterhoeven
2023-09-12 4:51 ` [PATCH 17/37] clk: renesas: rzg2l: remove CPG_SDHI_DSEL from generic header Claudiu
2023-09-14 15:18 ` Geert Uytterhoeven
2023-09-12 4:51 ` [PATCH 18/37] clk: renesas: rzg2l: refactor sd mux driver Claudiu
2023-09-14 15:18 ` Geert Uytterhoeven
2023-09-15 7:30 ` claudiu beznea
2023-09-15 8:06 ` Geert Uytterhoeven
2023-09-12 4:51 ` [PATCH 19/37] clk: renesas: rzg2l: add a divider clock for RZ/G3S Claudiu
2023-09-12 4:51 ` [PATCH 20/37] dt-bindings: clock: renesas,rzg2l-cpg: document RZ/G3S SoC Claudiu
2023-09-12 16:02 ` Rob Herring
2023-09-15 11:58 ` Geert Uytterhoeven
2023-09-12 4:51 ` [PATCH 21/37] dt-bindings: clock: add r9a08g045 CPG clocks and resets definitions Claudiu
2023-09-12 16:03 ` Rob Herring
2023-09-14 15:26 ` Geert Uytterhoeven
2023-09-15 7:24 ` Krzysztof Kozlowski
2023-09-15 7:38 ` Geert Uytterhoeven
2023-09-15 7:42 ` Krzysztof Kozlowski
2023-09-15 11:59 ` Geert Uytterhoeven
2023-09-28 4:54 ` claudiu beznea
2023-09-28 7:25 ` Geert Uytterhoeven
2023-09-12 4:51 ` [PATCH 22/37] clk: renesas: add minimal boot support for RZ/G3S SoC Claudiu
2023-09-15 12:52 ` Geert Uytterhoeven
2023-09-18 6:20 ` claudiu beznea
2023-09-18 7:00 ` Geert Uytterhoeven
2023-09-18 7:50 ` claudiu beznea
2023-09-18 9:05 ` Geert Uytterhoeven
2023-09-12 4:51 ` [PATCH 23/37] pinctrl: renesas: rzg2l: index all registers based on port offset Claudiu
2023-09-20 13:20 ` Geert Uytterhoeven
2023-09-20 13:43 ` Lad, Prabhakar
2023-09-12 4:51 ` [PATCH 24/37] pinctrl: renesas: rzg2l: adapt for different SD, PWPR register offsets Claudiu
2023-09-21 12:07 ` Geert Uytterhoeven
2023-09-12 4:51 ` [PATCH 25/37] pinctrl: renesas: rzg2l: adapt function number for RZ/G3S Claudiu
2023-09-21 12:51 ` Geert Uytterhoeven
2023-09-26 9:55 ` claudiu beznea
2023-09-26 14:23 ` Geert Uytterhoeven
2023-09-12 4:51 ` [PATCH 26/37] pinctrl: renesas: rzg2l: move ds and oi to SoC specific configuration Claudiu
2023-09-21 12:54 ` Geert Uytterhoeven
2023-09-12 4:51 ` [PATCH 27/37] pinctrl: renesas: rzg2l: add support for different ds values on different groups Claudiu
2023-09-21 13:07 ` Geert Uytterhoeven
2023-09-12 4:51 ` [PATCH 28/37] pinctrl: renesas: rzg2l: make struct rzg2l_pinctrl_data::dedicated_pins constant Claudiu
2023-09-21 13:08 ` Geert Uytterhoeven
2023-09-12 4:51 ` [PATCH 29/37] dt-bindings: pinctrl: renesas: document RZ/G3S SoC Claudiu
2023-09-12 16:13 ` Rob Herring
2023-09-21 15:00 ` Geert Uytterhoeven
2023-09-12 4:51 ` [PATCH 30/37] pinctrl: renesas: rzg2l: add support for " Claudiu
2023-09-21 14:58 ` Geert Uytterhoeven
2023-09-26 10:58 ` claudiu beznea [this message]
2023-09-26 14:29 ` Geert Uytterhoeven
2023-09-12 4:51 ` [PATCH 31/37] dt-bindings: mmc: renesas,sdhi: Document RZ/G3S support Claudiu
2023-09-12 16:13 ` Rob Herring
2023-09-14 14:47 ` Ulf Hansson
2023-09-14 15:35 ` Geert Uytterhoeven
2023-09-12 4:51 ` [PATCH 32/37] arm64: dts: renesas: add initial DTSI for RZ/G3S SoC Claudiu
2023-09-15 13:17 ` Geert Uytterhoeven
2023-09-12 4:51 ` [PATCH 33/37] arm64: dts: renesas: rzg3l-smarc-som: add initial support for RZ/G3S SMARC Carrier-II SoM Claudiu
2023-09-15 14:28 ` Geert Uytterhoeven
2023-09-18 6:02 ` claudiu beznea
2023-09-12 4:51 ` [PATCH 34/37] arm64: dts: renesas: rzg3s-smarc: add initial device tree for RZ SMARC Carrier-II board Claudiu
2023-09-15 14:32 ` Geert Uytterhoeven
2023-09-12 4:51 ` [PATCH 35/37] dt-bindings: arm: renesas: document SMARC Carrier-II EVK Claudiu
2023-09-12 16:16 ` Rob Herring
2023-09-13 5:32 ` claudiu beznea
2023-09-13 15:16 ` Geert Uytterhoeven
2023-09-12 4:51 ` [PATCH 36/37] arm64: dts: renesas: r9a08g045s33-smarc: add initial device tree for RZ/G3S SMARC EVK board Claudiu
2023-09-21 15:02 ` Geert Uytterhoeven
2023-09-12 4:51 ` [PATCH 37/37] arm64: defconfig: enable RZ/G3S (R9A08G045) SoC Claudiu
2023-09-15 14:34 ` Geert Uytterhoeven
2023-09-12 8:55 ` [PATCH 00/37] Add new Renesas RZ/G3S SoC and RZ/G3S SMARC EVK Linus Walleij
2023-09-12 9:03 ` Geert Uytterhoeven
2023-09-12 9:05 ` Linus Walleij
2023-09-13 5:40 ` claudiu beznea
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