From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id B920CEE49A3 for ; Wed, 23 Aug 2023 02:42:11 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231203AbjHWCmL (ORCPT ); Tue, 22 Aug 2023 22:42:11 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:41644 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229549AbjHWCmK (ORCPT ); Tue, 22 Aug 2023 22:42:10 -0400 Received: from ex01.ufhost.com (ex01.ufhost.com [61.152.239.75]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 38B6CCF9; Tue, 22 Aug 2023 19:42:04 -0700 (PDT) Received: from EXMBX165.cuchost.com (unknown [175.102.18.54]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (Client CN "EXMBX165", Issuer "EXMBX165" (not verified)) by ex01.ufhost.com (Postfix) with ESMTP id BB07824E2EE; Wed, 23 Aug 2023 10:42:01 +0800 (CST) Received: from EXMBX168.cuchost.com (172.16.6.78) by EXMBX165.cuchost.com (172.16.6.75) with Microsoft SMTP Server (TLS) id 15.0.1497.42; Wed, 23 Aug 2023 10:42:01 +0800 Received: from [192.168.125.113] (113.72.145.205) by EXMBX168.cuchost.com (172.16.6.78) with Microsoft SMTP Server (TLS) id 15.0.1497.42; Wed, 23 Aug 2023 10:42:00 +0800 Message-ID: <65292b7f-0e9d-65c1-4ca5-b23d301e02cd@starfivetech.com> Date: Wed, 23 Aug 2023 10:42:00 +0800 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (Windows NT 10.0; Win64; x64; rv:102.0) Gecko/20100101 Thunderbird/102.14.0 Subject: Re: [PATCH v2 5/5] riscv: dts: starfive: Add the nodes and pins of I2Srx/I2Stx0/I2Stx1 To: Xingyu Wu , Liam Girdwood , Mark Brown , Claudiu Beznea , Jaroslav Kysela , "Takashi Iwai" , Maxim Kochetkov , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Emil Renner Berthing CC: Jose Abreu , Paul Walmsley , Palmer Dabbelt , Albert Ou , , , , References: <20230821144151.207339-1-xingyu.wu@starfivetech.com> <20230821144151.207339-6-xingyu.wu@starfivetech.com> Content-Language: en-US From: Walker Chen In-Reply-To: <20230821144151.207339-6-xingyu.wu@starfivetech.com> Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: 7bit X-Originating-IP: [113.72.145.205] X-ClientProxiedBy: EXCAS066.cuchost.com (172.16.6.26) To EXMBX168.cuchost.com (172.16.6.78) X-YovoleRuleAgent: yovoleflag Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org On 2023/8/21 22:41, Xingyu Wu wrote: > Add I2Srx/I2Stx0/I2Stx1 nodes and pins configuration for the > StarFive JH7110 SoC. > > Signed-off-by: Xingyu Wu > --- > .../jh7110-starfive-visionfive-2.dtsi | 58 +++++++++++++++++ > arch/riscv/boot/dts/starfive/jh7110.dtsi | 65 +++++++++++++++++++ > 2 files changed, 123 insertions(+) > > diff --git a/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi b/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi > index d79f94432b27..7179f1a31cf2 100644 > --- a/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi > +++ b/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi > @@ -203,6 +203,24 @@ &i2c6 { > status = "okay"; > }; > > +&i2srx { > + pinctrl-names = "default"; > + pinctrl-0 = <&i2srx_pins>; > + status = "okay"; > +}; > + > +&i2stx0 { > + pinctrl-names = "default"; > + pinctrl-0 = <&mclk_ext_pins>; > + status = "okay"; > +}; > + > +&i2stx1 { > + pinctrl-names = "default"; > + pinctrl-0 = <&i2stx1_pins>; > + status = "okay"; > +}; > + > &mmc0 { > max-frequency = <100000000>; > bus-width = <8>; > @@ -337,6 +355,46 @@ GPOEN_SYS_I2C6_DATA, > }; > }; > > + i2srx_pins: i2srx-0 { > + clk-sd-pins { > + pinmux = + GPOEN_DISABLE, > + GPI_SYS_I2SRX_BCLK)>, > + + GPOEN_DISABLE, > + GPI_SYS_I2SRX_LRCK)>, > + + GPOEN_DISABLE, > + GPI_SYS_I2STX1_BCLK)>, > + + GPOEN_DISABLE, > + GPI_SYS_I2STX1_LRCK)>, > + + GPOEN_DISABLE, > + GPI_SYS_I2SRX_SDIN0)>; > + input-enable; > + }; > + }; > + > + i2stx1_pins: i2stx1-0 { > + sd-pins { > + pinmux = + GPOEN_ENABLE, > + GPI_NONE)>; > + bias-disable; > + input-disable; > + }; > + }; > + > + mclk_ext_pins: mclk-ext-0 { > + mclk-ext-pins { > + pinmux = + GPOEN_DISABLE, > + GPI_SYS_MCLK_EXT)>; > + input-enable; > + }; > + }; > + > mmc0_pins: mmc0-0 { > rst-pins { > pinmux = diff --git a/arch/riscv/boot/dts/starfive/jh7110.dtsi b/arch/riscv/boot/dts/starfive/jh7110.dtsi > index e85464c328d0..621b68c02ea8 100644 > --- a/arch/riscv/boot/dts/starfive/jh7110.dtsi > +++ b/arch/riscv/boot/dts/starfive/jh7110.dtsi > @@ -512,6 +512,30 @@ tdm: tdm@10090000 { > status = "disabled"; > }; > > + i2srx: i2s@100e0000 { > + compatible = "starfive,jh7110-i2srx"; > + reg = <0x0 0x100e0000 0x0 0x1000>; > + clocks = <&syscrg JH7110_SYSCLK_I2SRX_BCLK_MST>, > + <&syscrg JH7110_SYSCLK_I2SRX_APB>, > + <&syscrg JH7110_SYSCLK_MCLK>, > + <&syscrg JH7110_SYSCLK_MCLK_INNER>, > + <&mclk_ext>, > + <&syscrg JH7110_SYSCLK_I2SRX_BCLK>, > + <&syscrg JH7110_SYSCLK_I2SRX_LRCK>, > + <&i2srx_bclk_ext>, > + <&i2srx_lrck_ext>; > + clock-names = "i2sclk", "apb", "mclk", > + "mclk_inner", "mclk_ext", "bclk", > + "lrck", "bclk_ext", "lrck_ext"; > + resets = <&syscrg JH7110_SYSRST_I2SRX_APB>, > + <&syscrg JH7110_SYSRST_I2SRX_BCLK>; > + dmas = <0>, <&dma 24>; > + dma-names = "tx", "rx"; > + starfive,syscon = <&sys_syscon 0x18 0x2>; > + #sound-dai-cells = <0>; > + status = "disabled"; > + }; > + > usb0: usb@10100000 { > compatible = "starfive,jh7110-usb"; > ranges = <0x0 0x0 0x10100000 0x100000>; > @@ -736,6 +760,47 @@ spi6: spi@120a0000 { > status = "disabled"; > }; > > + i2stx0: i2s@120b0000 { > + compatible = "starfive,jh7110-i2stx0"; > + reg = <0x0 0x120b0000 0x0 0x1000>; > + clocks = <&syscrg JH7110_SYSCLK_I2STX0_BCLK_MST>, > + <&syscrg JH7110_SYSCLK_I2STX0_APB>, > + <&syscrg JH7110_SYSCLK_MCLK>, > + <&syscrg JH7110_SYSCLK_MCLK_INNER>, > + <&mclk_ext>; > + clock-names = "i2sclk", "apb", "mclk", > + "mclk_inner","mclk_ext"; > + resets = <&syscrg JH7110_SYSRST_I2STX0_APB>, > + <&syscrg JH7110_SYSRST_I2STX0_BCLK>; > + dmas = <&dma 47>; > + dma-names = "tx"; > + #sound-dai-cells = <0>; > + status = "disabled"; > + }; > + > + i2stx1: i2s@120c0000 { > + compatible = "starfive,jh7110-i2stx1"; > + reg = <0x0 0x120c0000 0x0 0x1000>; > + clocks = <&syscrg JH7110_SYSCLK_I2STX1_BCLK_MST>, > + <&syscrg JH7110_SYSCLK_I2STX1_APB>, > + <&syscrg JH7110_SYSCLK_MCLK>, > + <&syscrg JH7110_SYSCLK_MCLK_INNER>, > + <&mclk_ext>, > + <&syscrg JH7110_SYSCLK_I2STX1_BCLK>, > + <&syscrg JH7110_SYSCLK_I2STX1_LRCK>, > + <&i2stx_bclk_ext>, > + <&i2stx_lrck_ext>; > + clock-names = "i2sclk", "apb", "mclk", > + "mclk_inner", "mclk_ext", "bclk", > + "lrck", "bclk_ext", "lrck_ext"; > + resets = <&syscrg JH7110_SYSRST_I2STX1_APB>, > + <&syscrg JH7110_SYSRST_I2STX1_BCLK>; > + dmas = <&dma 48>; > + dma-names = "tx"; > + #sound-dai-cells = <0>; > + status = "disabled"; > + }; > + > sfctemp: temperature-sensor@120e0000 { > compatible = "starfive,jh7110-temp"; > reg = <0x0 0x120e0000 0x0 0x10000>; Reviewed-by: Walker Chen Thanks!