From: Lorenzo Bianconi <lorenzo@kernel.org>
To: linux-phy@lists.infradead.org
Cc: vkoul@kernel.org, kishon@kernel.org,
lorenzo.bianconi83@gmail.com, conor@kernel.org,
linux-arm-kernel@lists.infradead.org, robh+dt@kernel.org,
krzysztof.kozlowski+dt@linaro.org, conor+dt@kernel.org,
devicetree@vger.kernel.org, nbd@nbd.name, john@phrozen.org,
dd@embedd.com, catalin.marinas@arm.com, will@kernel.org,
upstream@airoha.com, angelogioacchino.delregno@collabora.com,
amitsinght@marvell.com
Subject: [PATCH v4 1/3] dt-bindings: phy: airoha: Add PCIe PHY controller
Date: Sat, 15 Jun 2024 23:15:41 +0200 [thread overview]
Message-ID: <656133f865433c1d02f00a3abbb1aa9312d2a24e.1718485860.git.lorenzo@kernel.org> (raw)
In-Reply-To: <cover.1718485860.git.lorenzo@kernel.org>
Introduce device-tree binding documentation for Airoha EN7581 PCIe PHY
controller.
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Signed-off-by: Lorenzo Bianconi <lorenzo@kernel.org>
---
.../bindings/phy/airoha,en7581-pcie-phy.yaml | 58 +++++++++++++++++++
1 file changed, 58 insertions(+)
create mode 100644 Documentation/devicetree/bindings/phy/airoha,en7581-pcie-phy.yaml
diff --git a/Documentation/devicetree/bindings/phy/airoha,en7581-pcie-phy.yaml b/Documentation/devicetree/bindings/phy/airoha,en7581-pcie-phy.yaml
new file mode 100644
index 000000000000..e26c30d17ff0
--- /dev/null
+++ b/Documentation/devicetree/bindings/phy/airoha,en7581-pcie-phy.yaml
@@ -0,0 +1,58 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/phy/airoha,en7581-pcie-phy.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Airoha EN7581 PCI-Express PHY
+
+maintainers:
+ - Lorenzo Bianconi <lorenzo@kernel.org>
+
+description:
+ The PCIe PHY supports physical layer functionality for PCIe Gen2/Gen3 port.
+
+properties:
+ compatible:
+ const: airoha,en7581-pcie-phy
+
+ reg:
+ items:
+ - description: PCIE analog base address
+ - description: PCIE lane0 base address
+ - description: PCIE lane1 base address
+
+ reg-names:
+ items:
+ - const: csr-2l
+ - const: pma0
+ - const: pma1
+
+ "#phy-cells":
+ const: 0
+
+required:
+ - compatible
+ - reg
+ - reg-names
+ - "#phy-cells"
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/phy/phy.h>
+
+ soc {
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ phy@11e80000 {
+ compatible = "airoha,en7581-pcie-phy";
+ #phy-cells = <0>;
+ reg = <0x0 0x1fa5a000 0x0 0xfff>,
+ <0x0 0x1fa5b000 0x0 0xfff>,
+ <0x0 0x1fa5c000 0x0 0xfff>;
+ reg-names = "csr-2l", "pma0", "pma1";
+ };
+ };
--
2.45.1
next prev parent reply other threads:[~2024-06-15 21:16 UTC|newest]
Thread overview: 5+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-06-15 21:15 [PATCH v4 0/3] Introduce PCIe PHY driver for EN7581 SoC Lorenzo Bianconi
2024-06-15 21:15 ` Lorenzo Bianconi [this message]
2024-06-15 21:15 ` [PATCH v4 2/3] phy: airoha: Add " Lorenzo Bianconi
2024-06-15 21:15 ` [PATCH v4 3/3] arm64: defconfig: Enable Airoha pcie phy driver Lorenzo Bianconi
2024-06-20 16:38 ` (subset) [PATCH v4 0/3] Introduce PCIe PHY driver for EN7581 SoC Vinod Koul
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