From: Krzysztof Kozlowski <krzk@kernel.org>
To: Bjorn Andersson <andersson@kernel.org>
Cc: "Jyothi Kumar Seerapu" <quic_jseerapu@quicinc.com>,
"Vinod Koul" <vkoul@kernel.org>, "Rob Herring" <robh@kernel.org>,
"Krzysztof Kozlowski" <krzk+dt@kernel.org>,
"Conor Dooley" <conor+dt@kernel.org>,
"Konrad Dybcio" <konradybcio@kernel.org>,
"Andi Shyti" <andi.shyti@kernel.org>,
"Sumit Semwal" <sumit.semwal@linaro.org>,
"Christian König" <christian.koenig@amd.com>,
cros-qcom-dts-watchers@chromium.org,
linux-arm-msm@vger.kernel.org, dmaengine@vger.kernel.org,
devicetree@vger.kernel.org, linux-kernel@vger.kernel.org,
linux-i2c@vger.kernel.org, linux-media@vger.kernel.org,
dri-devel@lists.freedesktop.org, linaro-mm-sig@lists.linaro.org,
quic_msavaliy@quicinc.com, quic_vtanuku@quicinc.com
Subject: Re: [PATCH v1 2/5] arm64: dts: qcom: Add support for configuring channel TRE size
Date: Thu, 17 Oct 2024 09:10:39 +0200 [thread overview]
Message-ID: <658c19c7-9eeb-4329-aa96-a4a9b09d7117@kernel.org> (raw)
In-Reply-To: <7e7ksit5ptjrcnct66v75mbxuabnzzloungockdal2dl2y6nn5@ge4mrsjmd746>
On 16/10/2024 16:35, Bjorn Andersson wrote:
>>> @@ -1064,7 +1064,7 @@
>>> };
>>>
>>> gpi_dma0: dma-controller@900000 {
>>> - #dma-cells = <3>;
>>> + #dma-cells = <4>;
>>> compatible = "qcom,sc7280-gpi-dma", "qcom,sm6350-gpi-dma";
>>> reg = <0 0x00900000 0 0x60000>;
>>> interrupts = <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>,
>>> @@ -1114,8 +1114,8 @@
>>> "qup-memory";
>>> power-domains = <&rpmhpd SC7280_CX>;
>>> required-opps = <&rpmhpd_opp_low_svs>;
>>> - dmas = <&gpi_dma0 0 0 QCOM_GPI_I2C>,
>>> - <&gpi_dma0 1 0 QCOM_GPI_I2C>;
>>> + dmas = <&gpi_dma0 0 0 QCOM_GPI_I2C 64>,
>>> + <&gpi_dma0 1 0 QCOM_GPI_I2C 64>;
>>
>> So everywhere is 64, thus this is fixed. Deduce it from the compatible
>>
>
> If I understand correctly, it's a software tunable property, used to
> balance how many TRE elements that should be preallocated.
>
> If so, it would not be a property of the hardware/compatible, but rather
> a result of profiling and a balance between memory "waste" and
> performance.
In such case I would prefer it being runtime-calculated by the driver,
based on frequency or expected bandwidth.
And in any case if this is about to stay, having here default values
means all upstream users don't need it. What's not upstream, does not
exist in such context. We don't add features which are not used by upstream.
Best regards,
Krzysztof
next prev parent reply other threads:[~2024-10-17 7:10 UTC|newest]
Thread overview: 27+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-10-15 12:07 [PATCH v1 0/5] Add Block event interrupt support for I2C protocol Jyothi Kumar Seerapu
2024-10-15 12:07 ` [PATCH v1 1/5] dt-bindings: dmaengine: qcom: gpi: Add additional arg to dma-cell property Jyothi Kumar Seerapu
2024-10-15 13:26 ` Rob Herring (Arm)
2024-10-28 5:57 ` Jyothi Kumar Seerapu
2024-10-15 13:31 ` Krzysztof Kozlowski
2024-10-25 18:11 ` Jyothi Kumar Seerapu
2024-10-15 14:01 ` Rob Herring
2024-10-28 5:38 ` Jyothi Kumar Seerapu
2024-10-16 4:54 ` Vinod Koul
2024-10-25 18:25 ` Jyothi Kumar Seerapu
2024-10-28 5:50 ` Jyothi Kumar Seerapu
2024-10-15 12:07 ` [PATCH v1 2/5] arm64: dts: qcom: Add support for configuring channel TRE size Jyothi Kumar Seerapu
2024-10-15 13:33 ` Krzysztof Kozlowski
2024-10-16 14:35 ` Bjorn Andersson
2024-10-17 7:10 ` Krzysztof Kozlowski [this message]
2024-10-28 5:34 ` Jyothi Kumar Seerapu
2024-10-15 12:07 ` [PATCH v1 3/5] dmaengine: qcom: gpi: Add provision to support TRE size as the fourth argument of dma-cells property Jyothi Kumar Seerapu
2024-10-25 18:17 ` Konrad Dybcio
2024-10-28 6:32 ` Jyothi Kumar Seerapu
2024-10-15 12:07 ` [PATCH v1 4/5] dmaengine: qcom: gpi: Add GPI Block event interrupt support Jyothi Kumar Seerapu
2024-10-15 12:07 ` [PATCH v1 5/5] i2c: i2c-qcom-geni: Add " Jyothi Kumar Seerapu
2024-10-16 15:06 ` Andi Shyti
2024-10-28 6:04 ` Jyothi Kumar Seerapu
2024-10-18 22:11 ` kernel test robot
2024-10-28 6:07 ` Jyothi Kumar Seerapu
2024-10-19 3:12 ` kernel test robot
2024-10-28 6:06 ` Jyothi Kumar Seerapu
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