From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 7B8E4155A24; Thu, 17 Oct 2024 07:10:47 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1729149047; cv=none; b=nG+OxUrbhaj/F2VwcnuXnAVEpakeFs7bXLte3cdjLM/gzhObxHE1+6LRDFeuwVM9ceLXEssoZSXEWZQzpsxe4xDX9JJtolNipfBfHbej2CPXICpydUxCpvggh5VTFg3S4bI0UuvFaFVUCdkAea+4966llvAvCpc1yuOBkAaaj74= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1729149047; c=relaxed/simple; bh=szqZuOUBSNoFodxJ4PIlXC02tAIat2KqHOjusZ/IS1U=; h=Message-ID:Date:MIME-Version:Subject:To:Cc:References:From: In-Reply-To:Content-Type; b=SM8sNn+ruj0VB4yu7Zw+Gp4j9ZG3iHratYBJUGtrkp3N/N3gctVdObSgE52kvLsblyivc3+q/GdgN4I7o87Pu5TYOQpY4Zya592Y/P9oPZ7YtPccQ3+gojwosKJ/6+kC3dRjbd/pYvmjpbpEYhF41PQ2e6vAT0WrCLwVv19k8Q0= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=qqUZj5+2; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="qqUZj5+2" Received: by smtp.kernel.org (Postfix) with ESMTPSA id A09DDC4CEC5; Thu, 17 Oct 2024 07:10:41 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1729149047; bh=szqZuOUBSNoFodxJ4PIlXC02tAIat2KqHOjusZ/IS1U=; h=Date:Subject:To:Cc:References:From:In-Reply-To:From; b=qqUZj5+2IgXcByOugwIFfstUYe58eZNDbIdMvl4t0W8Wa49IYPVCrRimCEmlv0oyJ R7nM/+U5UYbej8nkoJl/9jQ+d3kPAHN/K/CMkqWHzAffcrExJfihXUasomOMmYGs4d vLpEMD3doesEG8LbEFxjfo1vs+tQH3lkgvDLoiwgcLdULb40xj1l0rZkTfoCzyfqFq ALTssMMxbRhqe3DjXClgPQ90q0kpQAEVdLrIRTqHGTgqJMHI2jW5XgqTCZwfmxabEP LOekFXQX2ii94stBnl/1apNHxgPf19oKx+CKTjewyD+PWThsHbzQVeRpdVajbHmyCN Mv/wIzit91xKQ== Message-ID: <658c19c7-9eeb-4329-aa96-a4a9b09d7117@kernel.org> Date: Thu, 17 Oct 2024 09:10:39 +0200 Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v1 2/5] arm64: dts: qcom: Add support for configuring channel TRE size To: Bjorn Andersson Cc: Jyothi Kumar Seerapu , Vinod Koul , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Konrad Dybcio , Andi Shyti , Sumit Semwal , =?UTF-8?Q?Christian_K=C3=B6nig?= , cros-qcom-dts-watchers@chromium.org, linux-arm-msm@vger.kernel.org, dmaengine@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-i2c@vger.kernel.org, linux-media@vger.kernel.org, dri-devel@lists.freedesktop.org, linaro-mm-sig@lists.linaro.org, quic_msavaliy@quicinc.com, quic_vtanuku@quicinc.com References: <20241015120750.21217-1-quic_jseerapu@quicinc.com> <20241015120750.21217-3-quic_jseerapu@quicinc.com> <78a1c5c8-53c8-4144-b311-c34b155ca27c@kernel.org> <7e7ksit5ptjrcnct66v75mbxuabnzzloungockdal2dl2y6nn5@ge4mrsjmd746> From: Krzysztof Kozlowski Content-Language: en-US Autocrypt: addr=krzk@kernel.org; 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charset=UTF-8 Content-Transfer-Encoding: 7bit On 16/10/2024 16:35, Bjorn Andersson wrote: >>> @@ -1064,7 +1064,7 @@ >>> }; >>> >>> gpi_dma0: dma-controller@900000 { >>> - #dma-cells = <3>; >>> + #dma-cells = <4>; >>> compatible = "qcom,sc7280-gpi-dma", "qcom,sm6350-gpi-dma"; >>> reg = <0 0x00900000 0 0x60000>; >>> interrupts = , >>> @@ -1114,8 +1114,8 @@ >>> "qup-memory"; >>> power-domains = <&rpmhpd SC7280_CX>; >>> required-opps = <&rpmhpd_opp_low_svs>; >>> - dmas = <&gpi_dma0 0 0 QCOM_GPI_I2C>, >>> - <&gpi_dma0 1 0 QCOM_GPI_I2C>; >>> + dmas = <&gpi_dma0 0 0 QCOM_GPI_I2C 64>, >>> + <&gpi_dma0 1 0 QCOM_GPI_I2C 64>; >> >> So everywhere is 64, thus this is fixed. Deduce it from the compatible >> > > If I understand correctly, it's a software tunable property, used to > balance how many TRE elements that should be preallocated. > > If so, it would not be a property of the hardware/compatible, but rather > a result of profiling and a balance between memory "waste" and > performance. In such case I would prefer it being runtime-calculated by the driver, based on frequency or expected bandwidth. And in any case if this is about to stay, having here default values means all upstream users don't need it. What's not upstream, does not exist in such context. We don't add features which are not used by upstream. Best regards, Krzysztof