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[212.114.21.58]) by smtp.gmail.com with ESMTPSA id u11-20020adfdd4b000000b003143765e207sm1899030wrm.49.2023.07.03.00.24.24 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Mon, 03 Jul 2023 00:24:27 -0700 (PDT) Message-ID: <65d78d07-be4f-8ea0-b322-353b5c23fcb0@linaro.org> Date: Mon, 3 Jul 2023 09:24:23 +0200 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:102.0) Gecko/20100101 Thunderbird/102.12.0 From: Neil Armstrong Reply-To: neil.armstrong@linaro.org Subject: Re: [PATCH v6 5/9] drm/meson: gate px_clk when setting rate Content-Language: en-US To: George Stark , Jerome Brunet , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Kevin Hilman , Martin Blumenstingl , David Airlie , Daniel Vetter , Jagan Teki , Nicolas Belin Cc: linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-amlogic@lists.infradead.org, linux-arm-kernel@lists.infradead.org, dri-devel@lists.freedesktop.org References: <20230512-amlogic-v6-4-upstream-dsi-ccf-vim3-v6-0-fd2ac9845472@linaro.org> <20230512-amlogic-v6-4-upstream-dsi-ccf-vim3-v6-5-fd2ac9845472@linaro.org> Organization: Linaro Developer Services In-Reply-To: Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 8bit Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org On 30/06/2023 20:10, George Stark wrote: > Hello Neil > > On 6/30/23 19:29, Neil Armstrong wrote: >> Disable the px_clk when setting the rate to recover a fully >> configured and correctly reset VCLK clock tree after the rate >> is set. >> >> Fixes: 77d9e1e6b846 ("drm/meson: add support for MIPI-DSI transceiver") >> Signed-off-by: Neil Armstrong >> --- >>   drivers/gpu/drm/meson/meson_dw_mipi_dsi.c | 7 +++++++ >>   1 file changed, 7 insertions(+) >> >> diff --git a/drivers/gpu/drm/meson/meson_dw_mipi_dsi.c b/drivers/gpu/drm/meson/meson_dw_mipi_dsi.c >> index 57447abf1a29..dc63d2d813a9 100644 >> --- a/drivers/gpu/drm/meson/meson_dw_mipi_dsi.c >> +++ b/drivers/gpu/drm/meson/meson_dw_mipi_dsi.c >> @@ -94,6 +94,7 @@ static int dw_mipi_dsi_phy_init(void *priv_data) >>           return ret; >>       } >> +    clk_disable_unprepare(mipi_dsi->px_clk); >>       ret = clk_set_rate(mipi_dsi->px_clk, mipi_dsi->mode->clock * 1000); >>       if (ret) { >> @@ -102,6 +103,12 @@ static int dw_mipi_dsi_phy_init(void *priv_data) >>           return ret; >>       } >> +    clk_prepare_enable(mipi_dsi->px_clk); > probably should be: > ret = clk_prepare_enable(mipi_dsi->px_clk); Indeed, thx for noticing :-) >> +    if (ret) { >> +        dev_err(mipi_dsi->dev, "Failed to enable DSI Pixel clock (ret %d)\n", ret); >> +        return ret; >> +    } >> + >>       switch (mipi_dsi->dsi_device->format) { >>       case MIPI_DSI_FMT_RGB888: >>           dpi_data_format = DPI_COLOR_24BIT; >>