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Fri, 10 Nov 2023 04:27:39 -0800 (PST) Received: from [192.168.1.20] ([178.197.218.126]) by smtp.gmail.com with ESMTPSA id d14-20020a05600c34ce00b00406443c8b4fsm5028154wmq.19.2023.11.10.04.27.37 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Fri, 10 Nov 2023 04:27:38 -0800 (PST) Message-ID: <66173ccd-4478-4622-a386-557a8d35102f@linaro.org> Date: Fri, 10 Nov 2023 13:27:36 +0100 Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v7 2/4] pwm: opencores: Add PWM driver support Content-Language: en-US To: William Qiu , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org, linux-pwm@vger.kernel.org Cc: Emil Renner Berthing , Rob Herring , Thierry Reding , Philipp Zabel , Krzysztof Kozlowski , Conor Dooley , =?UTF-8?Q?Uwe_Kleine-K=C3=B6nig?= , Hal Feng , Paul Walmsley , Palmer Dabbelt , Albert Ou References: <20231110062039.103339-1-william.qiu@starfivetech.com> <20231110062039.103339-3-william.qiu@starfivetech.com> From: Krzysztof Kozlowski Autocrypt: addr=krzysztof.kozlowski@linaro.org; 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charset=UTF-8 Content-Transfer-Encoding: 7bit On 10/11/2023 07:20, William Qiu wrote: > Add Pulse Width Modulation driver support for OpenCores. What is OpenCores? Why all your commit messages lack basic explanation of the hardware you are working on? > > +static const struct ocores_pwm_data jh7100_pwm_data = { > + .get_ch_base = starfive_jh71x0_get_ch_base, > +}; > + > +static const struct ocores_pwm_data jh7110_pwm_data = { > + .get_ch_base = starfive_jh71x0_get_ch_base, > +}; > + > +static const struct of_device_id ocores_pwm_of_match[] = { > + { .compatible = "opencores,pwm" }, > + { .compatible = "starfive,jh7100-pwm", .data = &jh7100_pwm_data}, > + { .compatible = "starfive,jh7110-pwm", .data = &jh7110_pwm_data}, Your bindings say something entirely else. I don't understand what is happening with this patchset. > + { /* sentinel */ } > +}; ... > + ddata->regs = devm_platform_ioremap_resource(pdev, 0); > + if (IS_ERR(ddata->regs)) > + return dev_err_probe(dev, PTR_ERR(ddata->regs), > + "Unable to map IO resources\n"); > + > + ddata->clk = devm_clk_get(dev, NULL); > + if (IS_ERR(ddata->clk)) > + return dev_err_probe(dev, PTR_ERR(ddata->clk), > + "Unable to get pwm's clock\n"); > + > + ret = clk_prepare_enable(ddata->clk); > + if (ret) > + return dev_err_probe(dev, ret, "Clock enable failed\n"); dev_clk_get_enabled() or whatever the API is called > + > + ddata->rst = devm_reset_control_get_optional_exclusive(dev, NULL); > + reset_control_deassert(ddata->rst); > + > + ddata->clk_rate = clk_get_rate(ddata->clk); > + if (ddata->clk_rate <= 0) > + return dev_err_probe(dev, ddata->clk_rate, > + "Unable to get clock's rate\n"); > + > + ret = devm_pwmchip_add(dev, chip); > + if (ret < 0) { > + dev_err_probe(dev, ret, "Could not register PWM chip\n"); > + clk_disable_unprepare(ddata->clk); > + reset_control_assert(ddata->rst); return dev_err_probe > + } > + > + platform_set_drvdata(pdev, ddata); > + > + return ret; > +} > + > +static void ocores_pwm_remove(struct platform_device *dev) > +{ > + struct ocores_pwm_device *ddata = platform_get_drvdata(dev); > + > + reset_control_assert(ddata->rst); > + clk_disable_unprepare(ddata->clk); You have confusing order of cleanups. It's like random, once clock then reset, in other place reset then clock. Best regards, Krzysztof