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Mon, 25 May 2026 00:06:43 -0700 (PDT) X-Received: by 2002:a05:6a00:22c6:b0:836:900e:8743 with SMTP id d2e1a72fcca58-8415f35d58amr13665874b3a.36.1779692802978; Mon, 25 May 2026 00:06:42 -0700 (PDT) Received: from [10.218.5.182] ([202.46.22.19]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-84164fbb66bsm8423647b3a.45.2026.05.25.00.06.38 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Mon, 25 May 2026 00:06:42 -0700 (PDT) Message-ID: <66335474-d600-45ab-9ac6-e946f24142c8@oss.qualcomm.com> Date: Mon, 25 May 2026 12:36:36 +0530 Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v4 2/3] clk: qcom: camcc-glymur: Add camera clock controller driver To: Bryan O'Donoghue , Bjorn Andersson , Michael Turquette , Stephen Boyd , Brian Masney , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Konrad Dybcio Cc: linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Taniya Das , Konrad Dybcio References: <20260517-glymur_camcc-v4-0-9d00acffdbf7@oss.qualcomm.com> <20260517-glymur_camcc-v4-2-9d00acffdbf7@oss.qualcomm.com> <8bd4365e-0171-425c-9738-0b186047cb15@kernel.org> <2a496bdf-4728-47b9-84ba-063712a6e5b6@oss.qualcomm.com> <0a197b43-a672-4849-91c7-6e5bfe3175f7@kernel.org> Content-Language: en-US From: Jagadeesh Kona In-Reply-To: <0a197b43-a672-4849-91c7-6e5bfe3175f7@kernel.org> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwNTI1MDA2OSBTYWx0ZWRfX5n/J5KqfuGUb TK31t+cZo8hW6bvRPRtWxH3nRkMGsx3Ztqpisb0YPIpuvM8+Hl6rAjxJLMbYaKR5IXS+Uf9MgVp fJlMzPl3iFxXbM2aVlC2VNcpYGpjCpzxJQFfNQULMcKyKc3Fn7fsGAujP93ORY8svONDonYC3nF AAB/QUETdO6hd5UcW4vVwqxBU/pHyd+x8hvzp8wbXQ2mgLqTiRUiTPMUNQzhM8Vn3dtZm/9re2F zu9vzsTtm5X6SWF8WmcFFhxd7nTRGrqnw23L1V9HGYSIYldY//i1F40huhqN8Y3w5po578R8ek+ fdyQQbaXzHm5KXlHFRg7IoGa6UzLD840Vwg3MfhTAU6IBRQ5MWkpZdzapEh1xs5uLlYqrNcQWxB ns8XKdEZUX7hL94j4wnvmqbpNJtSk9UlXE06TrlJPh/XpdpDu06Ekt74ebzw+lCvxxTyDbBzZKv GLJ+lsslR1A3lqO/W3A== X-Proofpoint-ORIG-GUID: u-LYElcCtglBjjFRLXOgx-kfJk3SLzvm X-Authority-Analysis: v=2.4 cv=cN3QdFeN c=1 sm=1 tr=0 ts=6a13f504 cx=c_pps a=m5Vt/hrsBiPMCU0y4gIsQw==:117 a=fChuTYTh2wq5r3m49p7fHw==:17 a=IkcTkHD0fZMA:10 a=NGcC8JguVDcA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=rJkE3RaqiGZ5pbrm-msn:22 a=VwQbUJbxAAAA:8 a=EUspDBNiAAAA:8 a=tk3pCZAdYsx0TBu0sJAA:9 a=3ZKOabzyN94A:10 a=QEXdDO2ut3YA:10 a=IoOABgeZipijB_acs4fv:22 X-Proofpoint-GUID: u-LYElcCtglBjjFRLXOgx-kfJk3SLzvm X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.51,FMLib:17.12.100.49 definitions=2026-05-25_02,2026-05-18_01,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 malwarescore=0 suspectscore=0 adultscore=0 priorityscore=1501 phishscore=0 spamscore=0 bulkscore=0 lowpriorityscore=0 impostorscore=0 clxscore=1015 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2605130000 definitions=main-2605250069 On 5/18/2026 5:51 PM, Bryan O'Donoghue wrote: > On 18/05/2026 11:23, Jagadeesh Kona wrote: >> >> >> On 5/18/2026 1:05 PM, Bryan O'Donoghue wrote: >>> On 17/05/2026 18:33, Jagadeesh Kona wrote: >>>> +/* 1200.0 MHz Configuration */ >>>> +static const struct alpha_pll_config cam_cc_pll0_config = { >>>> +    .l = 0x3e, >>>> +    .alpha = 0x8000, >>>> +    .config_ctl_val = 0x25c400e7, >>>> +    .config_ctl_hi_val = 0x0a8060e0, >>>> +    .config_ctl_hi1_val = 0xf51dea20, >>>> +    .user_ctl_val = 0x00008408, >>>> +    .user_ctl_hi_val = 0x00000002, >>>> +}; >>> >>> I'll again push back on these magic numbers. >>> >>> At the very least you should be mentioning in the cover letter log why you _aren't_ making that change. >>> >>> Just reposting and hoping it slips by the person making the comment isn't too cool. >>> >>> Why can't qcom update the python? script that generates this code to enumerate fields instead of magic numbers here ? >>> >>> I get you don't want to do it but, just ignoring the review feedback is no OK. >>> >>> What gives ? >>> >> >> Hi Bryan, >> >> I haven't ignored your comments & already responded to your earlier comment on why the bit fields are not >> defined. Most of these values are static settings we get from PLL HW team and we program them only once >> as is during bootup and are never reused again anywhere from PLL code, so these bits are not defined. >> >> Please find the earlier responses for your comments below: >> https://lore.kernel.org/all/b92a2cbb-fe8d-4378-aa02-d91e2e4dfff4@oss.qualcomm.com/ >> https://lore.kernel.org/all/009ecdbb-2297-44eb-862d-233e3290691c@oss.qualcomm.com/ >> >> Thanks, >> Jagadeesh > > That's not in your overview letter so generally I'd advise to include things like "did X because Y" - "didn't do Q because Z" anyway, how does it make a difference if the values are static ? > > They are no less magic numbers that way. > > What exactly is the resistance to defining the bits ? > > I'll state again - when a vendor is submitting something upstream where that vendor 100% controls their own documentation - there's no reason at all to be presenting magic hex numbers - even more the case with generated code. > > Just update the script to enumerate the bit fields, I honestly don't get the aversion. > Hi Bryan, There’s no standard interface for these bits, and bit definitions/fields vary across PLL types. So, common macros aren’t feasible and would need redefinitions per controller. Since these bits are not reused elsewhere, IMO directly using values from the hardware documentation keeps the implementation simpler, avoids unnecessary abstraction, and makes debugging—through direct comparison with the hardware spec easier. Thanks, Jagadeesh