[RFC PATCH 0/6] arm64: dts: qcom: Introduce AIM500 platform device tree

[RFC PATCH 0/6] arm64: dts: qcom: Introduce AIM500 platform device tree

[Jingyi Wang]

Add the device tree for the AIM500 AIoT board along with usb, regulators,
serial and PCIe found in this board.

AIM500 Series is a highly optimized family of modules designed to support
AIoT and Generative AI applications which is based on SM8650P soc with
addtional functions like PMIC and bluetooth. And AIM500 AIoT is mounted
onto Qualcomm AIoT carrier board to support verification, evaluation and
development.

Signed-off-by: Jingyi Wang <quic_jingyw@quicinc.com>
---

This patch series has some open discussion topics depend on [1], including:
1. memory map will have a large reserved region for firmware related,
   since currently firmware features are still in developing and easily to
   be changed.
2. vph_pwr was open whether it should be put in som.dtsi, or board.dts. we
   can see vph_pwr may have different design and implementation from
   different boards design, while vph_pwr needed to be one of the som input,
   and then the vph_pwr is used inside som to different pmics input. So we
   proposed have the definition in som.dtsi, and have it's own implementation
   in board.dts.
3. board compatible like aim300-aiot was open whether can be added or not.
   We added currently since it will fail dt binding check if not.

[1] https://lore.kernel.org/linux-arm-msm/20240119100621.11788-1-quic_tengfan@quicinc.com/#t

And we got following error while doing dtb check:
sm8650p-aim500-aiot.dtb: usb@a6f8800: interrupt-names: ['hs_phy_irq', 'ss_phy_irq', 'dm_hs_phy_irq', 'dp_hs_phy_irq'] is too short
Which should be caused by missing intertupt name "pwr_event" in sm8650.dtsi

Jingyi Wang (6):
  dt-bindings: arm: qcom: Document sm8650p soc and AIM500 AIoT board
  dt-bindings: arm: qcom,ids: Add SoC ID for SM8650P
  soc: qcom: socinfo: Add SM8650P SoC ID table entry
  arm64: dts: qcom: sm8650p: introduce sm8650p dtsi
  arm64: dts: qcom: add base AIM500 dtsi
  arm64: dts: qcom: add AIM500 AIoT

 .../devicetree/bindings/arm/qcom.yaml         |   9 +
 arch/arm64/boot/dts/qcom/Makefile             |   1 +
 .../boot/dts/qcom/sm8650p-aim500-aiot.dts     | 314 ++++++++++++++
 arch/arm64/boot/dts/qcom/sm8650p-aim500.dtsi  | 409 ++++++++++++++++++
 arch/arm64/boot/dts/qcom/sm8650p.dtsi         | 180 ++++++++
 drivers/soc/qcom/socinfo.c                    |   1 +
 include/dt-bindings/arm/qcom,ids.h            |   1 +
 7 files changed, 915 insertions(+)
 create mode 100644 arch/arm64/boot/dts/qcom/sm8650p-aim500-aiot.dts
 create mode 100644 arch/arm64/boot/dts/qcom/sm8650p-aim500.dtsi
 create mode 100644 arch/arm64/boot/dts/qcom/sm8650p.dtsi

--
base-commit: 076d56d74f17e625b3d63cf4743b3d7d02180379 
2.25.1

[RFC PATCH 1/6] dt-bindings: arm: qcom: Document sm8650p soc and AIM500 AIoT board

[Jingyi Wang]

Document Qualcomm SM8650P SoC and AIM500 AIoT board.

Signed-off-by: Jingyi Wang <quic_jingyw@quicinc.com>
---
 Documentation/devicetree/bindings/arm/qcom.yaml | 9 +++++++++
 1 file changed, 9 insertions(+)

diff --git a/Documentation/devicetree/bindings/arm/qcom.yaml b/Documentation/devicetree/bindings/arm/qcom.yaml
index 1999a5f2f254..e87ceb42853b 100644
--- a/Documentation/devicetree/bindings/arm/qcom.yaml
+++ b/Documentation/devicetree/bindings/arm/qcom.yaml
@@ -88,11 +88,13 @@ description: |
         sm8450
         sm8550
         sm8650
+        sm8650p
         x1e80100
 
   The 'board' element must be one of the following strings:
 
         adp
+        aim500-aiot
         cdp
         dragonboard
         idp
@@ -1051,6 +1053,13 @@ properties:
               - qcom,sm8650-qrd
           - const: qcom,sm8650
 
+      - items:
+          - enum:
+              - qcom,sm8650p-aim500-aiot
+          - const: qcom,sm8650p-aim500
+          - const: qcom,sm8650p
+          - const: qcom,sm8650
+
       - items:
           - enum:
               - qcom,x1e80100-crd
-- 
2.25.1

[RFC PATCH 2/6] dt-bindings: arm: qcom,ids: Add SoC ID for SM8650P

[Jingyi Wang]

Add the ID for the Qualcomm SM8650P SoC.

Signed-off-by: Jingyi Wang <quic_jingyw@quicinc.com>
---
 include/dt-bindings/arm/qcom,ids.h | 1 +
 1 file changed, 1 insertion(+)

diff --git a/include/dt-bindings/arm/qcom,ids.h b/include/dt-bindings/arm/qcom,ids.h
index dc7ba87b50d7..22559fe3891f 100644
--- a/include/dt-bindings/arm/qcom,ids.h
+++ b/include/dt-bindings/arm/qcom,ids.h
@@ -257,6 +257,7 @@
 #define QCOM_ID_QDU1000			545
 #define QCOM_ID_SM8650			557
 #define QCOM_ID_SM4450			568
+#define QCOM_ID_SM8650P			577
 #define QCOM_ID_QDU1010			587
 #define QCOM_ID_QRU1032			588
 #define QCOM_ID_QRU1052			589
-- 
2.25.1

[RFC PATCH 3/6] soc: qcom: socinfo: Add SM8650P SoC ID table entry

[Jingyi Wang]

Add SoC Info support for the SM8650P platform.

Signed-off-by: Jingyi Wang <quic_jingyw@quicinc.com>
---
 drivers/soc/qcom/socinfo.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/soc/qcom/socinfo.c b/drivers/soc/qcom/socinfo.c
index 5a44ad870fb6..ee6ea575db0f 100644
--- a/drivers/soc/qcom/socinfo.c
+++ b/drivers/soc/qcom/socinfo.c
@@ -429,6 +429,7 @@ static const struct soc_id soc_id[] = {
 	{ qcom_board_id(QDU1000) },
 	{ qcom_board_id(SM8650) },
 	{ qcom_board_id(SM4450) },
+	{ qcom_board_id(SM8650P) },
 	{ qcom_board_id(QDU1010) },
 	{ qcom_board_id(QRU1032) },
 	{ qcom_board_id(QRU1052) },
-- 
2.25.1

[RFC PATCH 4/6] arm64: dts: qcom: sm8650p: introduce sm8650p dtsi

[Jingyi Wang]

Introduce sm8650p dtsi, sm8650p has same base functions
as sm8650 with different memory regions.

There are 3 types of reserved memory regions here:
1. Firmware related regions.
    This will be described as: reserved-region@address. Current
reserved-region may have reserved area which was not yet used, release
note of the firmware can have such kind of information.
2. Firmware related which shared with kernel access.
    Each region will have a specific node with specific label name for
later phandle reference from other driver dt node. May overlapping with
above type regions.
3. PIL regions.
    PIL regions are allocated by kernel and assigned to subsystem
firmware later.
Here is a map for this platform:
0x100000000 +------------------+
            |                  |
            | Firmware Related |
            |                  |
 0xd8000000 +------------------+
            |                  |
            | Kernel Available |
            |                  |
 0xA7000000 +------------------+
            |                  |
            |    PIL Region    |
            |                  |
 0x8BC00000 +------------------+
            |                  |
            | Firmware Related |
            |                  |
 0x80000000 +------------------+
Note that:
1. 0xA7000000 to 0xA8000000 was used by bootloader as well, not suggest
for other usage.
2. Kernel start address was start at 0xA8000000.

Signed-off-by: Jingyi Wang <quic_jingyw@quicinc.com>
---
 arch/arm64/boot/dts/qcom/sm8650p.dtsi | 180 ++++++++++++++++++++++++++
 1 file changed, 180 insertions(+)
 create mode 100644 arch/arm64/boot/dts/qcom/sm8650p.dtsi

diff --git a/arch/arm64/boot/dts/qcom/sm8650p.dtsi b/arch/arm64/boot/dts/qcom/sm8650p.dtsi
new file mode 100644
index 000000000000..26dfe315b49d
--- /dev/null
+++ b/arch/arm64/boot/dts/qcom/sm8650p.dtsi
@@ -0,0 +1,180 @@
+// SPDX-License-Identifier: BSD-3-Clause
+/*
+ * Copyright (c) 2024, Qualcomm Innovation Center, Inc. All rights reserved.
+ */
+
+#include "sm8650.dtsi"
+
+/delete-node/ &reserved_memory;
+
+/ {
+	reserved_memory: reserved-memory {
+		#address-cells = <2>;
+		#size-cells = <2>;
+		ranges;
+
+		/*
+		 * There are 3 types of reserved memory regions here:
+		 * 1. Firmware related regions.
+		 *     This will be described as: reserved-region@address. Current
+		 * reserved-region may have reserved area which was not yet used,
+		 * release note of the firmware can have such kind of information.
+		 * 2. Firmware related which shared with kernel access.
+		 *     Each region will have a specific node with specific label
+		 * name for later phandle reference from other driver dt node. May
+		 * overlapping with above type regions.
+		 * 3. PIL regions.
+		 *     PIL regions are allocated by kernel and assigned to subsystem
+		 * firmware later.
+		 * Here is a map for this platform:
+		 * 0x100000000 +------------------+
+		 *             |                  |
+		 *             | Firmware Related |
+		 *             |                  |
+		 *  0xd8000000 +------------------+
+		 *             |                  |
+		 *             | Kernel Available |
+		 *             |                  |
+		 *  0xA7000000 +------------------+
+		 *             |                  |
+		 *             |    PIL Region    |
+		 *             |                  |
+		 *  0x8BC00000 +------------------+
+		 *             |                  |
+		 *             | Firmware Related |
+		 *             |                  |
+		 *  0x80000000 +------------------+
+		 * Note that:
+		 * 1. 0xA7000000 to 0xA8000000 was used by bootloader as well, not
+		 * suggest for other usage.
+		 * 2. Kernel start address was start at 0xA8000000.
+		 */
+
+		/* Firmware related regions */
+		reserved-region@80000000 {
+			reg = <0x0 0x80000000 0x0 0xbc00000>;
+			no-map;
+		};
+
+		aop_image_mem: aop-image-region@81c00000 {
+			reg = <0x0 0x81c00000 0x0 0x60000>;
+			no-map;
+		};
+
+		aop_cmd_db_mem: aop-cmd-db-region@81c60000 {
+			compatible = "qcom,cmd-db";
+			reg = <0x0 0x81c60000 0x0 0x20000>;
+			no-map;
+		};
+
+		aop_config_mem: aop-config-region@81c80000 {
+			no-map;
+			reg = <0x0 0x81c80000 0x0 0x20000>;
+		};
+
+		smem_mem: smem-region@81d00000 {
+			compatible = "qcom,smem";
+			reg = <0x0 0x81d00000 0x0 0x200000>;
+			hwlocks = <&tcsr_mutex 3>;
+			no-map;
+		};
+
+		adsp_mhi_mem: adsp-mhi-region@81f00000 {
+			reg = <0x0 0x81f00000 0x0 0x20000>;
+			no-map;
+		};
+
+		global_sync_mem: global-sync@82600000 {
+			reg = <0 0x82600000 0 0x100000>;
+			no-map;
+		};
+
+		mpss_dsm_mem: mpss-dsm@86b00000 {
+			reg = <0 0x86b00000 0 0x4900000>;
+			no-map;
+		};
+
+		mpss_dsm_mem_2: mpss-dsm-2@8b400000 {
+			reg = <0 0x8b400000 0 0x800000>;
+			no-map;
+		};
+
+		/* PIL region */
+		mpss_mem: mpss-region@8bc00000 {
+			reg = <0x0 0x8bc00000 0x0 0xf400000>;
+			no-map;
+		};
+
+		q6_mpss_dtb_mem: q6-mpss-dtb-region@9b000000 {
+			reg = <0x0 0x9b000000 0x0 0x80000>;
+			no-map;
+		};
+
+		ipa_fw_mem: ipa-fw-region@9b080000 {
+			reg = <0x0 0x9b080000 0x0 0x10000>;
+			no-map;
+		};
+
+		ipa_gsi_mem: ipa-gsi-region@9b090000 {
+			reg = <0x0 0x9b090000 0x0 0xa000>;
+			no-map;
+		};
+
+		gpu_micro_code_mem: gpu-micro-code-region@9b09a000 {
+			reg = <0x0 0x9b09a000 0x0 0x2000>;
+			no-map;
+		};
+
+		spss_region_mem: spss-region@9b0a0000 {
+			reg = <0x0 0x9b0a0000 0x0 0x1e0000>;
+			no-map;
+		};
+
+		spu_secure_shared_memory_mem: spu-secure-shared-memory-region@9b280000 {
+			reg = <0x0 0x9b280000 0x0 0x80000>;
+			no-map;
+		};
+
+		camera_mem: camera-region@9b300000 {
+			reg = <0x0 0x9b300000 0x0 0x800000>;
+			no-map;
+		};
+
+		video_mem: video-region@9bb00000 {
+			reg = <0x0 0x9bb00000 0x0 0x800000>;
+			no-map;
+		};
+
+		cvp_mem: cvp-region@9c300000 {
+			reg = <0x0 0x9c300000 0x0 0x700000>;
+			no-map;
+		};
+
+		cdsp_mem: cdsp-region@9ca00000 {
+			reg = <0x0 0x9ca00000 0x0 0x1400000>;
+			no-map;
+		};
+
+		q6_cdsp_dtb_mem: q6-cdsp-dtb-region@9de00000 {
+			reg = <0x0 0x9de00000 0x0 0x80000>;
+			no-map;
+		};
+
+		q6_adsp_dtb_mem: q6-adsp-dtb-region@9de80000 {
+			reg = <0x0 0x9de80000 0x0 0x80000>;
+			no-map;
+		};
+
+		adspslpi_mem: adspslpi-region@9df00000 {
+			reg = <0x0 0x9df00000 0x0 0x4080000>;
+			no-map;
+		};
+
+		/* Firmware related regions */
+		reserved-region@d8000000 {
+			reg = <0x0 0xd8000000 0x0 0x28000000>;
+			no-map;
+		};
+
+	};
+};
-- 
2.25.1

[RFC PATCH 5/6] arm64: dts: qcom: add base AIM500 dtsi

[Jingyi Wang]

Introduce aim500 board dtsi.

AIM500 Series is a highly optimized family of modules designed to
support AIoT and Generative AI applications based on sm8650p with
PMIC and bluetooth functions etc.

Co-developed-by: Tingwei Zhang <quic_tingweiz@quicinc.com>
Signed-off-by: Tingwei Zhang <quic_tingweiz@quicinc.com>
Signed-off-by: Jingyi Wang <quic_jingyw@quicinc.com>
---
 arch/arm64/boot/dts/qcom/sm8650p-aim500.dtsi | 409 +++++++++++++++++++
 1 file changed, 409 insertions(+)
 create mode 100644 arch/arm64/boot/dts/qcom/sm8650p-aim500.dtsi

diff --git a/arch/arm64/boot/dts/qcom/sm8650p-aim500.dtsi b/arch/arm64/boot/dts/qcom/sm8650p-aim500.dtsi
new file mode 100644
index 000000000000..cb857da8653b
--- /dev/null
+++ b/arch/arm64/boot/dts/qcom/sm8650p-aim500.dtsi
@@ -0,0 +1,409 @@
+// SPDX-License-Identifier: BSD-3-Clause
+/*
+ * Copyright (c) 2024, Qualcomm Innovation Center, Inc. All rights reserved.
+ */
+
+#include <dt-bindings/regulator/qcom,rpmh-regulator.h>
+#include "sm8650p.dtsi"
+#include "pm8550.dtsi"
+#include "pm8550b.dtsi"
+#define PMK8550VE_SID 8
+#include "pm8550ve.dtsi"
+#include "pm8550vs.dtsi"
+#include "pmk8550.dtsi"
+
+/ {
+	aliases {
+		serial1 = &uart14;
+	};
+
+	vph_pwr: vph-pwr-regulator { };
+};
+
+&apps_rsc {
+	regulators-0 {
+		compatible = "qcom,pm8550-rpmh-regulators";
+
+		vdd-bob1-supply = <&vph_pwr>;
+		vdd-bob2-supply = <&vph_pwr>;
+		vdd-l2-l13-l14-supply = <&vreg_bob1>;
+		vdd-l3-supply = <&vreg_s1c_1p2>;
+		vdd-l5-l16-supply = <&vreg_bob1>;
+		vdd-l6-l7-supply = <&vreg_bob1>;
+		vdd-l8-l9-supply = <&vreg_bob1>;
+		vdd-l11-supply = <&vreg_s1c_1p2>;
+		vdd-l12-supply = <&vreg_s6c_1p8>;
+		vdd-l15-supply = <&vreg_s6c_1p8>;
+		vdd-l17-supply = <&vreg_bob2>;
+
+		qcom,pmic-id = "b";
+
+		vreg_bob1: bob1 {
+			regulator-name = "vreg_bob1";
+			regulator-min-microvolt = <3008000>;
+			regulator-max-microvolt = <3960000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+		};
+
+		vreg_bob2: bob2 {
+			regulator-name = "vreg_bob2";
+			regulator-min-microvolt = <2704000>;
+			regulator-max-microvolt = <3008000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+		};
+
+		vreg_l2b_3p0: ldo2 {
+			regulator-name = "vreg_l2b_3p0";
+			regulator-min-microvolt = <3008000>;
+			regulator-max-microvolt = <3008000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+			regulator-allow-set-load;
+			regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+						   RPMH_REGULATOR_MODE_HPM>;
+		};
+
+		vreg_l5b_3p1: ldo5 {
+			regulator-name = "vreg_l5b_3p1";
+			regulator-min-microvolt = <3104000>;
+			regulator-max-microvolt = <3104000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+			regulator-allow-set-load;
+			regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+						   RPMH_REGULATOR_MODE_HPM>;
+		};
+
+		vreg_l6b_1p8: ldo6 {
+			regulator-name = "vreg_l6b_1p8";
+			regulator-min-microvolt = <1800000>;
+			regulator-max-microvolt = <3008000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+			regulator-allow-set-load;
+			regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+						   RPMH_REGULATOR_MODE_HPM>;
+		};
+
+		vreg_l7b_1p8: ldo7 {
+			regulator-name = "vreg_l7b_1p8";
+			regulator-min-microvolt = <1800000>;
+			regulator-max-microvolt = <3008000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+		};
+
+		vreg_l8b_1p8: ldo8 {
+			regulator-name = "vreg_l8b_1p8";
+			regulator-min-microvolt = <1800000>;
+			regulator-max-microvolt = <3008000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+			regulator-allow-set-load;
+			regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+						   RPMH_REGULATOR_MODE_HPM>;
+		};
+
+		vreg_l11b_1p2: ldo11 {
+			regulator-name = "vreg_l11b_1p2";
+			regulator-min-microvolt = <1200000>;
+			regulator-max-microvolt = <1200000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+			regulator-allow-set-load;
+			regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+						   RPMH_REGULATOR_MODE_HPM>;
+		};
+
+		vreg_l12b_1p8: ldo12 {
+			regulator-name = "vreg_l12b_1p8";
+			regulator-min-microvolt = <1800000>;
+			regulator-max-microvolt = <1800000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+			regulator-allow-set-load;
+			regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+						   RPMH_REGULATOR_MODE_HPM>;
+		};
+
+		vreg_l13b_3p0: ldo13 {
+			regulator-name = "vreg_l13b_3p0";
+			regulator-min-microvolt = <3000000>;
+			regulator-max-microvolt = <3000000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+			regulator-allow-set-load;
+			regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+						   RPMH_REGULATOR_MODE_HPM>;
+		};
+
+		vreg_l14b_3p2: ldo14 {
+			regulator-name = "vreg_l14b_3p2";
+			regulator-min-microvolt = <3200000>;
+			regulator-max-microvolt = <3200000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+			regulator-allow-set-load;
+			regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+						   RPMH_REGULATOR_MODE_HPM>;
+		};
+
+		vreg_l15b_1p8: ldo15 {
+			regulator-name = "vreg_l15b_1p8";
+			regulator-min-microvolt = <1800000>;
+			regulator-max-microvolt = <1800000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+			regulator-allow-set-load;
+			regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+						   RPMH_REGULATOR_MODE_HPM>;
+		};
+
+		vreg_l16b_2p8: ldo16 {
+			regulator-name = "vreg_l16b_2p8";
+			regulator-min-microvolt = <2800000>;
+			regulator-max-microvolt = <2800000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+			regulator-allow-set-load;
+			regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+						   RPMH_REGULATOR_MODE_HPM>;
+		};
+
+		vreg_l17b_2p5: ldo17 {
+			regulator-name = "vreg_l17b_2p5";
+			regulator-min-microvolt = <2504000>;
+			regulator-max-microvolt = <2504000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+			regulator-allow-set-load;
+			regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+						   RPMH_REGULATOR_MODE_HPM>;
+		};
+	};
+
+	regulators-1 {
+		compatible = "qcom,pm8550vs-rpmh-regulators";
+
+		vdd-l1-supply = <&vreg_s1c_1p2>;
+		vdd-l2-supply = <&vreg_s1c_1p2>;
+		vdd-l3-supply = <&vreg_s1c_1p2>;
+		vdd-s1-supply = <&vph_pwr>;
+		vdd-s2-supply = <&vph_pwr>;
+		vdd-s3-supply = <&vph_pwr>;
+		vdd-s4-supply = <&vph_pwr>;
+		vdd-s5-supply = <&vph_pwr>;
+		vdd-s6-supply = <&vph_pwr>;
+
+		qcom,pmic-id = "c";
+
+		vreg_s1c_1p2: smps1 {
+			regulator-name = "vreg_s1c_1p2";
+			regulator-min-microvolt = <1224000>;
+			regulator-max-microvolt = <1348000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+		};
+
+		vreg_s2c_0p8: smps2 {
+			regulator-name = "vreg_s2c_0p8";
+			regulator-min-microvolt = <500000>;
+			regulator-max-microvolt = <1036000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+		};
+
+		vreg_s3c_0p9: smps3 {
+			regulator-name = "vreg_s3c_0p9";
+			regulator-min-microvolt = <904000>;
+			regulator-max-microvolt = <1068000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+		};
+
+		vreg_s4c_1p2: smps4 {
+			regulator-name = "vreg_s4c_1p2";
+			regulator-min-microvolt = <1200000>;
+			regulator-max-microvolt = <1280000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+		};
+
+		vreg_s5c_0p7: smps5 {
+			regulator-name = "vreg_s5c_0p7";
+			regulator-min-microvolt = <300000>;
+			regulator-max-microvolt = <900000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+		};
+
+		vreg_s6c_1p8: smps6 {
+			regulator-name = "vreg_s6c_1p8";
+			regulator-min-microvolt = <1856000>;
+			regulator-max-microvolt = <2000000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+		};
+
+		vreg_l1c_1p2: ldo1 {
+			regulator-name = "vreg_l1c_1p2";
+			regulator-min-microvolt = <1100000>;
+			regulator-max-microvolt = <1200000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+			regulator-allow-set-load;
+			regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+						   RPMH_REGULATOR_MODE_HPM>;
+		};
+
+		vreg_l3c_1p2: ldo3 {
+			regulator-name = "vreg_l3c_1p2";
+			regulator-min-microvolt = <1200000>;
+			regulator-max-microvolt = <1200000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+			regulator-allow-set-load;
+			regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+						   RPMH_REGULATOR_MODE_HPM>;
+		};
+	};
+
+	regulators-2 {
+		compatible = "qcom,pm8550vs-rpmh-regulators";
+
+		vdd-l1-supply = <&vreg_s3c_0p9>;
+
+		qcom,pmic-id = "d";
+
+		vreg_l1d_0p88: ldo1 {
+			regulator-name = "vreg_l1d_0p88";
+			regulator-min-microvolt = <880000>;
+			regulator-max-microvolt = <920000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+			regulator-allow-set-load;
+			regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+						   RPMH_REGULATOR_MODE_HPM>;
+		};
+	};
+
+	regulators-3 {
+		compatible = "qcom,pm8550vs-rpmh-regulators";
+
+		vdd-l3-supply = <&vreg_s3c_0p9>;
+
+		qcom,pmic-id = "e";
+
+		vreg_l3e_0p9: ldo3 {
+			regulator-name = "vreg_l3e_0p9";
+			regulator-min-microvolt = <880000>;
+			regulator-max-microvolt = <920000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+			regulator-allow-set-load;
+			regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+						   RPMH_REGULATOR_MODE_HPM>;
+		};
+	};
+
+	regulators-4 {
+		compatible = "qcom,pm8550vs-rpmh-regulators";
+
+		vdd-l1-supply = <&vreg_s3c_0p9>;
+		vdd-l3-supply = <&vreg_s3c_0p9>;
+
+		qcom,pmic-id = "g";
+
+		vreg_l1g_0p91: ldo1 {
+			regulator-name = "vreg_l1g_0p91";
+			regulator-min-microvolt = <912000>;
+			regulator-max-microvolt = <936000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+			regulator-allow-set-load;
+			regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+						   RPMH_REGULATOR_MODE_HPM>;
+		};
+
+		vreg_l3g_0p91: ldo3 {
+			regulator-name = "vreg_l3g_0p91";
+			regulator-min-microvolt = <880000>;
+			regulator-max-microvolt = <912000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+			regulator-allow-set-load;
+			regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+						   RPMH_REGULATOR_MODE_HPM>;
+		};
+	};
+
+	regulators-5 {
+		compatible = "qcom,pm8550ve-rpmh-regulators";
+
+		vdd-l1-supply = <&vreg_s3c_0p9>;
+		vdd-l2-supply = <&vreg_s3c_0p9>;
+		vdd-l3-supply = <&vreg_s1c_1p2>;
+		vdd-s4-supply = <&vph_pwr>;
+
+		qcom,pmic-id = "i";
+
+		vreg_s4i_0p85: smps4 {
+			regulator-name = "vreg_s4i_0p85";
+			regulator-min-microvolt = <300000>;
+			regulator-max-microvolt = <1004000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+		};
+
+		vreg_l1i_0p88: ldo1 {
+			regulator-name = "vreg_l1i_0p88";
+			regulator-min-microvolt = <880000>;
+			regulator-max-microvolt = <912000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+			regulator-allow-set-load;
+			regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+						   RPMH_REGULATOR_MODE_HPM>;
+		};
+
+		vreg_l2i_0p88: ldo2 {
+			regulator-name = "vreg_l2i_0p88";
+			regulator-min-microvolt = <880000>;
+			regulator-max-microvolt = <912000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+			regulator-allow-set-load;
+			regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+						   RPMH_REGULATOR_MODE_HPM>;
+		};
+
+		vreg_l3i_1p2: ldo3 {
+			regulator-name = "vreg_l3i_0p91";
+			regulator-min-microvolt = <1200000>;
+			regulator-max-microvolt = <1200000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+			regulator-allow-set-load;
+			regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+						   RPMH_REGULATOR_MODE_HPM>;
+		};
+	};
+};
+
+&qupv3_id_1 {
+	status = "okay";
+};
+
+&tlmm {
+	bt_default: bt-default-state {
+		bt-en-pins {
+			pins = "gpio17";
+			function = "gpio";
+			drive-strength = <16>;
+			bias-disable;
+		};
+
+		sw-ctrl-pins {
+			pins = "gpio18";
+			function = "gpio";
+			bias-pull-down;
+		};
+	};
+};
+
+&uart14 {
+	status = "okay";
+
+	bluetooth {
+		compatible = "qcom,wcn7850-bt";
+
+		clocks = <&rpmhcc RPMH_RF_CLK1>;
+
+		vddio-supply = <&vreg_l3c_1p2>;
+		vddaon-supply = <&vreg_l15b_1p8>;
+		vdddig-supply = <&vreg_s3c_0p9>;
+		vddrfa0p8-supply = <&vreg_s3c_0p9>;
+		vddrfa1p2-supply = <&vreg_s1c_1p2>;
+		vddrfa1p9-supply = <&vreg_s6c_1p8>;
+
+		max-speed = <3200000>;
+
+		enable-gpios = <&tlmm 17 GPIO_ACTIVE_HIGH>;
+		swctrl-gpios = <&tlmm 18 GPIO_ACTIVE_HIGH>;
+
+		pinctrl-0 = <&bt_default>;
+		pinctrl-names = "default";
+	};
+};
-- 
2.25.1

[RFC PATCH 6/6] arm64: dts: qcom: add AIM500 AIoT

[Jingyi Wang]

Add AIM500 AIoT DTS along with usb, regulators, serial and PCIe
found in this board. AIM500 AIoT is mounted onto Qualcomm AIoT
carrier board to support verification, evaluation and development.

Co-developed-by: Tingwei Zhang <quic_tingweiz@quicinc.com>
Signed-off-by: Tingwei Zhang <quic_tingweiz@quicinc.com>
Signed-off-by: Jingyi Wang <quic_jingyw@quicinc.com>
---
 arch/arm64/boot/dts/qcom/Makefile             |   1 +
 .../boot/dts/qcom/sm8650p-aim500-aiot.dts     | 314 ++++++++++++++++++
 2 files changed, 315 insertions(+)
 create mode 100644 arch/arm64/boot/dts/qcom/sm8650p-aim500-aiot.dts

diff --git a/arch/arm64/boot/dts/qcom/Makefile b/arch/arm64/boot/dts/qcom/Makefile
index f7c5662213e4..ce3744d7586f 100644
--- a/arch/arm64/boot/dts/qcom/Makefile
+++ b/arch/arm64/boot/dts/qcom/Makefile
@@ -239,5 +239,6 @@ dtb-$(CONFIG_ARCH_QCOM)	+= sm8550-mtp.dtb
 dtb-$(CONFIG_ARCH_QCOM)	+= sm8550-qrd.dtb
 dtb-$(CONFIG_ARCH_QCOM)	+= sm8650-mtp.dtb
 dtb-$(CONFIG_ARCH_QCOM)	+= sm8650-qrd.dtb
+dtb-$(CONFIG_ARCH_QCOM)	+= sm8650p-aim500-aiot.dtb
 dtb-$(CONFIG_ARCH_QCOM)	+= x1e80100-crd.dtb
 dtb-$(CONFIG_ARCH_QCOM)	+= x1e80100-qcp.dtb
diff --git a/arch/arm64/boot/dts/qcom/sm8650p-aim500-aiot.dts b/arch/arm64/boot/dts/qcom/sm8650p-aim500-aiot.dts
new file mode 100644
index 000000000000..a76b62abb9e0
--- /dev/null
+++ b/arch/arm64/boot/dts/qcom/sm8650p-aim500-aiot.dts
@@ -0,0 +1,314 @@
+// SPDX-License-Identifier: BSD-3-Clause
+/*
+ * Copyright (c) 2024, Qualcomm Innovation Center, Inc. All rights reserved.
+ */
+
+/dts-v1/;
+
+#include <dt-bindings/leds/common.h>
+#include "sm8650p-aim500.dtsi"
+#include "pm8010.dtsi"
+#include "pmr735d_a.dtsi"
+
+/ {
+	model = "Qualcomm Technologies, Inc. AIM500 AIOT";
+	compatible = "qcom,sm8650p-aim500-aiot", "qcom,sm8650p-aim500", "qcom,sm8650p",
+		     "qcom,sm8650";
+
+	aliases {
+		serial0 = &uart15;
+	};
+
+	chosen {
+		stdout-path = "serial0:115200n8";
+	};
+
+	gpio-keys {
+		compatible = "gpio-keys";
+
+		pinctrl-0 = <&volume_up_n>;
+		pinctrl-names = "default";
+
+		key-volume-up {
+			label = "Volume Up";
+			linux,code = <KEY_VOLUMEUP>;
+			gpios = <&pm8550_gpios 6 GPIO_ACTIVE_LOW>;
+			debounce-interval = <15>;
+			linux,can-disable;
+			wakeup-source;
+		};
+	};
+
+	pmic-glink {
+		compatible = "qcom,sm8650-pmic-glink",
+			     "qcom,sm8550-pmic-glink",
+			     "qcom,pmic-glink";
+		#address-cells = <1>;
+		#size-cells = <0>;
+		orientation-gpios = <&tlmm 29 GPIO_ACTIVE_HIGH>;
+
+		connector@0 {
+			compatible = "usb-c-connector";
+			reg = <0>;
+
+			power-role = "dual";
+			data-role = "dual";
+
+			ports {
+				#address-cells = <1>;
+				#size-cells = <0>;
+
+				port@0 {
+					reg = <0>;
+
+					pmic_glink_hs_in: endpoint {
+						remote-endpoint = <&usb_1_dwc3_hs>;
+					};
+				};
+
+				port@1 {
+					reg = <1>;
+
+					pmic_glink_ss_in: endpoint {
+						remote-endpoint = <&usb_1_dwc3_ss>;
+					};
+				};
+			};
+		};
+	};
+};
+
+&dispcc {
+	status = "okay";
+};
+
+&gpi_dma1 {
+	status = "okay";
+};
+
+&pcie_1_phy_aux_clk {
+	clock-frequency = <1000>;
+};
+
+&pcie0 {
+	perst-gpios = <&tlmm 94 GPIO_ACTIVE_LOW>;
+	wake-gpios = <&tlmm 96 GPIO_ACTIVE_HIGH>;
+
+	pinctrl-0 = <&pcie0_default_state>;
+	pinctrl-names = "default";
+
+	status = "okay";
+};
+
+&pcie0_phy {
+	vdda-phy-supply = <&vreg_l1i_0p88>;
+	vdda-pll-supply = <&vreg_l3i_1p2>;
+
+	status = "okay";
+};
+
+&pm8550_flash {
+	status = "okay";
+
+	led-0 {
+		function = LED_FUNCTION_FLASH;
+		color = <LED_COLOR_ID_YELLOW>;
+		flash-max-microamp = <2000000>;
+		flash-max-timeout-us = <1280000>;
+		function-enumerator = <0>;
+		led-sources = <1>, <4>;
+		led-max-microamp = <500000>;
+	};
+
+	led-1 {
+		function = LED_FUNCTION_FLASH;
+		color = <LED_COLOR_ID_WHITE>;
+		flash-max-microamp = <2000000>;
+		flash-max-timeout-us = <1280000>;
+		function-enumerator = <1>;
+		led-sources = <2>, <3>;
+		led-max-microamp = <500000>;
+	};
+};
+
+&pm8550_gpios {
+	volume_up_n: volume-up-n-state {
+		pins = "gpio6";
+		function = "normal";
+		power-source = <1>;
+		bias-pull-up;
+		input-enable;
+	};
+};
+
+&pm8550_pwm {
+	status = "okay";
+
+	multi-led {
+		color = <LED_COLOR_ID_RGB>;
+		function = LED_FUNCTION_STATUS;
+
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		led@1 {
+			reg = <1>;
+			color = <LED_COLOR_ID_RED>;
+		};
+
+		led@2 {
+			reg = <2>;
+			color = <LED_COLOR_ID_GREEN>;
+		};
+
+		led@3 {
+			reg = <3>;
+			color = <LED_COLOR_ID_BLUE>;
+		};
+	};
+};
+
+&pm8550b_eusb2_repeater {
+	vdd18-supply = <&vreg_l15b_1p8>;
+	vdd3-supply = <&vreg_l5b_3p1>;
+};
+
+&pmk8550_rtc {
+	status = "okay";
+};
+
+&pon_pwrkey {
+	status = "okay";
+};
+
+&pon_resin {
+	linux,code = <KEY_VOLUMEDOWN>;
+
+	status = "okay";
+};
+
+&qupv3_id_0 {
+	status = "okay";
+};
+
+&remoteproc_adsp {
+	firmware-name = "qcom/sm8650/adsp.mbn",
+			"qcom/sm8650/adsp_dtb.mbn";
+
+	status = "okay";
+};
+
+&remoteproc_cdsp {
+	firmware-name = "qcom/sm8650/cdsp.mbn",
+			"qcom/sm8650/cdsp_dtb.mbn";
+
+	status = "okay";
+};
+
+&sleep_clk {
+	clock-frequency = <32000>;
+};
+
+&tlmm {
+	gpio-reserved-ranges = <32 8>;
+
+	sde_dsi_active: sde-dsi-active-state {
+		pins = "gpio133";
+		function = "gpio";
+		drive-strength = <8>;
+		bias-disable;
+	};
+
+	sde_dsi_suspend: sde-dsi-suspend-state {
+		pins = "gpio133";
+		function = "gpio";
+		drive-strength = <2>;
+		bias-pull-down;
+	};
+
+	sde_te_active: sde-te-active-state {
+		pins = "gpio86";
+		function = "mdp_vsync";
+		drive-strength = <2>;
+		bias-pull-down;
+	};
+
+	sde_te_suspend: sde-te-suspend-state {
+		pins = "gpio86";
+		function = "mdp_vsync";
+		drive-strength = <2>;
+		bias-pull-down;
+	};
+
+	ts_irq: ts-irq-state {
+		pins = "gpio161";
+		function = "gpio";
+		drive-strength = <8>;
+		bias-pull-up;
+		output-disable;
+	};
+
+	ts_reset: ts-reset-state {
+		pins = "gpio162";
+		function = "gpio";
+		drive-strength = <8>;
+		bias-pull-up;
+	};
+};
+
+&uart15 {
+	status = "okay";
+};
+
+/*
+ * DPAUX -> WCD9395 -> USB_SBU -> USB-C
+ * eUSB2 DP/DM -> PM85550HS -> eUSB2 DP/DM -> WCD9395 -> USB-C
+ * USB SS -> NB7VPQ904MMUTWG -> USB-C
+ */
+
+&usb_1 {
+	status = "okay";
+};
+
+&usb_1_dwc3 {
+	dr_mode = "otg";
+	usb-role-switch;
+};
+
+&usb_1_dwc3_hs {
+	remote-endpoint = <&pmic_glink_hs_in>;
+};
+
+&usb_1_dwc3_ss {
+	remote-endpoint = <&pmic_glink_ss_in>;
+};
+
+&usb_1_hsphy {
+	vdd-supply = <&vreg_l1i_0p88>;
+	vdda12-supply = <&vreg_l3i_1p2>;
+
+	phys = <&pm8550b_eusb2_repeater>;
+
+	status = "okay";
+};
+
+&usb_dp_qmpphy {
+	vdda-phy-supply = <&vreg_l3i_1p2>;
+	vdda-pll-supply = <&vreg_l3g_0p91>;
+
+	status = "okay";
+};
+
+&vph_pwr {
+	compatible = "regulator-fixed";
+	regulator-name = "vph_pwr";
+	regulator-min-microvolt = <3700000>;
+	regulator-max-microvolt = <3700000>;
+
+	regulator-always-on;
+	regulator-boot-on;
+};
+
+&xo_board {
+	clock-frequency = <76800000>;
+};
-- 
2.25.1

Re: [RFC PATCH 1/6] dt-bindings: arm: qcom: Document sm8650p soc and AIM500 AIoT board

[Krzysztof Kozlowski]

On 05/02/2024 12:57, Jingyi Wang wrote:
> Document Qualcomm SM8650P SoC and AIM500 AIoT board.

Please describe shortly what is SM8650P and what are the differences
with SM8650.

> 
> Signed-off-by: Jingyi Wang <quic_jingyw@quicinc.com>
> ---
>  Documentation/devicetree/bindings/arm/qcom.yaml | 9 +++++++++
>  1 file changed, 9 insertions(+)
> 
> diff --git a/Documentation/devicetree/bindings/arm/qcom.yaml b/Documentation/devicetree/bindings/arm/qcom.yaml
> index 1999a5f2f254..e87ceb42853b 100644
> --- a/Documentation/devicetree/bindings/arm/qcom.yaml
> +++ b/Documentation/devicetree/bindings/arm/qcom.yaml
> @@ -88,11 +88,13 @@ description: |
>          sm8450
>          sm8550
>          sm8650
> +        sm8650p
>          x1e80100
>  
>    The 'board' element must be one of the following strings:
>  
>          adp
> +        aim500-aiot

Drop this line.

>          cdp
>          dragonboard
>          idp
> @@ -1051,6 +1053,13 @@ properties:
>                - qcom,sm8650-qrd
>            - const: qcom,sm8650
>  
> +      - items:
> +          - enum:
> +              - qcom,sm8650p-aim500-aiot
> +          - const: qcom,sm8650p-aim500
> +          - const: qcom,sm8650p
> +          - const: qcom,sm8650



Best regards,
Krzysztof

Re: [RFC PATCH 2/6] dt-bindings: arm: qcom,ids: Add SoC ID for SM8650P

[Krzysztof Kozlowski]

On 05/02/2024 12:57, Jingyi Wang wrote:
> Add the ID for the Qualcomm SM8650P SoC.
> 
> Signed-off-by: Jingyi Wang <quic_jingyw@quicinc.com>
> ---

Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>

Best regards,
Krzysztof

Re: [RFC PATCH 3/6] soc: qcom: socinfo: Add SM8650P SoC ID table entry

[Krzysztof Kozlowski]

On 05/02/2024 12:57, Jingyi Wang wrote:
> Add SoC Info support for the SM8650P platform.
> 
> Signed-off-by: Jingyi Wang <quic_jingyw@quicinc.com>
> ---
>  drivers/soc/qcom/socinfo.c | 1 +

Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>

Best regards,
Krzysztof

Re: [RFC PATCH 5/6] arm64: dts: qcom: add base AIM500 dtsi

[Krzysztof Kozlowski]

On 05/02/2024 12:57, Jingyi Wang wrote:
> Introduce aim500 board dtsi.
> 
> AIM500 Series is a highly optimized family of modules designed to
> support AIoT and Generative AI applications based on sm8650p with
> PMIC and bluetooth functions etc.
> 
> Co-developed-by: Tingwei Zhang <quic_tingweiz@quicinc.com>
> Signed-off-by: Tingwei Zhang <quic_tingweiz@quicinc.com>
> Signed-off-by: Jingyi Wang <quic_jingyw@quicinc.com>
> ---
>  arch/arm64/boot/dts/qcom/sm8650p-aim500.dtsi | 409 +++++++++++++++++++
>  1 file changed, 409 insertions(+)
>  create mode 100644 arch/arm64/boot/dts/qcom/sm8650p-aim500.dtsi
> 
> diff --git a/arch/arm64/boot/dts/qcom/sm8650p-aim500.dtsi b/arch/arm64/boot/dts/qcom/sm8650p-aim500.dtsi
> new file mode 100644
> index 000000000000..cb857da8653b
> --- /dev/null
> +++ b/arch/arm64/boot/dts/qcom/sm8650p-aim500.dtsi
> @@ -0,0 +1,409 @@
> +// SPDX-License-Identifier: BSD-3-Clause
> +/*
> + * Copyright (c) 2024, Qualcomm Innovation Center, Inc. All rights reserved.
> + */
> +
> +#include <dt-bindings/regulator/qcom,rpmh-regulator.h>
> +#include "sm8650p.dtsi"
> +#include "pm8550.dtsi"
> +#include "pm8550b.dtsi"
> +#define PMK8550VE_SID 8
> +#include "pm8550ve.dtsi"
> +#include "pm8550vs.dtsi"
> +#include "pmk8550.dtsi"
> +
> +/ {
> +	aliases {
> +		serial1 = &uart14;
> +	};
> +
> +	vph_pwr: vph-pwr-regulator { };

What is this? Why is it needed?


Best regards,
Krzysztof

Re: [RFC PATCH 5/6] arm64: dts: qcom: add base AIM500 dtsi

[Dmitry Baryshkov]

On Mon, 5 Feb 2024 at 14:00, Jingyi Wang <quic_jingyw@quicinc.com> wrote:
>
> Introduce aim500 board dtsi.

So, is it a board or a module?

>
> AIM500 Series is a highly optimized family of modules designed to
> support AIoT and Generative AI applications based on sm8650p with
> PMIC and bluetooth functions etc.
>
> Co-developed-by: Tingwei Zhang <quic_tingweiz@quicinc.com>
> Signed-off-by: Tingwei Zhang <quic_tingweiz@quicinc.com>
> Signed-off-by: Jingyi Wang <quic_jingyw@quicinc.com>
> ---
>  arch/arm64/boot/dts/qcom/sm8650p-aim500.dtsi | 409 +++++++++++++++++++
>  1 file changed, 409 insertions(+)
>  create mode 100644 arch/arm64/boot/dts/qcom/sm8650p-aim500.dtsi
>
> diff --git a/arch/arm64/boot/dts/qcom/sm8650p-aim500.dtsi b/arch/arm64/boot/dts/qcom/sm8650p-aim500.dtsi
> new file mode 100644
> index 000000000000..cb857da8653b
> --- /dev/null
> +++ b/arch/arm64/boot/dts/qcom/sm8650p-aim500.dtsi
> @@ -0,0 +1,409 @@
> +// SPDX-License-Identifier: BSD-3-Clause
> +/*
> + * Copyright (c) 2024, Qualcomm Innovation Center, Inc. All rights reserved.
> + */
> +
> +#include <dt-bindings/regulator/qcom,rpmh-regulator.h>
> +#include "sm8650p.dtsi"
> +#include "pm8550.dtsi"
> +#include "pm8550b.dtsi"
> +#define PMK8550VE_SID 8
> +#include "pm8550ve.dtsi"
> +#include "pm8550vs.dtsi"
> +#include "pmk8550.dtsi"
> +
> +/ {
> +       aliases {
> +               serial1 = &uart14;
> +       };
> +
> +       vph_pwr: vph-pwr-regulator { };

Is this regulator a part of the module or a part of the carrier board?
If the latter is true, this must go to the carrier board DT file.

> +};
> +
> +&apps_rsc {
> +       regulators-0 {
> +               compatible = "qcom,pm8550-rpmh-regulators";
> +
> +               vdd-bob1-supply = <&vph_pwr>;
> +               vdd-bob2-supply = <&vph_pwr>;
> +               vdd-l2-l13-l14-supply = <&vreg_bob1>;
> +               vdd-l3-supply = <&vreg_s1c_1p2>;
> +               vdd-l5-l16-supply = <&vreg_bob1>;
> +               vdd-l6-l7-supply = <&vreg_bob1>;
> +               vdd-l8-l9-supply = <&vreg_bob1>;
> +               vdd-l11-supply = <&vreg_s1c_1p2>;
> +               vdd-l12-supply = <&vreg_s6c_1p8>;
> +               vdd-l15-supply = <&vreg_s6c_1p8>;
> +               vdd-l17-supply = <&vreg_bob2>;
> +
> +               qcom,pmic-id = "b";

[skipped]

> +
> +&qupv3_id_1 {
> +       status = "okay";
> +};

No GPI node being enabled?

> +
> +&tlmm {
> +       bt_default: bt-default-state {
> +               bt-en-pins {
> +                       pins = "gpio17";
> +                       function = "gpio";
> +                       drive-strength = <16>;
> +                       bias-disable;
> +               };
> +
> +               sw-ctrl-pins {
> +                       pins = "gpio18";
> +                       function = "gpio";
> +                       bias-pull-down;
> +               };
> +       };
> +};
> +
> +&uart14 {
> +       status = "okay";
> +
> +       bluetooth {
> +               compatible = "qcom,wcn7850-bt";
> +
> +               clocks = <&rpmhcc RPMH_RF_CLK1>;
> +
> +               vddio-supply = <&vreg_l3c_1p2>;
> +               vddaon-supply = <&vreg_l15b_1p8>;
> +               vdddig-supply = <&vreg_s3c_0p9>;
> +               vddrfa0p8-supply = <&vreg_s3c_0p9>;
> +               vddrfa1p2-supply = <&vreg_s1c_1p2>;
> +               vddrfa1p9-supply = <&vreg_s6c_1p8>;
> +
> +               max-speed = <3200000>;
> +
> +               enable-gpios = <&tlmm 17 GPIO_ACTIVE_HIGH>;
> +               swctrl-gpios = <&tlmm 18 GPIO_ACTIVE_HIGH>;
> +
> +               pinctrl-0 = <&bt_default>;
> +               pinctrl-names = "default";
> +       };
> +};
> --
> 2.25.1
>
>


-- 
With best wishes
Dmitry

Re: [RFC PATCH 1/6] dt-bindings: arm: qcom: Document sm8650p soc and AIM500 AIoT board

[Jingyi Wang]

Hi Krzysztof,

On 2/5/2024 8:33 PM, Krzysztof Kozlowski wrote:
> On 05/02/2024 12:57, Jingyi Wang wrote:
>> Document Qualcomm SM8650P SoC and AIM500 AIoT board.
> 
> Please describe shortly what is SM8650P and what are the differences
> with SM8650.
> 
>>
>> Signed-off-by: Jingyi Wang <quic_jingyw@quicinc.com>
>> ---
>>  Documentation/devicetree/bindings/arm/qcom.yaml | 9 +++++++++
>>  1 file changed, 9 insertions(+)
>>
>> diff --git a/Documentation/devicetree/bindings/arm/qcom.yaml b/Documentation/devicetree/bindings/arm/qcom.yaml
>> index 1999a5f2f254..e87ceb42853b 100644
>> --- a/Documentation/devicetree/bindings/arm/qcom.yaml
>> +++ b/Documentation/devicetree/bindings/arm/qcom.yaml
>> @@ -88,11 +88,13 @@ description: |
>>          sm8450
>>          sm8550
>>          sm8650
>> +        sm8650p
>>          x1e80100
>>  
>>    The 'board' element must be one of the following strings:
>>  
>>          adp
>> +        aim500-aiot
> 
> Drop this line.
> 
drop this line will cause fail dt binding check failure, any suggestion on that?
>>          cdp
>>          dragonboard
>>          idp
>> @@ -1051,6 +1053,13 @@ properties:
>>                - qcom,sm8650-qrd
>>            - const: qcom,sm8650
>>  
>> +      - items:
>> +          - enum:
>> +              - qcom,sm8650p-aim500-aiot
>> +          - const: qcom,sm8650p-aim500
>> +          - const: qcom,sm8650p
>> +          - const: qcom,sm8650
> 
> 
> 
> Best regards,
> Krzysztof
> 
Thanks,
Jingyi

Re: [RFC PATCH 1/6] dt-bindings: arm: qcom: Document sm8650p soc and AIM500 AIoT board

[Dmitry Baryshkov]

On Tue, 20 Feb 2024 at 11:00, Jingyi Wang <quic_jingyw@quicinc.com> wrote:
>
>
> Hi Krzysztof,
>
> On 2/5/2024 8:33 PM, Krzysztof Kozlowski wrote:
> > On 05/02/2024 12:57, Jingyi Wang wrote:
> >> Document Qualcomm SM8650P SoC and AIM500 AIoT board.
> >
> > Please describe shortly what is SM8650P and what are the differences
> > with SM8650.
> >
> >>
> >> Signed-off-by: Jingyi Wang <quic_jingyw@quicinc.com>
> >> ---
> >>  Documentation/devicetree/bindings/arm/qcom.yaml | 9 +++++++++
> >>  1 file changed, 9 insertions(+)
> >>
> >> diff --git a/Documentation/devicetree/bindings/arm/qcom.yaml b/Documentation/devicetree/bindings/arm/qcom.yaml
> >> index 1999a5f2f254..e87ceb42853b 100644
> >> --- a/Documentation/devicetree/bindings/arm/qcom.yaml
> >> +++ b/Documentation/devicetree/bindings/arm/qcom.yaml
> >> @@ -88,11 +88,13 @@ description: |
> >>          sm8450
> >>          sm8550
> >>          sm8650
> >> +        sm8650p
> >>          x1e80100
> >>
> >>    The 'board' element must be one of the following strings:
> >>
> >>          adp
> >> +        aim500-aiot
> >
> > Drop this line.
> >
> drop this line will cause fail dt binding check failure, any suggestion on that?

It will not, it is just a free-form text

> >>          cdp
> >>          dragonboard
> >>          idp
> >> @@ -1051,6 +1053,13 @@ properties:
> >>                - qcom,sm8650-qrd
> >>            - const: qcom,sm8650
> >>
> >> +      - items:
> >> +          - enum:
> >> +              - qcom,sm8650p-aim500-aiot
> >> +          - const: qcom,sm8650p-aim500
> >> +          - const: qcom,sm8650p
> >> +          - const: qcom,sm8650
> >
> >
> >
> > Best regards,
> > Krzysztof
> >
> Thanks,
> Jingyi
>


-- 
With best wishes
Dmitry

Re: [RFC PATCH 5/6] arm64: dts: qcom: add base AIM500 dtsi

[Jingyi Wang]

Hi Krzysztof,

On 2/5/2024 8:35 PM, Krzysztof Kozlowski wrote:
> On 05/02/2024 12:57, Jingyi Wang wrote:
>> Introduce aim500 board dtsi.
>>
>> AIM500 Series is a highly optimized family of modules designed to
>> support AIoT and Generative AI applications based on sm8650p with
>> PMIC and bluetooth functions etc.
>>
>> Co-developed-by: Tingwei Zhang <quic_tingweiz@quicinc.com>
>> Signed-off-by: Tingwei Zhang <quic_tingweiz@quicinc.com>
>> Signed-off-by: Jingyi Wang <quic_jingyw@quicinc.com>
>> ---
>>  arch/arm64/boot/dts/qcom/sm8650p-aim500.dtsi | 409 +++++++++++++++++++
>>  1 file changed, 409 insertions(+)
>>  create mode 100644 arch/arm64/boot/dts/qcom/sm8650p-aim500.dtsi
>>
>> diff --git a/arch/arm64/boot/dts/qcom/sm8650p-aim500.dtsi b/arch/arm64/boot/dts/qcom/sm8650p-aim500.dtsi
>> new file mode 100644
>> index 000000000000..cb857da8653b
>> --- /dev/null
>> +++ b/arch/arm64/boot/dts/qcom/sm8650p-aim500.dtsi
>> @@ -0,0 +1,409 @@
>> +// SPDX-License-Identifier: BSD-3-Clause
>> +/*
>> + * Copyright (c) 2024, Qualcomm Innovation Center, Inc. All rights reserved.
>> + */
>> +
>> +#include <dt-bindings/regulator/qcom,rpmh-regulator.h>
>> +#include "sm8650p.dtsi"
>> +#include "pm8550.dtsi"
>> +#include "pm8550b.dtsi"
>> +#define PMK8550VE_SID 8
>> +#include "pm8550ve.dtsi"
>> +#include "pm8550vs.dtsi"
>> +#include "pmk8550.dtsi"
>> +
>> +/ {
>> +	aliases {
>> +		serial1 = &uart14;
>> +	};
>> +
>> +	vph_pwr: vph-pwr-regulator { };
> 
> What is this? Why is it needed?
> 
> 
> Best regards,
> Krzysztof
> 
vph_pwr is the power supply which differs from board design, it is defined in sm8650p-aim500-aiot.dts,
and it is used in the sm8650p-aim500.dts for regulator supply, so we leave the node here.

Thanks,
Jingyi

Re: [RFC PATCH 5/6] arm64: dts: qcom: add base AIM500 dtsi

[Jingyi Wang]

Hi Dmitry,

On 2/5/2024 10:23 PM, Dmitry Baryshkov wrote:
> On Mon, 5 Feb 2024 at 14:00, Jingyi Wang <quic_jingyw@quicinc.com> wrote:
>>
>> Introduce aim500 board dtsi.
> 
> So, is it a board or a module?
> 
aim500 is a module, will fix the descrption.

>>
>> AIM500 Series is a highly optimized family of modules designed to
>> support AIoT and Generative AI applications based on sm8650p with
>> PMIC and bluetooth functions etc.
>>
>> Co-developed-by: Tingwei Zhang <quic_tingweiz@quicinc.com>
>> Signed-off-by: Tingwei Zhang <quic_tingweiz@quicinc.com>
>> Signed-off-by: Jingyi Wang <quic_jingyw@quicinc.com>
>> ---
>>  arch/arm64/boot/dts/qcom/sm8650p-aim500.dtsi | 409 +++++++++++++++++++
>>  1 file changed, 409 insertions(+)
>>  create mode 100644 arch/arm64/boot/dts/qcom/sm8650p-aim500.dtsi
>>
>> diff --git a/arch/arm64/boot/dts/qcom/sm8650p-aim500.dtsi b/arch/arm64/boot/dts/qcom/sm8650p-aim500.dtsi
>> new file mode 100644
>> index 000000000000..cb857da8653b
>> --- /dev/null
>> +++ b/arch/arm64/boot/dts/qcom/sm8650p-aim500.dtsi
>> @@ -0,0 +1,409 @@
>> +// SPDX-License-Identifier: BSD-3-Clause
>> +/*
>> + * Copyright (c) 2024, Qualcomm Innovation Center, Inc. All rights reserved.
>> + */
>> +
>> +#include <dt-bindings/regulator/qcom,rpmh-regulator.h>
>> +#include "sm8650p.dtsi"
>> +#include "pm8550.dtsi"
>> +#include "pm8550b.dtsi"
>> +#define PMK8550VE_SID 8
>> +#include "pm8550ve.dtsi"
>> +#include "pm8550vs.dtsi"
>> +#include "pmk8550.dtsi"
>> +
>> +/ {
>> +       aliases {
>> +               serial1 = &uart14;
>> +       };
>> +
>> +       vph_pwr: vph-pwr-regulator { };
> 
> Is this regulator a part of the module or a part of the carrier board?
> If the latter is true, this must go to the carrier board DT file.
> 

the vph_pwr regulator is defined in the aim500-aiot carrier board and used
in aim500 module.

>> +};
>> +
>> +&apps_rsc {
>> +       regulators-0 {
>> +               compatible = "qcom,pm8550-rpmh-regulators";
>> +
>> +               vdd-bob1-supply = <&vph_pwr>;
>> +               vdd-bob2-supply = <&vph_pwr>;
>> +               vdd-l2-l13-l14-supply = <&vreg_bob1>;
>> +               vdd-l3-supply = <&vreg_s1c_1p2>;
>> +               vdd-l5-l16-supply = <&vreg_bob1>;
>> +               vdd-l6-l7-supply = <&vreg_bob1>;
>> +               vdd-l8-l9-supply = <&vreg_bob1>;
>> +               vdd-l11-supply = <&vreg_s1c_1p2>;
>> +               vdd-l12-supply = <&vreg_s6c_1p8>;
>> +               vdd-l15-supply = <&vreg_s6c_1p8>;
>> +               vdd-l17-supply = <&vreg_bob2>;
>> +
>> +               qcom,pmic-id = "b";
> 
> [skipped]
> 
>> +
>> +&qupv3_id_1 {
>> +       status = "okay";
>> +};
> 
> No GPI node being enabled?
> 
will drop this node for there is no client under that.
>> +
>> +&tlmm {
>> +       bt_default: bt-default-state {
>> +               bt-en-pins {
>> +                       pins = "gpio17";
>> +                       function = "gpio";
>> +                       drive-strength = <16>;
>> +                       bias-disable;
>> +               };
>> +
>> +               sw-ctrl-pins {
>> +                       pins = "gpio18";
>> +                       function = "gpio";
>> +                       bias-pull-down;
>> +               };
>> +       };
>> +};
>> +
>> +&uart14 {
>> +       status = "okay";
>> +
>> +       bluetooth {
>> +               compatible = "qcom,wcn7850-bt";
>> +
>> +               clocks = <&rpmhcc RPMH_RF_CLK1>;
>> +
>> +               vddio-supply = <&vreg_l3c_1p2>;
>> +               vddaon-supply = <&vreg_l15b_1p8>;
>> +               vdddig-supply = <&vreg_s3c_0p9>;
>> +               vddrfa0p8-supply = <&vreg_s3c_0p9>;
>> +               vddrfa1p2-supply = <&vreg_s1c_1p2>;
>> +               vddrfa1p9-supply = <&vreg_s6c_1p8>;
>> +
>> +               max-speed = <3200000>;
>> +
>> +               enable-gpios = <&tlmm 17 GPIO_ACTIVE_HIGH>;
>> +               swctrl-gpios = <&tlmm 18 GPIO_ACTIVE_HIGH>;
>> +
>> +               pinctrl-0 = <&bt_default>;
>> +               pinctrl-names = "default";
>> +       };
>> +};
>> --
>> 2.25.1
>>
>>
> 
> 
Thanks,
Jingyi

Re: [RFC PATCH 5/6] arm64: dts: qcom: add base AIM500 dtsi

[Dmitry Baryshkov]

On Tue, 20 Feb 2024 at 11:17, Jingyi Wang <quic_jingyw@quicinc.com> wrote:
>
> Hi Dmitry,
>
> On 2/5/2024 10:23 PM, Dmitry Baryshkov wrote:
> > On Mon, 5 Feb 2024 at 14:00, Jingyi Wang <quic_jingyw@quicinc.com> wrote:
> >>
> >> Introduce aim500 board dtsi.
> >
> > So, is it a board or a module?
> >
> aim500 is a module, will fix the descrption.
>
> >>
> >> AIM500 Series is a highly optimized family of modules designed to
> >> support AIoT and Generative AI applications based on sm8650p with
> >> PMIC and bluetooth functions etc.
> >>
> >> Co-developed-by: Tingwei Zhang <quic_tingweiz@quicinc.com>
> >> Signed-off-by: Tingwei Zhang <quic_tingweiz@quicinc.com>
> >> Signed-off-by: Jingyi Wang <quic_jingyw@quicinc.com>
> >> ---
> >>  arch/arm64/boot/dts/qcom/sm8650p-aim500.dtsi | 409 +++++++++++++++++++
> >>  1 file changed, 409 insertions(+)
> >>  create mode 100644 arch/arm64/boot/dts/qcom/sm8650p-aim500.dtsi
> >>
> >> diff --git a/arch/arm64/boot/dts/qcom/sm8650p-aim500.dtsi b/arch/arm64/boot/dts/qcom/sm8650p-aim500.dtsi
> >> new file mode 100644
> >> index 000000000000..cb857da8653b
> >> --- /dev/null
> >> +++ b/arch/arm64/boot/dts/qcom/sm8650p-aim500.dtsi
> >> @@ -0,0 +1,409 @@
> >> +// SPDX-License-Identifier: BSD-3-Clause
> >> +/*
> >> + * Copyright (c) 2024, Qualcomm Innovation Center, Inc. All rights reserved.
> >> + */
> >> +
> >> +#include <dt-bindings/regulator/qcom,rpmh-regulator.h>
> >> +#include "sm8650p.dtsi"
> >> +#include "pm8550.dtsi"
> >> +#include "pm8550b.dtsi"
> >> +#define PMK8550VE_SID 8
> >> +#include "pm8550ve.dtsi"
> >> +#include "pm8550vs.dtsi"
> >> +#include "pmk8550.dtsi"
> >> +
> >> +/ {
> >> +       aliases {
> >> +               serial1 = &uart14;
> >> +       };
> >> +
> >> +       vph_pwr: vph-pwr-regulator { };
> >
> > Is this regulator a part of the module or a part of the carrier board?
> > If the latter is true, this must go to the carrier board DT file.
> >
>
> the vph_pwr regulator is defined in the aim500-aiot carrier board and used
> in aim500 module.

If it is defined in the carrier board, then please move it and
corresponding supply entries to the carrier board dts. Other devices
using the SoM can have different power tree.

While we are at it, could you please rename the node to regulator-vph-pwr?


-- 
With best wishes
Dmitry

Re: [RFC PATCH 1/6] dt-bindings: arm: qcom: Document sm8650p soc and AIM500 AIoT board

[Jingyi Wang]

Hi Krzysztof & Dmitry 

On 2/20/2024 5:06 PM, Dmitry Baryshkov wrote:
> On Tue, 20 Feb 2024 at 11:00, Jingyi Wang <quic_jingyw@quicinc.com> wrote:
>>
>>
>> Hi Krzysztof,
>>
>> On 2/5/2024 8:33 PM, Krzysztof Kozlowski wrote:
>>> On 05/02/2024 12:57, Jingyi Wang wrote:
>>>> Document Qualcomm SM8650P SoC and AIM500 AIoT board.
>>>
>>> Please describe shortly what is SM8650P and what are the differences
>>> with SM8650.
>>>

sm8650p has same base functions as sm8650 without modem-RF system.
Will update the description.

>>>>
>>>> Signed-off-by: Jingyi Wang <quic_jingyw@quicinc.com>
>>>> ---
>>>>  Documentation/devicetree/bindings/arm/qcom.yaml | 9 +++++++++
>>>>  1 file changed, 9 insertions(+)
>>>>
>>>> diff --git a/Documentation/devicetree/bindings/arm/qcom.yaml b/Documentation/devicetree/bindings/arm/qcom.yaml
>>>> index 1999a5f2f254..e87ceb42853b 100644
>>>> --- a/Documentation/devicetree/bindings/arm/qcom.yaml
>>>> +++ b/Documentation/devicetree/bindings/arm/qcom.yaml
>>>> @@ -88,11 +88,13 @@ description: |
>>>>          sm8450
>>>>          sm8550
>>>>          sm8650
>>>> +        sm8650p
>>>>          x1e80100
>>>>
>>>>    The 'board' element must be one of the following strings:
>>>>
>>>>          adp
>>>> +        aim500-aiot
>>>
>>> Drop this line.
>>>
>> drop this line will cause fail dt binding check failure, any suggestion on that?
> 
> It will not, it is just a free-form text
> 
will drop that.
>>>>          cdp
>>>>          dragonboard
>>>>          idp
>>>> @@ -1051,6 +1053,13 @@ properties:
>>>>                - qcom,sm8650-qrd
>>>>            - const: qcom,sm8650
>>>>
>>>> +      - items:
>>>> +          - enum:
>>>> +              - qcom,sm8650p-aim500-aiot
>>>> +          - const: qcom,sm8650p-aim500
>>>> +          - const: qcom,sm8650p
>>>> +          - const: qcom,sm8650
>>>
>>>
>>>
>>> Best regards,
>>> Krzysztof
>>>
>> Thanks,
>> Jingyi
>>
> 
> 
Thanks,
Jingyi

Re: [RFC PATCH 1/6] dt-bindings: arm: qcom: Document sm8650p soc and AIM500 AIoT board

[Krzysztof Kozlowski]

On 20/02/2024 09:55, Jingyi Wang wrote:
> 
> Hi Krzysztof,
> 
> On 2/5/2024 8:33 PM, Krzysztof Kozlowski wrote:
>> On 05/02/2024 12:57, Jingyi Wang wrote:
>>> Document Qualcomm SM8650P SoC and AIM500 AIoT board.
>>
>> Please describe shortly what is SM8650P and what are the differences
>> with SM8650.
>>
>>>
>>> Signed-off-by: Jingyi Wang <quic_jingyw@quicinc.com>
>>> ---
>>>  Documentation/devicetree/bindings/arm/qcom.yaml | 9 +++++++++
>>>  1 file changed, 9 insertions(+)
>>>
>>> diff --git a/Documentation/devicetree/bindings/arm/qcom.yaml b/Documentation/devicetree/bindings/arm/qcom.yaml
>>> index 1999a5f2f254..e87ceb42853b 100644
>>> --- a/Documentation/devicetree/bindings/arm/qcom.yaml
>>> +++ b/Documentation/devicetree/bindings/arm/qcom.yaml
>>> @@ -88,11 +88,13 @@ description: |
>>>          sm8450
>>>          sm8550
>>>          sm8650
>>> +        sm8650p
>>>          x1e80100
>>>  
>>>    The 'board' element must be one of the following strings:
>>>  
>>>          adp
>>> +        aim500-aiot
>>
>> Drop this line.
>>
> drop this line will cause fail dt binding check failure, any suggestion on that?

Really? How?



Best regards,
Krzysztof

Re: [RFC PATCH 5/6] arm64: dts: qcom: add base AIM500 dtsi

[Krzysztof Kozlowski]

On 20/02/2024 10:11, Jingyi Wang wrote:
> Hi Krzysztof,
> 
> On 2/5/2024 8:35 PM, Krzysztof Kozlowski wrote:
>> On 05/02/2024 12:57, Jingyi Wang wrote:
>>> Introduce aim500 board dtsi.
>>>
>>> AIM500 Series is a highly optimized family of modules designed to
>>> support AIoT and Generative AI applications based on sm8650p with
>>> PMIC and bluetooth functions etc.
>>>
>>> Co-developed-by: Tingwei Zhang <quic_tingweiz@quicinc.com>
>>> Signed-off-by: Tingwei Zhang <quic_tingweiz@quicinc.com>
>>> Signed-off-by: Jingyi Wang <quic_jingyw@quicinc.com>
>>> ---
>>>  arch/arm64/boot/dts/qcom/sm8650p-aim500.dtsi | 409 +++++++++++++++++++
>>>  1 file changed, 409 insertions(+)
>>>  create mode 100644 arch/arm64/boot/dts/qcom/sm8650p-aim500.dtsi
>>>
>>> diff --git a/arch/arm64/boot/dts/qcom/sm8650p-aim500.dtsi b/arch/arm64/boot/dts/qcom/sm8650p-aim500.dtsi
>>> new file mode 100644
>>> index 000000000000..cb857da8653b
>>> --- /dev/null
>>> +++ b/arch/arm64/boot/dts/qcom/sm8650p-aim500.dtsi
>>> @@ -0,0 +1,409 @@
>>> +// SPDX-License-Identifier: BSD-3-Clause
>>> +/*
>>> + * Copyright (c) 2024, Qualcomm Innovation Center, Inc. All rights reserved.
>>> + */
>>> +
>>> +#include <dt-bindings/regulator/qcom,rpmh-regulator.h>
>>> +#include "sm8650p.dtsi"
>>> +#include "pm8550.dtsi"
>>> +#include "pm8550b.dtsi"
>>> +#define PMK8550VE_SID 8
>>> +#include "pm8550ve.dtsi"
>>> +#include "pm8550vs.dtsi"
>>> +#include "pmk8550.dtsi"
>>> +
>>> +/ {
>>> +	aliases {
>>> +		serial1 = &uart14;
>>> +	};
>>> +
>>> +	vph_pwr: vph-pwr-regulator { };
>>
>> What is this? Why is it needed?
>>
>>
>> Best regards,
>> Krzysztof
>>
> vph_pwr is the power supply which differs from board design, it is defined in sm8650p-aim500-aiot.dts,
> and it is used in the sm8650p-aim500.dts for regulator supply, so we leave the node here.

How an empty, unused node is a power supply?

Best regards,
Krzysztof

Re: [RFC PATCH 1/6] dt-bindings: arm: qcom: Document sm8650p soc and AIM500 AIoT board

[Jingyi Wang]

Hi Krzysztof,

On 2/20/2024 5:43 PM, Krzysztof Kozlowski wrote:
> On 20/02/2024 09:55, Jingyi Wang wrote:
>>
>> Hi Krzysztof,
>>
>> On 2/5/2024 8:33 PM, Krzysztof Kozlowski wrote:
>>> On 05/02/2024 12:57, Jingyi Wang wrote:
>>>> Document Qualcomm SM8650P SoC and AIM500 AIoT board.
>>>
>>> Please describe shortly what is SM8650P and what are the differences
>>> with SM8650.
>>>
>>>>
>>>> Signed-off-by: Jingyi Wang <quic_jingyw@quicinc.com>
>>>> ---
>>>>  Documentation/devicetree/bindings/arm/qcom.yaml | 9 +++++++++
>>>>  1 file changed, 9 insertions(+)
>>>>
>>>> diff --git a/Documentation/devicetree/bindings/arm/qcom.yaml b/Documentation/devicetree/bindings/arm/qcom.yaml
>>>> index 1999a5f2f254..e87ceb42853b 100644
>>>> --- a/Documentation/devicetree/bindings/arm/qcom.yaml
>>>> +++ b/Documentation/devicetree/bindings/arm/qcom.yaml
>>>> @@ -88,11 +88,13 @@ description: |
>>>>          sm8450
>>>>          sm8550
>>>>          sm8650
>>>> +        sm8650p
>>>>          x1e80100
>>>>  
>>>>    The 'board' element must be one of the following strings:
>>>>  
>>>>          adp
>>>> +        aim500-aiot
>>>
>>> Drop this line.
>>>
>> drop this line will cause fail dt binding check failure, any suggestion on that?
> 
> Really? How?
> 
> 
> 
> Best regards,
> Krzysztof
> 
Sorry I made some mistakes, have just checked that remove this should be fine.

Thanks,
Jingyi 

Re: [RFC PATCH 5/6] arm64: dts: qcom: add base AIM500 dtsi

[Jingyi Wang]

Hi Dmitry,

On 2/20/2024 5:19 PM, Dmitry Baryshkov wrote:
> On Tue, 20 Feb 2024 at 11:17, Jingyi Wang <quic_jingyw@quicinc.com> wrote:
>>
>> Hi Dmitry,
>>
>> On 2/5/2024 10:23 PM, Dmitry Baryshkov wrote:
>>> On Mon, 5 Feb 2024 at 14:00, Jingyi Wang <quic_jingyw@quicinc.com> wrote:
>>>>
>>>> Introduce aim500 board dtsi.
>>>
>>> So, is it a board or a module?
>>>
>> aim500 is a module, will fix the descrption.
>>
>>>>
>>>> AIM500 Series is a highly optimized family of modules designed to
>>>> support AIoT and Generative AI applications based on sm8650p with
>>>> PMIC and bluetooth functions etc.
>>>>
>>>> Co-developed-by: Tingwei Zhang <quic_tingweiz@quicinc.com>
>>>> Signed-off-by: Tingwei Zhang <quic_tingweiz@quicinc.com>
>>>> Signed-off-by: Jingyi Wang <quic_jingyw@quicinc.com>
>>>> ---
>>>>  arch/arm64/boot/dts/qcom/sm8650p-aim500.dtsi | 409 +++++++++++++++++++
>>>>  1 file changed, 409 insertions(+)
>>>>  create mode 100644 arch/arm64/boot/dts/qcom/sm8650p-aim500.dtsi
>>>>
>>>> diff --git a/arch/arm64/boot/dts/qcom/sm8650p-aim500.dtsi b/arch/arm64/boot/dts/qcom/sm8650p-aim500.dtsi
>>>> new file mode 100644
>>>> index 000000000000..cb857da8653b
>>>> --- /dev/null
>>>> +++ b/arch/arm64/boot/dts/qcom/sm8650p-aim500.dtsi
>>>> @@ -0,0 +1,409 @@
>>>> +// SPDX-License-Identifier: BSD-3-Clause
>>>> +/*
>>>> + * Copyright (c) 2024, Qualcomm Innovation Center, Inc. All rights reserved.
>>>> + */
>>>> +
>>>> +#include <dt-bindings/regulator/qcom,rpmh-regulator.h>
>>>> +#include "sm8650p.dtsi"
>>>> +#include "pm8550.dtsi"
>>>> +#include "pm8550b.dtsi"
>>>> +#define PMK8550VE_SID 8
>>>> +#include "pm8550ve.dtsi"
>>>> +#include "pm8550vs.dtsi"
>>>> +#include "pmk8550.dtsi"
>>>> +
>>>> +/ {
>>>> +       aliases {
>>>> +               serial1 = &uart14;
>>>> +       };
>>>> +
>>>> +       vph_pwr: vph-pwr-regulator { };
>>>
>>> Is this regulator a part of the module or a part of the carrier board?
>>> If the latter is true, this must go to the carrier board DT file.
>>>
>>
>> the vph_pwr regulator is defined in the aim500-aiot carrier board and used
>> in aim500 module.
> 
> If it is defined in the carrier board, then please move it and
> corresponding supply entries to the carrier board dts. Other devices
> using the SoM can have different power tree.
> 
> While we are at it, could you please rename the node to regulator-vph-pwr?
> 
> 
will rename the node and move it to sm8650p-aim500-aiot.dts

Thanks,
Jingyi

Re: [RFC PATCH 5/6] arm64: dts: qcom: add base AIM500 dtsi

[Aiqun Yu (Maria)]

On 2/20/2024 6:06 PM, Jingyi Wang wrote:
> Hi Dmitry,
> 
> On 2/20/2024 5:19 PM, Dmitry Baryshkov wrote:
>> On Tue, 20 Feb 2024 at 11:17, Jingyi Wang <quic_jingyw@quicinc.com> wrote:
>>>
>>> Hi Dmitry,
>>>
>>> On 2/5/2024 10:23 PM, Dmitry Baryshkov wrote:
>>>> On Mon, 5 Feb 2024 at 14:00, Jingyi Wang <quic_jingyw@quicinc.com> wrote:
>>>>>
>>>>> Introduce aim500 board dtsi.
>>>>
>>>> So, is it a board or a module?
>>>>
>>> aim500 is a module, will fix the descrption.
>>>
>>>>>
>>>>> AIM500 Series is a highly optimized family of modules designed to
>>>>> support AIoT and Generative AI applications based on sm8650p with
>>>>> PMIC and bluetooth functions etc.
>>>>>
>>>>> Co-developed-by: Tingwei Zhang <quic_tingweiz@quicinc.com>
>>>>> Signed-off-by: Tingwei Zhang <quic_tingweiz@quicinc.com>
>>>>> Signed-off-by: Jingyi Wang <quic_jingyw@quicinc.com>
>>>>> ---
>>>>>   arch/arm64/boot/dts/qcom/sm8650p-aim500.dtsi | 409 +++++++++++++++++++
>>>>>   1 file changed, 409 insertions(+)
>>>>>   create mode 100644 arch/arm64/boot/dts/qcom/sm8650p-aim500.dtsi
>>>>>
>>>>> diff --git a/arch/arm64/boot/dts/qcom/sm8650p-aim500.dtsi b/arch/arm64/boot/dts/qcom/sm8650p-aim500.dtsi
>>>>> new file mode 100644
>>>>> index 000000000000..cb857da8653b
>>>>> --- /dev/null
>>>>> +++ b/arch/arm64/boot/dts/qcom/sm8650p-aim500.dtsi
>>>>> @@ -0,0 +1,409 @@
>>>>> +// SPDX-License-Identifier: BSD-3-Clause
>>>>> +/*
>>>>> + * Copyright (c) 2024, Qualcomm Innovation Center, Inc. All rights reserved.
>>>>> + */
>>>>> +
>>>>> +#include <dt-bindings/regulator/qcom,rpmh-regulator.h>
>>>>> +#include "sm8650p.dtsi"
>>>>> +#include "pm8550.dtsi"
>>>>> +#include "pm8550b.dtsi"
>>>>> +#define PMK8550VE_SID 8
>>>>> +#include "pm8550ve.dtsi"
>>>>> +#include "pm8550vs.dtsi"
>>>>> +#include "pmk8550.dtsi"
>>>>> +
>>>>> +/ {
>>>>> +       aliases {
>>>>> +               serial1 = &uart14;
>>>>> +       };
>>>>> +
>>>>> +       vph_pwr: vph-pwr-regulator { };
>>>>
>>>> Is this regulator a part of the module or a part of the carrier board?
>>>> If the latter is true, this must go to the carrier board DT file.
>>>>
>>>
>>> the vph_pwr regulator is defined in the aim500-aiot carrier board and used
>>> in aim500 module.
>>
>> If it is defined in the carrier board, then please move it and
>> corresponding supply entries to the carrier board dts. Other devices
>> using the SoM can have different power tree.
>>
>> While we are at it, could you please rename the node to regulator-vph-pwr?
>>
>>
> will rename the node and move it to sm8650p-aim500-aiot.dts

Shall we have the VPH_PWR implementation inside the board dts file, and 
have the supply entries which used the VPH_PWR inside the SOM.dtsi file?

The VPH_PWR is an input IO of SOM. And the corresponding supply entries 
is inside the SOM hardware design as well.

The VPH_PWR as a fixed regulator implementation is the board design, it 
can be changed to other design from different boards.

Here is a simple diagram to show the hardware description of the VPH_PWR 
related design:

+------------------------------------------------------+ 
 

|                 Board                                | 
 

|                                                      | 
 

|           +-----------------+                        | 
 

|power----->| Fixed regulator-----------+              | 
 

|           +-----------------+         |              | 
 

|                                       |              | 
 

|                                       v VPH_PWR      | 
 

|                  +------|----------------------+     | 
 

|                  |      |    SOM       |       |     | 
 

|                  |      |              |       |     | 
 

|                  |      vVPH_PWR       vVPM_PWR|     | 
 

|                  |  +------+       +------+    |     | 
 

|                  |  | pmic1|       |pmic2 |    |     | 
 

|                  |  +------+       +------+    |     | 
 

|                  |                             |     | 
 

|                  +-----------------------------+     | 
 

+------------------------------------------------------+ 
 



> 
> Thanks,
> Jingyi

-- 
Thx and BRs,
Aiqun(Maria) Yu

Re: [RFC PATCH 4/6] arm64: dts: qcom: sm8650p: introduce sm8650p dtsi

[neil.armstrong]

On 05/02/2024 12:57, Jingyi Wang wrote:
> Introduce sm8650p dtsi, sm8650p has same base functions
> as sm8650 with different memory regions.
> 
> There are 3 types of reserved memory regions here:
> 1. Firmware related regions.
>      This will be described as: reserved-region@address. Current
> reserved-region may have reserved area which was not yet used, release
> note of the firmware can have such kind of information.
> 2. Firmware related which shared with kernel access.
>      Each region will have a specific node with specific label name for
> later phandle reference from other driver dt node. May overlapping with
> above type regions.
> 3. PIL regions.
>      PIL regions are allocated by kernel and assigned to subsystem
> firmware later.
> Here is a map for this platform:
> 0x100000000 +------------------+
>              |                  |
>              | Firmware Related |
>              |                  |
>   0xd8000000 +------------------+
>              |                  |
>              | Kernel Available |
>              |                  |
>   0xA7000000 +------------------+
>              |                  |
>              |    PIL Region    |
>              |                  |
>   0x8BC00000 +------------------+
>              |                  |
>              | Firmware Related |
>              |                  |
>   0x80000000 +------------------+
> Note that:
> 1. 0xA7000000 to 0xA8000000 was used by bootloader as well, not suggest
> for other usage.
> 2. Kernel start address was start at 0xA8000000.
> 
> Signed-off-by: Jingyi Wang <quic_jingyw@quicinc.com>
> ---
>   arch/arm64/boot/dts/qcom/sm8650p.dtsi | 180 ++++++++++++++++++++++++++
>   1 file changed, 180 insertions(+)
>   create mode 100644 arch/arm64/boot/dts/qcom/sm8650p.dtsi
> 
> diff --git a/arch/arm64/boot/dts/qcom/sm8650p.dtsi b/arch/arm64/boot/dts/qcom/sm8650p.dtsi
> new file mode 100644
> index 000000000000..26dfe315b49d
> --- /dev/null
> +++ b/arch/arm64/boot/dts/qcom/sm8650p.dtsi
> @@ -0,0 +1,180 @@
> +// SPDX-License-Identifier: BSD-3-Clause
> +/*
> + * Copyright (c) 2024, Qualcomm Innovation Center, Inc. All rights reserved.
> + */
> +
> +#include "sm8650.dtsi"
> +
> +/delete-node/ &reserved_memory;
> +
> +/ {
> +	reserved_memory: reserved-memory {
> +		#address-cells = <2>;
> +		#size-cells = <2>;
> +		ranges;
> +
> +		/*
> +		 * There are 3 types of reserved memory regions here:
> +		 * 1. Firmware related regions.
> +		 *     This will be described as: reserved-region@address. Current
> +		 * reserved-region may have reserved area which was not yet used,
> +		 * release note of the firmware can have such kind of information.
> +		 * 2. Firmware related which shared with kernel access.
> +		 *     Each region will have a specific node with specific label
> +		 * name for later phandle reference from other driver dt node. May
> +		 * overlapping with above type regions.
> +		 * 3. PIL regions.
> +		 *     PIL regions are allocated by kernel and assigned to subsystem
> +		 * firmware later.
> +		 * Here is a map for this platform:
> +		 * 0x100000000 +------------------+
> +		 *             |                  |
> +		 *             | Firmware Related |
> +		 *             |                  |
> +		 *  0xd8000000 +------------------+
> +		 *             |                  |
> +		 *             | Kernel Available |
> +		 *             |                  |
> +		 *  0xA7000000 +------------------+
> +		 *             |                  |
> +		 *             |    PIL Region    |
> +		 *             |                  |
> +		 *  0x8BC00000 +------------------+
> +		 *             |                  |
> +		 *             | Firmware Related |
> +		 *             |                  |
> +		 *  0x80000000 +------------------+
> +		 * Note that:
> +		 * 1. 0xA7000000 to 0xA8000000 was used by bootloader as well, not
> +		 * suggest for other usage.
> +		 * 2. Kernel start address was start at 0xA8000000.
> +		 */
> +
> +		/* Firmware related regions */
> +		reserved-region@80000000 {
> +			reg = <0x0 0x80000000 0x0 0xbc00000>;
> +			no-map;
> +		};

Ok this region goes up to 0x8BC00000 and so overlaps with the next regions:

> +
> +		aop_image_mem: aop-image-region@81c00000 {
> +			reg = <0x0 0x81c00000 0x0 0x60000>;
> +			no-map;
> +		};
> +
> +		aop_cmd_db_mem: aop-cmd-db-region@81c60000 {
> +			compatible = "qcom,cmd-db";
> +			reg = <0x0 0x81c60000 0x0 0x20000>;
> +			no-map;
> +		};
> +
> +		aop_config_mem: aop-config-region@81c80000 {
> +			no-map;
> +			reg = <0x0 0x81c80000 0x0 0x20000>;
> +		};
> +
> +		smem_mem: smem-region@81d00000 {
> +			compatible = "qcom,smem";
> +			reg = <0x0 0x81d00000 0x0 0x200000>;
> +			hwlocks = <&tcsr_mutex 3>;
> +			no-map;
> +		};
> +
> +		adsp_mhi_mem: adsp-mhi-region@81f00000 {
> +			reg = <0x0 0x81f00000 0x0 0x20000>;
> +			no-map;
> +		};
> +
> +		global_sync_mem: global-sync@82600000 {
> +			reg = <0 0x82600000 0 0x100000>;
> +			no-map;
> +		};
> +
> +		mpss_dsm_mem: mpss-dsm@86b00000 {
> +			reg = <0 0x86b00000 0 0x4900000>;
> +			no-map;
> +		};
> +
> +		mpss_dsm_mem_2: mpss-dsm-2@8b400000 {
> +			reg = <0 0x8b400000 0 0x800000>;
> +			no-map;
> +		};

up to here

Please fix this,

I just checked against plain sm8650.dtsi and actually the memory adresses are the same.

So what's the _real_ difference here ? Just drop the superfluous memory zones and redefine them if needed.

Thanks,
Neil

> +
> +		/* PIL region */
> +		mpss_mem: mpss-region@8bc00000 {
> +			reg = <0x0 0x8bc00000 0x0 0xf400000>;
> +			no-map;
> +		};
> +
> +		q6_mpss_dtb_mem: q6-mpss-dtb-region@9b000000 {
> +			reg = <0x0 0x9b000000 0x0 0x80000>;
> +			no-map;
> +		};
> +
> +		ipa_fw_mem: ipa-fw-region@9b080000 {
> +			reg = <0x0 0x9b080000 0x0 0x10000>;
> +			no-map;
> +		};
> +
> +		ipa_gsi_mem: ipa-gsi-region@9b090000 {
> +			reg = <0x0 0x9b090000 0x0 0xa000>;
> +			no-map;
> +		};
> +
> +		gpu_micro_code_mem: gpu-micro-code-region@9b09a000 {
> +			reg = <0x0 0x9b09a000 0x0 0x2000>;
> +			no-map;
> +		};
> +
> +		spss_region_mem: spss-region@9b0a0000 {
> +			reg = <0x0 0x9b0a0000 0x0 0x1e0000>;
> +			no-map;
> +		};
> +
> +		spu_secure_shared_memory_mem: spu-secure-shared-memory-region@9b280000 {
> +			reg = <0x0 0x9b280000 0x0 0x80000>;
> +			no-map;
> +		};
> +
> +		camera_mem: camera-region@9b300000 {
> +			reg = <0x0 0x9b300000 0x0 0x800000>;
> +			no-map;
> +		};
> +
> +		video_mem: video-region@9bb00000 {
> +			reg = <0x0 0x9bb00000 0x0 0x800000>;
> +			no-map;
> +		};
> +
> +		cvp_mem: cvp-region@9c300000 {
> +			reg = <0x0 0x9c300000 0x0 0x700000>;
> +			no-map;
> +		};
> +
> +		cdsp_mem: cdsp-region@9ca00000 {
> +			reg = <0x0 0x9ca00000 0x0 0x1400000>;
> +			no-map;
> +		};
> +
> +		q6_cdsp_dtb_mem: q6-cdsp-dtb-region@9de00000 {
> +			reg = <0x0 0x9de00000 0x0 0x80000>;
> +			no-map;
> +		};
> +
> +		q6_adsp_dtb_mem: q6-adsp-dtb-region@9de80000 {
> +			reg = <0x0 0x9de80000 0x0 0x80000>;
> +			no-map;
> +		};
> +
> +		adspslpi_mem: adspslpi-region@9df00000 {
> +			reg = <0x0 0x9df00000 0x0 0x4080000>;
> +			no-map;
> +		};
> +
> +		/* Firmware related regions */
> +		reserved-region@d8000000 {
> +			reg = <0x0 0xd8000000 0x0 0x28000000>;
> +			no-map;
> +		};
> +
> +	};
> +};

Re: [RFC PATCH 4/6] arm64: dts: qcom: sm8650p: introduce sm8650p dtsi

[Aiqun Yu (Maria)]

On 2/22/2024 9:21 PM, neil.armstrong@linaro.org wrote:
> On 05/02/2024 12:57, Jingyi Wang wrote:
>> Introduce sm8650p dtsi, sm8650p has same base functions
>> as sm8650 with different memory regions.
>>
>> There are 3 types of reserved memory regions here:
>> 1. Firmware related regions.
>>      This will be described as: reserved-region@address. Current
>> reserved-region may have reserved area which was not yet used, release
>> note of the firmware can have such kind of information.
>> 2. Firmware related which shared with kernel access.
>>      Each region will have a specific node with specific label name for
>> later phandle reference from other driver dt node. May overlapping with
>> above type regions.
>> 3. PIL regions.
>>      PIL regions are allocated by kernel and assigned to subsystem
>> firmware later.
>> Here is a map for this platform:
>> 0x100000000 +------------------+
>>              |                  |
>>              | Firmware Related |
>>              |                  |
>>   0xd8000000 +------------------+
>>              |                  |
>>              | Kernel Available |
>>              |                  |
>>   0xA7000000 +------------------+
>>              |                  |
>>              |    PIL Region    |
>>              |                  |
>>   0x8BC00000 +------------------+
>>              |                  |
>>              | Firmware Related |
>>              |                  |
>>   0x80000000 +------------------+
>> Note that:
>> 1. 0xA7000000 to 0xA8000000 was used by bootloader as well, not suggest
>> for other usage.
>> 2. Kernel start address was start at 0xA8000000.
>>
>> Signed-off-by: Jingyi Wang <quic_jingyw@quicinc.com>
>> ---
>>   arch/arm64/boot/dts/qcom/sm8650p.dtsi | 180 ++++++++++++++++++++++++++
>>   1 file changed, 180 insertions(+)
>>   create mode 100644 arch/arm64/boot/dts/qcom/sm8650p.dtsi
>>
>> diff --git a/arch/arm64/boot/dts/qcom/sm8650p.dtsi 
>> b/arch/arm64/boot/dts/qcom/sm8650p.dtsi
>> new file mode 100644
>> index 000000000000..26dfe315b49d
>> --- /dev/null
>> +++ b/arch/arm64/boot/dts/qcom/sm8650p.dtsi
>> @@ -0,0 +1,180 @@
>> +// SPDX-License-Identifier: BSD-3-Clause
>> +/*
>> + * Copyright (c) 2024, Qualcomm Innovation Center, Inc. All rights 
>> reserved.
>> + */
>> +
>> +#include "sm8650.dtsi"
>> +
>> +/delete-node/ &reserved_memory;
>> +
>> +/ {
>> +    reserved_memory: reserved-memory {
>> +        #address-cells = <2>;
>> +        #size-cells = <2>;
>> +        ranges;
>> +
>> +        /*
>> +         * There are 3 types of reserved memory regions here:
>> +         * 1. Firmware related regions.
>> +         *     This will be described as: reserved-region@address. 
>> Current
>> +         * reserved-region may have reserved area which was not yet 
>> used,
>> +         * release note of the firmware can have such kind of 
>> information.
>> +         * 2. Firmware related which shared with kernel access.
>> +         *     Each region will have a specific node with specific label
>> +         * name for later phandle reference from other driver dt 
>> node. May
>> +         * overlapping with above type regions.
>> +         * 3. PIL regions.
>> +         *     PIL regions are allocated by kernel and assigned to 
>> subsystem
>> +         * firmware later.
>> +         * Here is a map for this platform:
>> +         * 0x100000000 +------------------+
>> +         *             |                  |
>> +         *             | Firmware Related |
>> +         *             |                  |
>> +         *  0xd8000000 +------------------+
>> +         *             |                  |
>> +         *             | Kernel Available |
>> +         *             |                  |
>> +         *  0xA7000000 +------------------+
>> +         *             |                  |
>> +         *             |    PIL Region    |
>> +         *             |                  |
>> +         *  0x8BC00000 +------------------+
>> +         *             |                  |
>> +         *             | Firmware Related |
>> +         *             |                  |
>> +         *  0x80000000 +------------------+
>> +         * Note that:
>> +         * 1. 0xA7000000 to 0xA8000000 was used by bootloader as 
>> well, not
>> +         * suggest for other usage.
>> +         * 2. Kernel start address was start at 0xA8000000.
>> +         */
>> +
>> +        /* Firmware related regions */
>> +        reserved-region@80000000 {
>> +            reg = <0x0 0x80000000 0x0 0xbc00000>;
>> +            no-map;
>> +        };
> 
> Ok this region goes up to 0x8BC00000 and so overlaps with the next regions:
The idea here is to reserve more needed ddr regions for different 
version of firmware compatibility. While inside this region which shared 
device memory from firmware to kernel, it is still needed to have node 
information in the device tree.

More clear reference here for the firmware needed no-map reserved region 
diagram, take the smem_mem here to be exposed shared read to kernel:
*  0x8BC00000 +------------------+
*             |                  |
*             | reserved_region2 |
*  0x81c60000 +------------------+
*             |    smem_mem      |
*  0x81c00000 +------------------+
*             |  reserved_region1|
*  0x80000000 +------------------+

what's the suggestion here for this requirement?:
option 1: have a big region_reserved, and then have smem_mem overlap 
reserved region node information inside the dt.
option 2: Have each separate "reserved_region1 node + smem_mem node + 
reserved_region2 node".
other options?

> 
>> +
>> +        aop_image_mem: aop-image-region@81c00000 {
>> +            reg = <0x0 0x81c00000 0x0 0x60000>;
>> +            no-map;
>> +        };
>> +
>> +        aop_cmd_db_mem: aop-cmd-db-region@81c60000 {
>> +            compatible = "qcom,cmd-db";
>> +            reg = <0x0 0x81c60000 0x0 0x20000>;
>> +            no-map;
>> +        };
>> +
>> +        aop_config_mem: aop-config-region@81c80000 {
>> +            no-map;
>> +            reg = <0x0 0x81c80000 0x0 0x20000>;
>> +        };
>> +
>> +        smem_mem: smem-region@81d00000 {
>> +            compatible = "qcom,smem";
>> +            reg = <0x0 0x81d00000 0x0 0x200000>;
>> +            hwlocks = <&tcsr_mutex 3>;
>> +            no-map;
>> +        };
>> +
>> +        adsp_mhi_mem: adsp-mhi-region@81f00000 {
>> +            reg = <0x0 0x81f00000 0x0 0x20000>;
>> +            no-map;
>> +        };
>> +
>> +        global_sync_mem: global-sync@82600000 {
>> +            reg = <0 0x82600000 0 0x100000>;
>> +            no-map;
>> +        };
>> +
>> +        mpss_dsm_mem: mpss-dsm@86b00000 {
>> +            reg = <0 0x86b00000 0 0x4900000>;
>> +            no-map;
>> +        };
>> +
>> +        mpss_dsm_mem_2: mpss-dsm-2@8b400000 {
>> +            reg = <0 0x8b400000 0 0x800000>;
>> +            no-map;
>> +        };
> 
> up to here
> 
> Please fix this,
> 
> I just checked against plain sm8650.dtsi and actually the memory 
> adresses are the same.
> 
> So what's the _real_ difference here ? Just drop the superfluous memory 
> zones and redefine them if needed.
With big reserved regions agreed, I think the memory map can be modified 
directly in sm8650.dtsi. It will be a memory map support different 
derived soc firmware release as well.
> 
> Thanks,
> Neil
> 
>> +
>> +        /* PIL region */
>> +        mpss_mem: mpss-region@8bc00000 {
>> +            reg = <0x0 0x8bc00000 0x0 0xf400000>;
>> +            no-map;
>> +        };
>> +
>> +        q6_mpss_dtb_mem: q6-mpss-dtb-region@9b000000 {
>> +            reg = <0x0 0x9b000000 0x0 0x80000>;
>> +            no-map;
>> +        };
>> +
>> +        ipa_fw_mem: ipa-fw-region@9b080000 {
>> +            reg = <0x0 0x9b080000 0x0 0x10000>;
>> +            no-map;
>> +        };
>> +
>> +        ipa_gsi_mem: ipa-gsi-region@9b090000 {
>> +            reg = <0x0 0x9b090000 0x0 0xa000>;
>> +            no-map;
>> +        };
>> +
>> +        gpu_micro_code_mem: gpu-micro-code-region@9b09a000 {
>> +            reg = <0x0 0x9b09a000 0x0 0x2000>;
>> +            no-map;
>> +        };
>> +
>> +        spss_region_mem: spss-region@9b0a0000 {
>> +            reg = <0x0 0x9b0a0000 0x0 0x1e0000>;
>> +            no-map;
>> +        };
>> +
>> +        spu_secure_shared_memory_mem: 
>> spu-secure-shared-memory-region@9b280000 {
>> +            reg = <0x0 0x9b280000 0x0 0x80000>;
>> +            no-map;
>> +        };
>> +
>> +        camera_mem: camera-region@9b300000 {
>> +            reg = <0x0 0x9b300000 0x0 0x800000>;
>> +            no-map;
>> +        };
>> +
>> +        video_mem: video-region@9bb00000 {
>> +            reg = <0x0 0x9bb00000 0x0 0x800000>;
>> +            no-map;
>> +        };
>> +
>> +        cvp_mem: cvp-region@9c300000 {
>> +            reg = <0x0 0x9c300000 0x0 0x700000>;
>> +            no-map;
>> +        };
>> +
>> +        cdsp_mem: cdsp-region@9ca00000 {
>> +            reg = <0x0 0x9ca00000 0x0 0x1400000>;
>> +            no-map;
>> +        };
>> +
>> +        q6_cdsp_dtb_mem: q6-cdsp-dtb-region@9de00000 {
>> +            reg = <0x0 0x9de00000 0x0 0x80000>;
>> +            no-map;
>> +        };
>> +
>> +        q6_adsp_dtb_mem: q6-adsp-dtb-region@9de80000 {
>> +            reg = <0x0 0x9de80000 0x0 0x80000>;
>> +            no-map;
>> +        };
>> +
>> +        adspslpi_mem: adspslpi-region@9df00000 {
>> +            reg = <0x0 0x9df00000 0x0 0x4080000>;
>> +            no-map;
>> +        };
>> +
>> +        /* Firmware related regions */
>> +        reserved-region@d8000000 {
>> +            reg = <0x0 0xd8000000 0x0 0x28000000>;
>> +            no-map;
>> +        };
>> +
>> +    };
>> +};
> 

-- 
Thx and BRs,
Aiqun(Maria) Yu