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[79.52.250.20]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-4290c74a698sm184004695e9.21.2024.08.12.03.10.02 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 12 Aug 2024 03:10:04 -0700 (PDT) Message-ID: <66b9df7c.050a0220.3574aa.d5bb@mx.google.com> X-Google-Original-Message-ID: Date: Mon, 12 Aug 2024 12:10:03 +0200 From: Christian Marangi To: Miquel Raynal Cc: Ulf Hansson , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Richard Weinberger , Vignesh Raghavendra , Joern Engel , Keith Busch , Jens Axboe , Christoph Hellwig , Sagi Grimberg , Saravana Kannan , Thomas Bogendoerfer , Wolfram Sang , Florian Fainelli , linux-mmc@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-mtd@lists.infradead.org, linux-nvme@lists.infradead.org Subject: Re: [PATCH v4 0/7] mtd: improve block2mtd + airoha parser References: <20240809172106.25892-1-ansuelsmth@gmail.com> <20240812104954.1e8d55f7@xps-13> Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20240812104954.1e8d55f7@xps-13> On Mon, Aug 12, 2024 at 10:49:54AM +0200, Miquel Raynal wrote: > Hi Christian, > > ansuelsmth@gmail.com wrote on Fri, 9 Aug 2024 19:20:58 +0200: > > > This small series handle 2 problems. > > > > It does try to ""standardize"" the usage of block2mtd module with > > MTD OF nodes. > > > > It is very easy to add support for MTD parser by just adding an > > OF node to the mtd created for block2mtd. > > > > This apply only if the root block is used for block2mtd to allow > > scenario where the full eMMC or an NVME is used for MTD and it doesn't > > have any partition table. > > > > To also support NVME, similar to how it's done with eMMC, we introduce > > a subnode to the NVME controller that needs to have the "nvme-card" > > compatible where a dev can define fixed-paritions for MTD parser usage. > > > > This series also add support for the Airoha partition table where > > the last partition is always ART and is placed at the end of the flash. > > > > This require dynamic calculation of the offset as some dedicated > > driver for bad block management might be used that reserve some space > > at the end of the flash for block accounting. > > Who is reserving this space? And this is not reflected anywhere in the > partition table? > To be more precise Mediatek use a custom way to handle bad blocks called BMT where they reserve and store data at the end of the nand. This is loaded before the flash driver controller so when MTD is init, the size is already reduced. The reserved space can change and it really depends on the tuned values hence it may change. > > New aarch64 Airoha SoC make use of this partition table and use block2mtd > > for eMMC to treat them as MTD with custom bad block management and block > > tracking. > > I am sorry, I am not used to such use cases, and I really fail getting > why you would like to use mtd with an eMMC. Can you explain a little > bit more what is not available in the block world that you really need > from mtd? Since vendor needs more space and doesn't want to adapt to block world, they are starting to use eMMC or block devices in general unpartitioned and raw and using block2mtd to simulate it. They don't care about the performance penalities as it's something read at boot time and only new firmware or some config files are written. Is it more clear now? > > Also, did you consider nvmem layouts instead to detect and define the > ART area? (just asking). > They still need a MTD partition and most of the time userspace tool are used on the ART partition. Using block2mtd and DT support will permit the use of nvmem cell as a side effect (and that is a missive bonus point of this honestly) -- Ansuel