[PATCH 2/3] dt-bindings: dma: snps,dw-axi-dmac: Add iommu property

[PATCH 2/3] dt-bindings: dma: snps,dw-axi-dmac: Add iommu property

[Khairul Anuar Romli]

Add iommu as an optional property that can be added to the snps,dw-axi-dmac
compatible node.

Signed-off-by: Adrian Ng Ho Yin <adrianhoyin.ng@altera.com>
Signed-off-by: Khairul Anuar Romli <khairul.anuar.romli@altera.com>
---
 Documentation/devicetree/bindings/dma/snps,dw-axi-dmac.yaml | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/Documentation/devicetree/bindings/dma/snps,dw-axi-dmac.yaml b/Documentation/devicetree/bindings/dma/snps,dw-axi-dmac.yaml
index 935735a59afd..a393a33c8908 100644
--- a/Documentation/devicetree/bindings/dma/snps,dw-axi-dmac.yaml
+++ b/Documentation/devicetree/bindings/dma/snps,dw-axi-dmac.yaml
@@ -42,6 +42,9 @@ properties:
     minItems: 1
     maxItems: 8
 
+  iommus:
+    maxItems: 1
+
   clocks:
     items:
       - description: Bus Clock
-- 
2.35.3

[PATCH v3 0/3] Add iommu supports

[Khairul Anuar Romli]

This patch series adds IOMMU support for the Agilex5 platform by:

- Updating the device tree bindings for:
  - Cadence HP NAND controller (`cdns,hp-nfc`)
  - Synopsys DesignWare AXI DMA controller (`snps,dw-axi-dmac`)
  to accept the `iommus` property.

- Adding the SMMU (System Memory Management Unit) node to the Agilex5
  device tree and wiring up the IOMMU properties to the supported
  peripherals:
  - NAND controller
  - DMA controller
  - SPI controller

The Agilex5 SoC includes an ARM SMMU v3 with dedicated Translation Buffer
Units (TBUs) for peripherals. These allow for hardware-enforced DMA
address translation and memory isolation using the IOMMU framework.

Enabling IOMMU support ensures proper integration of these devices in
virtualized or secure environments, and aligns the platform with ARM’s
architectural requirements.

---
Changes in v3:
	- Refined commit messages with detailed hardware descriptions.
	- Clarified which peripherals are covered in the DT changes.
Changes in v2:
	- Add more description in the commit message body to clarify
	  device required for this changes.
---
Khairul Anuar Romli (3):
  dt-bindings: mtd: cdns,hp-nfc: Add iommu property
  dt-bindings: dma: snps,dw-axi-dmac: Add iommu property
  arm64: dts: socfpga: agilex5: Add SMMU nodes

 .../bindings/dma/snps,dw-axi-dmac.yaml           |  3 +++
 .../devicetree/bindings/mtd/cdns,hp-nfc.yaml     |  3 +++
 arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi   | 16 ++++++++++++++++
 3 files changed, 22 insertions(+)

-- 
2.35.3

[PATCH v3 1/3] dt-bindings: mtd: cdns,hp-nfc: Add iommu property

[Khairul Anuar Romli]

Agilex5 integrates an ARM SMMU (System Memory Management Unit) with
Translation Buffer Units (TBUs) assigned to various peripherals,
including the NAND controller.

The Cadence HP NAND controller ("cdns,hp-nfc") on Agilex5 is behind a
TBU connected to the system's SMMUv3. To support this, the controller
requires an `iommus` property in the device tree to properly configure
address translation through the IOMMU framework.

Adding the `iommus` property to the binding schema allows the OS
to associate the NAND controller with its corresponding SMMU stream ID.
This enables:
- DMA address translation between the controller and system memory
- Memory protection for NAND operations
- Proper functioning of the IOMMU framework in secure or virtualized
  environments

This change documents the IOMMU integration for the NAND controller
on platforms like Agilex5 where such hardware is present.

Signed-off-by: Adrian Ng Ho Yin <adrianhoyin.ng@altera.com>
Signed-off-by: Khairul Anuar Romli <khairul.anuar.romli@altera.com>
---
Changes in v3:
	- Refined commit messages with detailed hardware descriptions.
	- Remove redundant commit message and add the hardware used for
	  iommu.
Changes in v2:
	- Updated the commit message to clarify the need for the changes
	  and the hardware used of this changes.
---
 Documentation/devicetree/bindings/mtd/cdns,hp-nfc.yaml | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/Documentation/devicetree/bindings/mtd/cdns,hp-nfc.yaml b/Documentation/devicetree/bindings/mtd/cdns,hp-nfc.yaml
index e1f4d7c35a88..73dc69cee4d8 100644
--- a/Documentation/devicetree/bindings/mtd/cdns,hp-nfc.yaml
+++ b/Documentation/devicetree/bindings/mtd/cdns,hp-nfc.yaml
@@ -40,6 +40,9 @@ properties:
   dmas:
     maxItems: 1
 
+  iommus:
+    maxItems: 1
+
   cdns,board-delay-ps:
     description: |
       Estimated Board delay. The value includes the total round trip
-- 
2.35.3

[PATCH 2/3] dt-bindings: dma: snps,dw-axi-dmac: Add iommu property

[Khairul Anuar Romli]

Agilex5 integrates an ARM SMMU v3 (System Memory Management Unit) with
dedicated Translation Buffer Units (TBUs) assigned to various peripherals,
including the Synopsys DesignWare AXI DMA controller.

Each TBU handles address translation for its associated device by mapping
stream IDs to memory access permissions and virtual-to-physical address
mappings via the SMMU core.

The DesignWare AXI DMAC instances on Agilex5 are connected to their
respective TBUs. These TBUs forward DMA transactions from the controller
through the SMMU, enabling IOMMU-based features such as:
- Address translation for DMA operations
- Isolation and protection of memory regions accessed by the DMA controller
- Support for secure and virtualized environments through enforced access
  control

To support this configuration, the `iommus` property must be added to the
binding schema for `snps,dw-axi-dmac`. This allows the device tree to
associate each DMA controller with the correct SMMU stream ID, enabling
the Linux IOMMU framework to configure translation contexts at runtime.

This change documents the IOMMU support for the DMA controller on Agilex5
and allows proper integration with the SMMUv3 hardware.

Signed-off-by: Adrian Ng Ho Yin <adrianhoyin.ng@altera.com>
Signed-off-by: Khairul Anuar Romli <khairul.anuar.romli@altera.com>
---
Changes in v3:
	- Refined commit messages with detailed hardware descriptions.
	- Remove redundant commit message and add hardware use for iommu.
Changes in v2:
        - Updated the commit message to clarify the need for the changes
	  and the hardware used of this changes.
---
 Documentation/devicetree/bindings/dma/snps,dw-axi-dmac.yaml | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/Documentation/devicetree/bindings/dma/snps,dw-axi-dmac.yaml b/Documentation/devicetree/bindings/dma/snps,dw-axi-dmac.yaml
index 935735a59afd..a393a33c8908 100644
--- a/Documentation/devicetree/bindings/dma/snps,dw-axi-dmac.yaml
+++ b/Documentation/devicetree/bindings/dma/snps,dw-axi-dmac.yaml
@@ -42,6 +42,9 @@ properties:
     minItems: 1
     maxItems: 8
 
+  iommus:
+    maxItems: 1
+
   clocks:
     items:
       - description: Bus Clock
-- 
2.35.3

[PATCH 3/3] arm64: dts: socfpga: agilex5: Add SMMU nodes

[Khairul Anuar Romli]

Agilex5 includes an ARM SMMU v3 (System Memory Management Unit) to provide
address translation and memory protection for DMA-capable devices such as
PCIe, USB, and other peripherals.

This commit adds the SMMU node to the Agilex5 device tree with compatible
string "arm,smmu-v3", along with its register space and interrupts.

The SMMU is required to:
- Enable DMA address translation for devices that cannot directly access
  the full physical memory space.
- Provide isolation and memory protection by restricting device access
  to specific regions of memory, improving system security.
- Support virtualization use cases by enabling safe and isolated device
  passthrough to guest VMs.
- Align with ARM platform architecture requirements for IOMMU support.

By describing the SMMU in the device tree, the Linux IOMMU framework
can probe and initialize it during boot. Devices in the system can then
bind to the SMMU via the `iommus` property, enabling memory translation
and protection features as expected.

The following devices are updated to reference the SMMU:
- NAND controller
- DMA controller
- SPI controller

This change is a necessary step toward full enablement high-speed
peripherals on Agilex5.

Signed-off-by: Adrian Ng Ho Yin <adrianhoyin.ng@altera.com>
Signed-off-by: Khairul Anuar Romli <khairul.anuar.romli@altera.com>
---
Changes in v3:
	- Rewrite commit messages with detailed hardware descriptions.
Changes in v2:
	- Follow revision of the patch series from v1->v2.
---
 arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi | 16 ++++++++++++++++
 1 file changed, 16 insertions(+)

diff --git a/arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi b/arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi
index 04e99cd7e74b..a22cf6a211e2 100644
--- a/arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi
+++ b/arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi
@@ -272,6 +272,7 @@ nand: nand-controller@10b80000 {
 			interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
 			clocks = <&clkmgr AGILEX5_NAND_NF_CLK>;
 			cdns,board-delay-ps = <4830>;
+			iommus = <&smmu 4>;
 			status = "disabled";
 		};
 
@@ -298,6 +299,7 @@ dmac0: dma-controller@10db0000 {
 			snps,block-size = <32767 32767 32767 32767>;
 			snps,priority = <0 1 2 3>;
 			snps,axi-max-burst-len = <8>;
+			iommus = <&smmu 8>;
 		};
 
 		dmac1: dma-controller@10dc0000 {
@@ -315,6 +317,7 @@ dmac1: dma-controller@10dc0000 {
 			snps,block-size = <32767 32767 32767 32767>;
 			snps,priority = <0 1 2 3>;
 			snps,axi-max-burst-len = <8>;
+			iommus = <&smmu 9>;
 		};
 
 		rst: rstmgr@10d11000 {
@@ -323,6 +326,18 @@ rst: rstmgr@10d11000 {
 			#reset-cells = <1>;
 		};
 
+		smmu: iommu@16000000 {
+			compatible = "arm,smmu-v3";
+			reg = <0x16000000 0x30000>;
+			interrupts = <GIC_SPI 134 IRQ_TYPE_EDGE_RISING>,
+				     <GIC_SPI 129 IRQ_TYPE_EDGE_RISING>,
+				     <GIC_SPI 132 IRQ_TYPE_EDGE_RISING>;
+			interrupt-names = "eventq", "gerror", "priq";
+			dma-coherent;
+			#iommu-cells = <1>;
+			status = "disabled";
+		};
+
 		spi0: spi@10da4000 {
 			compatible = "snps,dw-apb-ssi";
 			reg = <0x10da4000 0x1000>;
@@ -423,6 +438,7 @@ usb0: usb@10b00000 {
 			phy-names = "usb2-phy";
 			resets = <&rst USB0_RESET>, <&rst USB0_OCP_RESET>;
 			reset-names = "dwc2", "dwc2-ecc";
+			iommus = <&smmu 6>;
 			clocks = <&clkmgr AGILEX5_USB2OTG_HCLK>;
 			clock-names = "otg";
 			status = "disabled";
-- 
2.35.3

Re: [PATCH v3 1/3] dt-bindings: mtd: cdns,hp-nfc: Add iommu property

[Krzysztof Kozlowski]

On Wed, Oct 15, 2025 at 08:13:37AM +0800, Khairul Anuar Romli wrote:
> Agilex5 integrates an ARM SMMU (System Memory Management Unit) with
> Translation Buffer Units (TBUs) assigned to various peripherals,
> including the NAND controller.
> 
> The Cadence HP NAND controller ("cdns,hp-nfc") on Agilex5 is behind a
> TBU connected to the system's SMMUv3. To support this, the controller
> requires an `iommus` property in the device tree to properly configure
> address translation through the IOMMU framework.
> 
> Adding the `iommus` property to the binding schema allows the OS
> to associate the NAND controller with its corresponding SMMU stream ID.
> This enables:
> - DMA address translation between the controller and system memory
> - Memory protection for NAND operations
> - Proper functioning of the IOMMU framework in secure or virtualized
>   environments
> 
> This change documents the IOMMU integration for the NAND controller
> on platforms like Agilex5 where such hardware is present.
> 
> Signed-off-by: Adrian Ng Ho Yin <adrianhoyin.ng@altera.com>
> Signed-off-by: Khairul Anuar Romli <khairul.anuar.romli@altera.com>
> ---
> Changes in v3:
> 	- Refined commit messages with detailed hardware descriptions.
> 	- Remove redundant commit message and add the hardware used for
> 	  iommu.
> Changes in v2:
> 	- Updated the commit message to clarify the need for the changes
> 	  and the hardware used of this changes.
> ---
>  Documentation/devicetree/bindings/mtd/cdns,hp-nfc.yaml | 3 +++
>  1 file changed, 3 insertions(+)

Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>

Best regards,
Krzysztof

Re: [PATCH 2/3] dt-bindings: dma: snps,dw-axi-dmac: Add iommu property

[Krzysztof Kozlowski]

On 15/10/2025 02:13, Khairul Anuar Romli wrote:
> Agilex5 integrates an ARM SMMU v3 (System Memory Management Unit) with
> dedicated Translation Buffer Units (TBUs) assigned to various peripherals,
> including the Synopsys DesignWare AXI DMA controller.
> 
> Each TBU handles address translation for its associated device by mapping
> stream IDs to memory access permissions and virtual-to-physical address
> mappings via the SMMU core.
> 
> The DesignWare AXI DMAC instances on Agilex5 are connected to their
> respective TBUs. These TBUs forward DMA transactions from the controller
> through the SMMU, enabling IOMMU-based features such as:
> - Address translation for DMA operations
> - Isolation and protection of memory regions accessed by the DMA controller
> - Support for secure and virtualized environments through enforced access
>   control
> 
> To support this configuration, the `iommus` property must be added to the
> binding schema for `snps,dw-axi-dmac`. This allows the device tree to
> associate each DMA controller with the correct SMMU stream ID, enabling
> the Linux IOMMU framework to configure translation contexts at runtime.
> 
> This change documents the IOMMU support for the DMA controller on Agilex5
> and allows proper integration with the SMMUv3 hardware.
> 
> Signed-off-by: Adrian Ng Ho Yin <adrianhoyin.ng@altera.com>
> Signed-off-by: Khairul Anuar Romli <khairul.anuar.romli@altera.com>
> ---
> Changes in v3:
> 	- Refined commit messages with detailed hardware descriptions.
> 	- Remove redundant commit message and add hardware use for iommu.
> Changes in v2:
>         - Updated the commit message to clarify the need for the changes
> 	  and the hardware used of this changes.
> ---
>  Documentation/devicetree/bindings/dma/snps,dw-axi-dmac.yaml | 3 +++
>  1 file changed, 3 insertions(+)

Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>

Best regards,
Krzysztof

Re: [PATCH v3 0/3] Add iommu supports

[Dinh Nguyen]

On 10/14/25 19:13, Khairul Anuar Romli wrote:
> This patch series adds IOMMU support for the Agilex5 platform by:
> 
> - Updating the device tree bindings for:
>    - Cadence HP NAND controller (`cdns,hp-nfc`)
>    - Synopsys DesignWare AXI DMA controller (`snps,dw-axi-dmac`)
>    to accept the `iommus` property.
> 
> - Adding the SMMU (System Memory Management Unit) node to the Agilex5
>    device tree and wiring up the IOMMU properties to the supported
>    peripherals:
>    - NAND controller
>    - DMA controller
>    - SPI controller
> 
> The Agilex5 SoC includes an ARM SMMU v3 with dedicated Translation Buffer
> Units (TBUs) for peripherals. These allow for hardware-enforced DMA
> address translation and memory isolation using the IOMMU framework.
> 
> Enabling IOMMU support ensures proper integration of these devices in
> virtualized or secure environments, and aligns the platform with ARM’s
> architectural requirements.
> 
> ---
> Changes in v3:
> 	- Refined commit messages with detailed hardware descriptions.
> 	- Clarified which peripherals are covered in the DT changes.
> Changes in v2:
> 	- Add more description in the commit message body to clarify
> 	  device required for this changes.
> ---
> Khairul Anuar Romli (3):
>    dt-bindings: mtd: cdns,hp-nfc: Add iommu property
>    dt-bindings: dma: snps,dw-axi-dmac: Add iommu property
>    arm64: dts: socfpga: agilex5: Add SMMU nodes
> 

Applied!

Thanks,
Dinh